Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 61825

Article: 61825
Subject: Re: Quartus 2.2, SOPC builder and leonardo
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 13 Oct 2003 11:17:37 -0700
Links: << >>  << T >>  << A >>
Mancini Stephane wrote:
> Hi all,
> I'm wondering how to synthesize the VHDL from SOPC Builder of quartus 2.2
> with Leonardo.
> Indeed, I would like to perform a synthesis separated from the Quartus P&R
> for a course (I have a limited time and doing the both is far too long).
> The idea is to provide students an already synthesized system : they just
> have to complete some peripherals so I can pre-synthesize the whole system
> , students do synthesize peripherals and the pieces are put together for P&R with quartus.


Consider leaving the sopc code alone.

Write and sim the peripheral code separately in my_wrapper.vhd.
In this code, include an unbound component
instance representing connections to the sopc top level entity.

Compile my_wrapper.vhd in leo to make my_wrapper.edf.
Add my_wrapper.edf to the quartus file list containing the sopc files.


  -- Mike Treseler



Article: 61826
Subject: Re: PCI-X bridge from Xilinx LogiCORE and half bridge
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Mon, 13 Oct 2003 11:49:27 -0700
Links: << >>  << T >>  << A >>

Hello,

To get a better answer, you'll have to be more specific
about what you want to build.  Are you trying to build a
fully compliant PCI(-X) to PCI(-X) bridge?  If that is
the case, you should buy an ASSP to do the job.

The Xilinx PCI and PCI-X LogiCOREs, as you might buy them
over the web, have Type 0 configuration spaces and are not
suitable for compliant bridging applications.  However,
there are other options and it depends on what you are
trying to do.

What exactly are you trying to do?
Eric

> Hi.
>
> I'm considering Xilinx LogiCORE PCI-X core, and Xilinx
> HalfBridge core for building a PCI-X bridge.
> 
> Can anyone share experience with these cores for PCI bridge
> application?  Does these cores deal with the address
> translation from "type 1" to "type 0" ?
> 
> ThankX
> NAHUM

Article: 61827
Subject: Re: How to select a FPGA
From: "Vinh Pham" <a@a.a>
Date: Mon, 13 Oct 2003 19:16:04 GMT
Links: << >>  << T >>  << A >>
> I've almost finished the RTL for the design.

Do you mean you're almost finish writing the HDL?  If so the easiest thing
to do is send it through your synthesizer and see what logic usage it
reports.

If you haven't written the HDL, the next question is whether you think you
have enough time to write the HDL before having to make a decission on a
FPGA.  The HDL doesn't have to be functionally correct, so you don't have to
waste time debugging it.  You just have to make sure the synthesizer isn't
optimizing logic away due to a coding error.  You still have to make a
ballpark guess so you can do a sanity check on what the synthesizer reports.

I'm not sure if the following situation applies to you but here goes:

If the PCB folks need a decission sooner, then you gotta make an educated
guess and tack on some safety margin.  If you're lucky, there is a previous
design which is very similar to yours, that you can use.  If there's a lot
of reptitive logic, that can make it easier since you just figure out the
size of one block and multiply by how often it's instantiated.  If your
design is datapath heavy, then concentrate more on the datapath logic and
make a rough guess for your control logic.

Also remember that a lot of FPGAs come in different sizes (logic wise) but
have the same packaging/PCB-footprint.  So you can give the PCB folks a
package that they can start working with, while you have some freedom in
picking a size.  If your design turns out to be larger than you guess, you
might be able to choose a larger size FPGA in the same package.  You have to
make sure such a larger part exists, what the lead time is, and the price.
Be sure to ask your chip vendor for that information on all the sizes in a
given package.  Also remember that when it comes to choosing a package, the
main thing is to make sure it has enough I/O for your needs, so usually you
worry about I/O first, then logic.


--Vinh



Article: 61828
Subject: ByteBlasterII
From: ivansimoes@msn.com (Ivan)
Date: 13 Oct 2003 14:12:51 -0700
Links: << >>  << T >>  << A >>
Has anyone used a non altera byteblasterII scheme for loading serial
configuration device (EPSC1 or EPCS4)? I found two reference on the
net but I couldn't implement then yet, I don't know if they work.

reference:

  http://www.hdl.co.jp/tp2/
  http://fishing.gptel.ru/sm/ByteBlasterII.pdf

I'd appreciate any help

Thanks

Ivan

Article: 61829
Subject: Re: VCC's HOTman
From: machosri@yahoo.com (Sriram)
Date: 13 Oct 2003 14:18:45 -0700
Links: << >>  << T >>  << A >>
Dear Mr.Casselman,
Thanks for replying to my message ,and no i did not get the license
file.
Also I dont want to do remote hardware upgrade,I just want to write to
the FPGA using C++ hardware objects.
As I wrote in earlier I'm not able to run the HOTman application even
after following the steps for first time use (like updating the batch
file etc ..)

Do help me out.
Thanks,
Sriram 
 "Steve Casselman" <sc_nospam@vcc.com> wrote in message news:<pzBib.870$sb7.162658550@newssvr21.news.prodigy.com>...
> There is a date coded license file did you ever get that? So the HOTMan
> software allows you to download remotely and it has a "plugin" technology
> that allows you to get inbetween the delievery of the bitstream and the
> final destination. It has examples of how to use the Xilinx download cable
> and it also has Jtag functions. HOTMan also lets you make your own commands
> so you can build test software for your system.
> 
> With just a few lines of code you can deliver your bitstream run some kind
> of test and then the software will ship back a message that you create. And
> it will work over the net so you can run it from your office and download
> into the lab.
> 
> Let me know if you have problems.
> 
> Steve
> 
> "Sriram" <machosri@yahoo.com> wrote in message
> news:56210527.0310101012.5ec866c2@posting.google.com...
> > Hi ,
> > I downloaded HOTman from Virtual Computing corporation around April'03
> > but when I tried to open the console now it didnt work.Also I went
> > through the procedure again for running HOTman the first time and
> > still couldnt get the GUI to appear.I got the error message "Could not
> > find main class" when I double clicked on the Hotman.jar file.
> >
> > Is this a problem of JRE or is the software HOTman no longer working.
> > I also tried to download the evaluation edition again from the VCC
> > website and couldnt do it(got an internal server error problem).Have
> > they closed the site ?
> >
> > Has anybody faced similar problems with HOTman?
> > Also to implement programs from C directly to FPGA would Celoxica's
> > HandelC oriented DK1-design Suite be the next best option,if I cant
> > get HOTman working.
> >
> >
> > Kindly do help me out on the above.
> >
> > Thanks ,
> > Sriram

Article: 61830
Subject: mp3 project
From: "SneakerNet" <nospam@nospam.org>
Date: Tue, 14 Oct 2003 10:27:10 +1300
Links: << >>  << T >>  << A >>
Hi All

Has anyone done/come across a mp3 personal project which is done using FPGA
with added circuitry. Please let me know. I'm looking at making one myself
and would like some added help.

Right now i'm doing research on it, so any info pls pass it on.

Kind Regards





Article: 61831
Subject: Xilinx "Programming failed" message
From: circaeng@hotmail.com (Patrick Robin)
Date: 13 Oct 2003 15:27:48 -0700
Links: << >>  << T >>  << A >>
Hello,

I have been using Web ISE for over a year to program  Xilinx CPLDs
XC9572XL

Everything was working fine for hundreds of units until my computer
crashed and I had to resinstall ISE. I now get a "Programming failed"
error. Everything else seems to work as far as communicating with the
chip using the parallel cable. Impact detects the chip, I can query
the ID compute the checksum (zero) and erase it fine.

But I get the "Programming failed error" when I try to program chips.
I tried a number of brand new CPLDs. Is there a way to get more
specific error messages. At this point there are many variables since
I had to resintall Windows XP and ISE.

I tried these versions of web ISE: 5.1, 5.2 and 6.1.


The version I had working before I crashed was probably 5.2 since I
downloaded mid june 2003.

Is it possible for the cable to only fail during program and
everything else works? Any specifie signals I need to check?

I recreated the .jed file with ISE 6.1 to make sure is wasn't
corrupted.

Any help appreciated.

Thank You

 Patrick

Article: 61832
Subject: Re: mp3 project
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 13 Oct 2003 22:31:44 GMT
Links: << >>  << T >>  << A >>
The first stop for research I'd recommend would be

  http://groups.google.com

then search with

  mp3 group:comp.arch.fpga

and you'll get a bunch of hits from people who have taked about doing this,
perhaps some who already have.  If nothing else, you'll get a flavor for
some of the issues surrounding an FPGA based mp3.


"SneakerNet" <nospam@nospam.org> wrote in message
news:PMEib.177545$JA5.4451689@news.xtra.co.nz...
> Hi All
>
> Has anyone done/come across a mp3 personal project which is done using
FPGA
> with added circuitry. Please let me know. I'm looking at making one myself
> and would like some added help.
>
> Right now i'm doing research on it, so any info pls pass it on.
>
> Kind Regards



Article: 61833
Subject: Re: VCC's HOTman
From: "Steve Casselman" <sc_nospam@vcc.com>
Date: Mon, 13 Oct 2003 22:41:23 GMT
Links: << >>  << T >>  << A >>
This software allows you to encapsulate a bitstream and do remote upgrades.
It does not use C++ as a a hardware description language. I think what you
want is

http://rcc.lanl.gov/Tools/Streams-C/index.php

Steve



"Sriram" <machosri@yahoo.com> wrote in message
news:56210527.0310131318.23e6c957@posting.google.com...
> Dear Mr.Casselman,
> Thanks for replying to my message ,and no i did not get the license
> file.
> Also I dont want to do remote hardware upgrade,I just want to write to
> the FPGA using C++ hardware objects.
> As I wrote in earlier I'm not able to run the HOTman application even
> after following the steps for first time use (like updating the batch
> file etc ..)
>
> Do help me out.
> Thanks,
> Sriram
>  "Steve Casselman" <sc_nospam@vcc.com> wrote in message
news:<pzBib.870$sb7.162658550@newssvr21.news.prodigy.com>...
> > There is a date coded license file did you ever get that? So the HOTMan
> > software allows you to download remotely and it has a "plugin"
technology
> > that allows you to get inbetween the delievery of the bitstream and the
> > final destination. It has examples of how to use the Xilinx download
cable
> > and it also has Jtag functions. HOTMan also lets you make your own
commands
> > so you can build test software for your system.
> >
> > With just a few lines of code you can deliver your bitstream run some
kind
> > of test and then the software will ship back a message that you create.
And
> > it will work over the net so you can run it from your office and
download
> > into the lab.
> >
> > Let me know if you have problems.
> >
> > Steve
> >
> > "Sriram" <machosri@yahoo.com> wrote in message
> > news:56210527.0310101012.5ec866c2@posting.google.com...
> > > Hi ,
> > > I downloaded HOTman from Virtual Computing corporation around April'03
> > > but when I tried to open the console now it didnt work.Also I went
> > > through the procedure again for running HOTman the first time and
> > > still couldnt get the GUI to appear.I got the error message "Could not
> > > find main class" when I double clicked on the Hotman.jar file.
> > >
> > > Is this a problem of JRE or is the software HOTman no longer working.
> > > I also tried to download the evaluation edition again from the VCC
> > > website and couldnt do it(got an internal server error problem).Have
> > > they closed the site ?
> > >
> > > Has anybody faced similar problems with HOTman?
> > > Also to implement programs from C directly to FPGA would Celoxica's
> > > HandelC oriented DK1-design Suite be the next best option,if I cant
> > > get HOTman working.
> > >
> > >
> > > Kindly do help me out on the above.
> > >
> > > Thanks ,
> > > Sriram



Article: 61834
Subject: Re: mp3 project
From: "SneakerNet" <nospam@nospam.org>
Date: Tue, 14 Oct 2003 11:51:04 +1300
Links: << >>  << T >>  << A >>
Hi John
I now remember that Altera provided a mp3 project with their Nios
Development Kit (APEX Edition). I wonder where I can find the source code
for that.

Thanks ;o)


"John_H" <johnhandwork@mail.com> wrote in message
news:kJFib.7$4d7.2653@news-west.eli.net...
> The first stop for research I'd recommend would be
>
>   http://groups.google.com
>
> then search with
>
>   mp3 group:comp.arch.fpga
>
> and you'll get a bunch of hits from people who have taked about doing
this,
> perhaps some who already have.  If nothing else, you'll get a flavor for
> some of the issues surrounding an FPGA based mp3.
>
>
> "SneakerNet" <nospam@nospam.org> wrote in message
> news:PMEib.177545$JA5.4451689@news.xtra.co.nz...
> > Hi All
> >
> > Has anyone done/come across a mp3 personal project which is done using
> FPGA
> > with added circuitry. Please let me know. I'm looking at making one
myself
> > and would like some added help.
> >
> > Right now i'm doing research on it, so any info pls pass it on.
> >
> > Kind Regards
>
>



Article: 61835
Subject: Re: Spartan 3 pinout typo?
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Mon, 13 Oct 2003 16:05:50 -0700
Links: << >>  << T >>  << A >>
The Spartan-3 pinout tables have now been updated to correct this mistake.
The mistake in the data sheet is strictly the bank indication in the pinout
table.  The pin name and pin number in the data sheet is correct as is the
PQ208 footprint diagram.

The correct information for the PQ208 footprint table is available via
either of the following two links.

Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)
http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf

Spartan-3 Complete Data Sheet (All four modules)
http://direct.xilinx.com/bvdocs/publications/ds099.pdf

The electronic ASCII-text footprint tables were not affected by this
mistake.
http://direct.xilinx.com/bvdocs/publications/s3_pin.zip

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC


"Jake Janovetz" <jakespambox@yahoo.com> wrote in message
news:d6ad3144.0310082043.43d07d9a@posting.google.com...
> Hi folks-
>
> This isn't a significant note, but it seems there is a slight typo in
> the PQ208 package pinout for the Spartan 3.  Namely, Bank 1 includes
> the following that I believe should be listed as Bank 0:
>
> IO_L32N_0/GCLK7
> IO_L32P_0/GCLK6
>
> Although the suffix (_0) indicates they belong in Bank 0, I wanted to
> make sure they follow Bank 0 power supplies.  Also, the table at the
> end of the listing puts two GCLKs in Bank0 and two in Bank1, so that
> seems to reinforce the typo.
>
> Correction?
>
>    Jake



Article: 61836
Subject: Re: Spartan 3 pinout typo?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 13 Oct 2003 22:23:33 -0400
Links: << >>  << T >>  << A >>
"Steven K. Knapp" wrote:
> 
> The Spartan-3 pinout tables have now been updated to correct this mistake.
> The mistake in the data sheet is strictly the bank indication in the pinout
> table.  The pin name and pin number in the data sheet is correct as is the
> PQ208 footprint diagram.
> 
> The correct information for the PQ208 footprint table is available via
> either of the following two links.
> 
> Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)
> http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf
> 
> Spartan-3 Complete Data Sheet (All four modules)
> http://direct.xilinx.com/bvdocs/publications/ds099.pdf
> 
> The electronic ASCII-text footprint tables were not affected by this
> mistake.
> http://direct.xilinx.com/bvdocs/publications/s3_pin.zip

Steven,

I am looking at partial/modular reconfiguration in Spartan 3 and I
realize that there are some issues with IO that I am not sure how to
resolve.  To get an understanding of how to approach the problem I need
to know what IO pads and pins are mapped to what CLB columns.  I am
looking at using the XC3S400 in the 456 pin BGA package.  Where can I
get info on how the IOs are mapped to the CLB columns?  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 61837
Subject: Re: mp3 project
From: "Henry" <otc_friend@gmx.net>
Date: Tue, 14 Oct 2003 04:37:38 +0200
Links: << >>  << T >>  << A >>
There was a project using a Atmel FPSLIC (=AVR+FPGA)vcfor all processing.
The FPGA realized a IDE interface and a 32-bit DSP (!) for decoding MP3 !
Don't know where but if you mail me I will see on my harddisk.
- Henry

SneakerNet schrieb in Nachricht ...
>Hi All
>
>Has anyone done/come across a mp3 personal project which is done using FPGA
>with added circuitry. Please let me know. I'm looking at making one myself
>and would like some added help.
>
>Right now i'm doing research on it, so any info pls pass it on.
>
>Kind Regards
>
>
>
>



Article: 61838
Subject: Pass transistor logic in a FPGA
From: nitinyogi@hotmail.com (Nitin)
Date: 13 Oct 2003 21:39:19 -0700
Links: << >>  << T >>  << A >>
Hi,
    I am a graduate student of Auburn Univeristy doing my research in
SoC testing. I am really an amateur in FPGAs and would like your help.
I have a question, which I think you people can answer. For my
research, I would like to implement a transmission gate into a FPGA.
Can it be done? If yes could you tell me how?

  Would really appreciate your help...


   Thanks
             Nitin

Article: 61839
Subject: Xilinx Logic Handbook
From: John <johnboy1231@bellsouth.net>
Date: Mon, 13 Oct 2003 22:07:53 -0700
Links: << >>  << T >>  << A >>
I would like to obtain a hard copy of the Programmable Logic 
Design Handbook (featuring FPGAs and CPLDs). I cannot find one 
listed on the Xilinx web site, though I might have missed it. 
The downloadable pdf probably works for most people, but I prefer 
having a book to thumb through. Thanks, 

John 



Article: 61840
Subject: Re: ISE6.1i RPM's, Multipliers and grids
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Tue, 14 Oct 2003 07:10:44 GMT
Links: << >>  << T >>  << A >>
"John_H" wrote:

>   Perhaps it's Floorplanner's ability to deal with RPM_GRIDs that's not
> ready for prime time?  I had great success with my manual UCF approach to
> get my registers placed relative to the BlockRAMs.  The RPM_GRID attribute
> is effectively assigned per-macro.  You can't have one macro with a mix of
> RPM_GRID and standard XY resource gridding.
>
> I didn't touch Floorplanner to get my grid locations.  I went straight to
> FPGA Editor to get the grid locations; you can find those by clicking on a
> slice or a multiplier and the RPM_GRID XnYm location is displayed with the
> other information for that resource.

I read XAPP416.  Here's one problem:

Page 3.
"The RLOC_ORIGIN attribute for an RPM Grid macro must be specified in terms
of RPM
Grid coordinates."

If you are right in that you cannot mix RPM_GRID with standard grid
nomenclature, then, does that mean that you must convert all of your old
RPM's to use RPM_GRID?  A top module might contain RPM's built out of other
RPM's.  How do you deal with that?

TOP ----- A ---- B (RPM_GRID used internally to B)
    \      \---- C standard grid
     \      \--- D standard grid
      \
       \--E (RPM_GRID based)

With regards to the Floorplanner.  I understand that the only way to get
RPM_GRID coordinates at the moment seems to be FPGA Editor.  Floorplanner is
a nice way to quickly look at a design and examine how things are layed out.
However, if you use RPM_GRID, immediately upon loading a design it pops-up a
window that says that it does not support the RPM_GRID system.  My question
is:  What does this mean?  Does this mean that it won't let you grab logic
and make one?  Or that it won't display one correctly?  What happens to all
the components that use the RPM_GRID?  Are they shown properly?  The message
all by itself, if you think about it is meaningless without further
information.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





Article: 61841
Subject: Re: Quartus II simulation question.
From: "Christos" <chris_saturnNOSPAM@hotmail.com>
Date: Tue, 14 Oct 2003 10:38:05 +0200
Links: << >>  << T >>  << A >>
Hi Subroto,

Thanks once again for your help, its working great.

Christos



"Subroto Datta" <sdatta@altera.com> wrote in message
news:ca4d800d.0310091159.10bc0751@posting.google.com...
> "Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message
news:<bm3agi$gr9$1@sunnews.cern.ch>...
> > Hi all,
> >
> > In the vector waveform file that I am creating to enter the inputs for
my
> > simulation I can also enter the outputs and the registers that I would
like
> > to be recorded.
> > There using the node finder I can enter some combinatorial signals that
I
> > would like to observe.
> > But after the simulation those signals have been omitted and the warning
has
> > been given :
> > "Warning: Ignored node in vector source file. Can't find corresponding
node
> > name CFCstatus in design."
> >
> > So, can someone please explain me how I can check those internal
signals?
> > For example the output of a lpm_compare block which feeds an input of a
> > counter without inserting in the middle a output pin? (you don't have to
use
> > this example of course).
> >
> > I thing it doesn't make any difference the version but I am using
Quartus II
> > 3.0.
> >
> > Thanks,
> > Christos
>
> Hi Christos,
>
>  To preserve a combinatorial node through synthesis, place and route,
> you should do one of the following:
>
> a) If it is a BDF (schematic file) or TDF (AHDL file), feed the signal
> that you are interested in observing into a LCELL primitive, and give
> the LCELL primitive an interesting name, so that you can find it when
> you choose the Post Compilation filter in the node finder. You should
> feed the output of the LCELL to where the signal wof interes was
> previously connected.
>
> b) If you are using VHDL or Verilog, consider using the keep
> pragma/keyword. Its usage is described in the online help. Search for
> "keep". The Verilog help panel is shown below:
>
> ------------------- keep usage in Verilog
> -----------------------------------
> A Verilog HDL language directive that directs Analysis & Synthesis to
> keep a particular wire intact. You can use this language directive to
> keep a combinational logic node so you can observe the node during
> simulation or with the SignalTapģ II Logic Analyzer.
>
> You cannot use this language directive for nodes that have no fan-out.
>
> To use the keep language directive, you can specify the keep language
> directive in a comment that is on the same line as the register you
> want Analysis & Synthesis to preserve. In the comment, precede the
> language directive with the synthesis keyword.
>
> For example, in the following code, the comment /* synthesis preserve
> */ directs Analysis & Synthesis to not minimize the keep_wire
> register:
>
> wire keep_wire /* synthesis keep */;
>
> --------------------------------------------------------------------------
-----
>
> You would search for keep_wire in the Mode Finder.
>
> Hope this helps.
>
> - Subroto Datta
> Altera Corp.



Article: 61842
Subject: Re: How to select a FPGA
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 14 Oct 2003 08:40:28 +0000 (UTC)
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:
: Here is a beginning.
: Look at your design:
: How many flip-flops, how many BlockRAMs, how many multipliers (if any),
: how many different clocks, and how many I/O?
: It should only take minutes to answer these questions. Then you look at
: the overview in the data sheet and select an FPGA that has at least what
: you need.

Also have a look at the package option and the availability too...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------


Article: 61843
Subject: FPGA/CPLD With Analog Functions?
From: "Josť F. da Rocha" <jose_rocha@yahoo.com>
Date: Tue, 14 Oct 2003 01:58:23 -0700
Links: << >>  << T >>  << A >>
Hello. 
Iím new at the FPGA/CPLDs world and Iím currently subscribed to 
receive Xilinx email communications. 

I would like to know if is there some FPGA/CPLD incorporating some 
few analog functions or analog blocks like instrumentation amplifiers, 
OPerational AMPlifiers/(analog amplification), ADCs (Analog-to-Digital-Converter) and DACs? 

Thank you very much if you are kindly enough to answer. 
(jose_rocha@yahoo.com) 



Article: 61844
Subject: problem with XC18v01 and Spartan XCS20XL
From: Dennis Binder <dennis.binder@ipm.fhg.de>
Date: Tue, 14 Oct 2003 11:18:28 +0200
Links: << >>  << T >>  << A >>
Hello,

we encounter problems with a XC18v01.
In which way is it possible, that the prom loses
information ?
Most time everything works fine. But after delivering
the mashine to the customer, the content of the XC18v01 has changed.
We have no idea how this can happen.
All the JTAG-Signals of the prom are left open and we supply the
whole electronic with two seperated external power-supplies (3.3V 5V).
3.3V for FPGA and Prom.
5V for the digital electronic which interfaces to the FPGA.

I would be glad if anybody can help !

Dennis


Article: 61845
Subject: Re: Xilinx S3 I/O robustness question
From: lecroy7200@chek.com (lecroy)
Date: 14 Oct 2003 03:34:17 -0700
Links: << >>  << T >>  << A >>
Surely as hard as you Xilinx guys pushed simulation as the answer for
this, you would know the details of the S3 models.  Are you looking
into it?  Is the part just to new and there is no information
available at your level?

Article: 61846
Subject: Re: ByteBlasterII
From: "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com>
Date: Tue, 14 Oct 2003 13:02:58 +0200
Links: << >>  << T >>  << A >>
Ivan wrote:
> Has anyone used a non altera byteblasterII scheme for loading serial
> configuration device (EPSC1 or EPCS4)? I found two reference on the
> net but I couldn't implement then yet, I don't know if they work.
> 
> reference:
> 
>   http://www.hdl.co.jp/tp2/
>   http://fishing.gptel.ru/sm/ByteBlasterII.pdf
> 
> I'd appreciate any help
> 
> Thanks
> 
> Ivan
All your www ref. descibe ByteBlasterMV and not ByteBlasterII. 
ByteBlasterII is an active POD, ByteBlasterMV is passive !

It will be very expensive to think to do your own ByteBlasterII !

Or see www.amontec.com/chameleon.shtml

Laurent Gauch
Amontec Team


Article: 61847
Subject: Re: Pass transistor logic in a FPGA
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 14 Oct 2003 07:45:01 -0400
Links: << >>  << T >>  << A >>
Nitin wrote:
> 
> Hi,
>     I am a graduate student of Auburn Univeristy doing my research in
> SoC testing. I am really an amateur in FPGAs and would like your help.
> I have a question, which I think you people can answer. For my
> research, I would like to implement a transmission gate into a FPGA.
> Can it be done? If yes could you tell me how?
> 
>   Would really appreciate your help...
> 
>    Thanks
>              Nitin

FPGAs use pass transistors in their internal construction, but the key
word is "internal".  AFAIK, they don't make a pass transistor directly
available as a user selectable element.  But depending on what features
of the pass transistor you are trying to make use of, you may be able to
use the transistors in the routing or possibly even the LUT for your
application.  It has been indicated here that the LUTs use pass
transistors to implement the output mux of the RAM.  

Can you give us some insight into what you are trying to do?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 61848
Subject: Re: FPGA/CPLD With Analog Functions?
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 14 Oct 2003 07:54:16 -0400
Links: << >>  << T >>  << A >>
"Josť F. da Rocha" wrote:
> 
> Hello.
> 
> Iím new at the FPGA/CPLDs world and Iím currently subscribed to
> receive Xilinx email communications.
> 
> I would like to know if is there some FPGA/CPLD incorporating some few
> analog functions or analog blocks like instrumentation amplifiers,
> OPerational AMPlifiers/(analog amplification), ADCs
> (Analog-to-Digital-Converter) and DACs?
> 
> Thank you very much if you are kindly enough to answer.
> (jose_rocha@yahoo.com)

There are two devices you might be interested in.  One is an MCU with
programmable digital and analog blocks made by Cypress Semi.  This is
not really an FPGA since they don't make it easy for you to design your
own digital functions.  They used to, but they seem to have gone to a
canned module approach where you have lots of standard functions to
choose from.  But I think the digital blocks are easier to work with
than the analog blocks, so you might be able to do what you need.  

The other chip is an FPAA (field programmable analog array).  This is an
analog analog (pun intended) to digital FPGAs.  I don't know a lot about
them, but a google search should tell you the maker(s) and you can read
up.  

AFAIK, there are no chips that combine programmable digital and analog
functions on one chip.  The processing technologies are different enough
that this would be a poor tradeoff and would be neither a good digital
or a good analog chip.  Eventually when FPGAs have gotten dense enough
that they are mostly overkill for many apps, they will sacrifice digital
speed and density for the added features of built in analog functions. 
But don't hold your breath.  And don't expect the analog functions to be
programmable, at least not at first.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 61849
Subject: Re: Xilinx S3 I/O robustness question
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 14 Oct 2003 07:57:28 -0400
Links: << >>  << T >>  << A >>
lecroy wrote:
> 
> Surely as hard as you Xilinx guys pushed simulation as the answer for
> this, you would know the details of the S3 models.  Are you looking
> into it?  Is the part just to new and there is no information
> available at your level?

No one has responded to my posting here.  This is not the sort of
question you can expect a good answer from by the hotline.  So unless my
local rep can give me some straight talk, I will assume that the IBIS
models are still very preliminary and not of any real value for
simulation yet.  BTW, I am having breakfast with my rep and sales person
today.  We'll see what they have to say about the IBIS models and the
partial reconfiguration issues.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search