Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
> How do I define a specific pin to be a "virtual ground" on a Xilinx > XC9572 CPLD. > I'm sure there is more than one way to do this. Here's one way: In Project Navigator's process view, right click on Implement design and select properties. On the Basic tab check "Create Programmable GND pins on unused". That's it! All the unused pins will be held to ground. You might enjoy our free Xilinx tutorial that covers 9572 and 95108 devices: http://www.al-williams.com/pictutor Regards, Al Williams AWC * Easy RS232 prototyping: http://www.al-williams.com/awce/rs1.htmArticle: 44126
Peter, thank you for the promptness (is correct this expression?) of your answer. Well, this labels me as a rookie in this field... Mauricio Peter Alfke <Peter.Alfke@xilinx.com> wrote in message news:<3D063315.4A8F60D1@xilinx.com>... > Mauricio, you answered your own question, and described it exactly right. > It has to be this way, otherwise you could not concatenate the lead device > with additional slave serial devices... > Peter Alfke > =====================Article: 44127
Al Williams wrote: > > How do I define a specific pin to be a "virtual ground" on a Xilinx > > XC9572 CPLD. > > > > I'm sure there is more than one way to do this. Here's one way: > > In Project Navigator's process view, right click on Implement design > and select properties. > > On the Basic tab check "Create Programmable GND pins on unused". > > That's it! All the unused pins will be held to ground. I am aware of this option but I don't see how you can select the pins to be held at ground individually. My goal is to have the clock input surrounded by one ground on each side. So far I was able to pin down the clock location and "prohibit" the pins on each side but that doesn't mean the prohibited pins are connected to ground internally from what I read? Thanks Patrick > > > You might enjoy our free Xilinx tutorial that covers 9572 and 95108 > devices: http://www.al-williams.com/pictutor > > Regards, > > Al Williams > AWC > * Easy RS232 prototyping: http://www.al-williams.com/awce/rs1.htmArticle: 44128
Paul, Good news about tline support. Without it, it would be useless. You even need it to model the packages themselves, as using a single RLC pi network for the package can be false and misleading (usually is) at the edge rates we run at now. Lossy lines are useful if you have to go more than about 6" (100 mm). We routinely do a QA check comparing the spice models with the IBIS models here at Xilinx. There is some small differences right before and at the over shoot and undershoot probably mostly affected by the t-line models used, and other idosyncrasies of the simulators, but in the switching region, and in terms of the overall results, they are close enough for signal integrity work. Because the silicon can be fast or slow, or anywhere inbetween (short poly, wide poly, strong nmos, strong pmos, etc etc etc), the actual results will vary much more than comparing two simulators. Some things spice is more useful for are things like ground bounce (lifting ground, inserting impedances, modeling power return paths), and examining eye patterns for psuedorandom data patterns (although some high end IBIS simulators can do this too). Also modeling a 3.3V driver into a 2.5V input (some IBIS simulators do not allow more than one Vcco). I have had folks call and demand why the 90% point is different by 3 mV between spice and IBIS. They have missed the point entirely of SI engineering, where a SWR of 2:1 is supposed to be good enough to work under all corners. Is it? Recently a customer called and asked why the IO didn't work the way it did in simulation. I simulated it, and the simulations matched their pcb pictures perfectly! They had done the simulations, and never notcied the drive strength was too weak (duty cycle was 40/60), and then wondered why the eye pattern was so bad. Running the simulation is only the first step. Then you must examine it to see what you get, and think about what the simulation is telling you. Slow corner? Duty cycle distortion? Rise and fall times? Fast corner? All of the same? What effect will this have on data signals? Eye patterns? Clock signals? Since IBIS (and spice) does not take care of ground bounce (not without extra modeling work with spice anyway), what effect will bounce have on the signal? Austin Paul wrote: > In article <3D067B77.AA28ACB0@xilinx.com>, Austin Lesea > <austin.lesea@xilinx.com> wrote: > > > Paul, > > > > Hey this is nifty. This should allow anyone to download the IBIS models > > from any vendor, convert to spcie .model statements, and then simulate it in > > spice. > > > > Sounds like you did this for 3.3V driver model. > > > > Do the free versions of spice support the simple transmission line model? > > > > Austin > > Something else. > > Maybe some of you out there can help me. I'd like to compare the Intusoft > converted Spice model against a real Spice model. The Philips web site > is the closest I've come, to finding commercial device models in both > IBIS and Spice form. Unfortunately, the Philips Spice model for LVC32 > devices uses a LEVEL=3 MOS model and the channel is 0.8u. The Spice 3F5 > level 3 code computes Leff and Weff and checks to see if they are smaller > than 1.0u, so this model won't run in Spice. This is the closest I've > come to having models of both that I can use to compare Spice with > translated IBIS. > > http://www.philipslogic.com/support/ibis/ > http://www.philipslogic.com/support/ibis/lvc32/ibs/lvch32244a.ibs > http://www.philipslogic.com/support/spice/lvc32.zip > > Does anyone know what valid changes I could make to these > models from the LVC32 Spice files ? Here are the transistor models > and a couple of instances of them, from the lvc32.zip collection. > > ************************************************ > * NOMINAL N-CHANNEL TRANSISTOR * > * UCB-3 PARAMETER SET * > ************************************************ > .MODEL MNEN NMOS > +LEVEL = 3 > +KP = 154E-6 > +VTO = 0.57 > +TOX = 15E-9 > +NSUB = 7.8E16 > +GAMMA = 0.70 > +PHI = 0.65 > +VMAX = 187E3 > +RS = 7.5 > +RD = 7.5 > +XJ = 0.26E-6 > +LD = 0.11E-6 > +DELTA = 1.89 > +THETA = 0.072 > +ETA = 0.043 > +KAPPA = 0.0 > +WD = 0.0 > > *********************************************** > * NOMINAL P-CHANNEL TRANSISTOR * > * UCB-3 PARAMETER SET * > *********************************************** > .MODEL MPEN PMOS > +LEVEL = 3 > +KP = 63.7E-6 > +VTO = -0.67 > +TOX = 15.0E-9 > +NSUB = 6.0E16 > +GAMMA = 0.84 > +PHI = 0.65 > +VMAX = 1.0E6 > +RS = 10 > +RD = 10 > +XJ = 0.30E-6 > +LD = 0.04E-6 > +DELTA = 2.88 > +THETA = 0.189 > +ETA = 0.091 > +KAPPA = 0.0 > +WD = -0.03E-6 > > Here are a couple of transistors using these models. > > MP1 3 4 50 50 MPEN W=150U L=0.8U AD=220P AS=400P PD=175U PS=175U > MN3 3 4 60 60 MNEN W= 70U L=0.8U AD= 80P AS=170P PD= 80U PS= 80U > > Thanks, > PaulArticle: 44129
www.analog.com is where I'd go as well. Since the application is FM, the (up to) 200kHz bandwidths wouldn't quite be compatible with a 455kHz filter. The 10.7MHz filters are available specifically for FM. The 90 degree transform is interesting - do you mean quadrature sampling? By sampling the signals at points 90 degrees out of phase, two independent signals can be extracted from a quadrature modulated signal without additional processing. Does the FM encode anything in quadrature? It's been too long since I've played with it. Analog devices also has nice resolution in the dual-channel devices but it sounds like quadrature is overkill. Sampling the 10.7MHz at an odd multiple of 10.7MHz will eliminate the problem of catching the "peak" of the signal. Consider sampling a 10.7MHz sine wave at 21.4MHz... there's a chance (without some form of phase lock) that the sampling will occur at the zero crossings instead of the peaks. Since "40MHz" is a popular A/D speed, perhaps sampling at 32.1 MHz will give you the data you need to avoid quadrature processing or frequency control in the analog realm. Have fun! Bevan Weiss wrote: > > Analog Devices have some pretty nice high speed ADC's. > AD6645 : 14bits @ 105MSPS > AD9430 : 12bits @ 200MSPS > AD9410 : 10bits @ 210MSPS > AD9054 : 8bits @ 200MSPS > > So it becomes a bit of a tradeoff between speed and resolution. And then > there's cost... > And power dissipation... > > You've also got to remember that any mixing(intentional or not) that you do > will create intermodulation products, some of these will most likely fall > within the bandwidth of any basic (non-crystal/ceramic-resonator) filter. > > You could always use a 455kHz IF. Btw, why did you choose the 10.7MHz IF?? > > With a 455kHz IF you could probably then just follow it up with a low > pass/bandpass filter that would create a narrow enough signal to feed into > your ADC's. Then do most of the more specific filtering in the FPGA > hardware (if you've got the room). > As for the actual FPGA implementation, you could use something like a > 90degree transform and then the CORDIC algorithm on both the phase and > quadrature signals. This will get you the magnitude, and the angle. Over > time that's also the frequency. > > "jaideep" <jaideep@sasken.com> wrote in message > news:c4312ee4.0206120057.65e089f@posting.google.com... > > Hi Newsgroup, > > > > In continuation to my earlier post with the same subject, I would > > appreciate very much, if someone can provide me with the following > > answer: what is highest frequency analog signal that I can sample with > > the currently available data converters. I am considering 2 sampling > > rates; one Nyquist and the other 4x upsampling. > > > > Thanks to Noddy for providing the information. I forgot to mention > > that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around > > another subcarrier located 70KHz from the center of 10.7 MHz. The FM > > data BW is 10 KHz around this subcarrier. Therefore I guess we need to > > have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any > > suggestion/discussion on this subject and also as how to implement > > this in FPGA. > > > > Thanks in advance. > > > > Jaideep BoseArticle: 44130
John, You need to get the I and Q signals to do a digital FM demod using the Hilbert transform. You can look for references by searching on "digital FM demodulation." Or you can read up on it in the ARRL Handbook. A number of high end ham transceivers use DSP to perform all signal processing (USB, LSB, AM, FM, CW, speech processing, variable bandwidth filters) at the IF frequency right down to the audio. Some even use DSP to go the other way, and go from USB, LSB, AM, FM, CW all the way back to IF with filters, compression, etc. The IF in this case is shifted down to where a DSP chip can handle it. The rates are not high enough to warrant using a FPGA. Austin John_H wrote: > www.analog.com is where I'd go as well. > > Since the application is FM, the (up to) 200kHz bandwidths wouldn't > quite be compatible with a 455kHz filter. The 10.7MHz filters are > available specifically for FM. > > The 90 degree transform is interesting - do you mean quadrature > sampling? By sampling the signals at points 90 degrees out of phase, > two independent signals can be extracted from a quadrature modulated > signal without additional processing. Does the FM encode anything in > quadrature? It's been too long since I've played with it. > > Analog devices also has nice resolution in the dual-channel devices but > it sounds like quadrature is overkill. > > Sampling the 10.7MHz at an odd multiple of 10.7MHz will eliminate the > problem of catching the "peak" of the signal. Consider sampling a > 10.7MHz sine wave at 21.4MHz... there's a chance (without some form of > phase lock) that the sampling will occur at the zero crossings instead > of the peaks. Since "40MHz" is a popular A/D speed, perhaps sampling at > 32.1 MHz will give you the data you need to avoid quadrature processing > or frequency control in the analog realm. > > Have fun! > > Bevan Weiss wrote: > > > > Analog Devices have some pretty nice high speed ADC's. > > AD6645 : 14bits @ 105MSPS > > AD9430 : 12bits @ 200MSPS > > AD9410 : 10bits @ 210MSPS > > AD9054 : 8bits @ 200MSPS > > > > So it becomes a bit of a tradeoff between speed and resolution. And then > > there's cost... > > And power dissipation... > > > > You've also got to remember that any mixing(intentional or not) that you do > > will create intermodulation products, some of these will most likely fall > > within the bandwidth of any basic (non-crystal/ceramic-resonator) filter. > > > > You could always use a 455kHz IF. Btw, why did you choose the 10.7MHz IF?? > > > > With a 455kHz IF you could probably then just follow it up with a low > > pass/bandpass filter that would create a narrow enough signal to feed into > > your ADC's. Then do most of the more specific filtering in the FPGA > > hardware (if you've got the room). > > As for the actual FPGA implementation, you could use something like a > > 90degree transform and then the CORDIC algorithm on both the phase and > > quadrature signals. This will get you the magnitude, and the angle. Over > > time that's also the frequency. > > > > "jaideep" <jaideep@sasken.com> wrote in message > > news:c4312ee4.0206120057.65e089f@posting.google.com... > > > Hi Newsgroup, > > > > > > In continuation to my earlier post with the same subject, I would > > > appreciate very much, if someone can provide me with the following > > > answer: what is highest frequency analog signal that I can sample with > > > the currently available data converters. I am considering 2 sampling > > > rates; one Nyquist and the other 4x upsampling. > > > > > > Thanks to Noddy for providing the information. I forgot to mention > > > that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around > > > another subcarrier located 70KHz from the center of 10.7 MHz. The FM > > > data BW is 10 KHz around this subcarrier. Therefore I guess we need to > > > have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any > > > suggestion/discussion on this subject and also as how to implement > > > this in FPGA. > > > > > > Thanks in advance. > > > > > > Jaideep BoseArticle: 44131
Piotr wrote: > > In my design internal clock is sourced from 4-to-1 multiplexer. Inputs of > the multiplexer are connected to IPADs. Is there any possibility to add > OFFSET_IN_BEFORE / OFFSET_OUT_AFTER constraint to this internal clock line. > Thanks in advance, > Piotr Foryt Muxing clocks very bad magic, many demons live there. Even if you are not muxing the clock in real time and shutdown the chip each time you change the clock, it plays havoc with timing analysis. I would be much better to assign each of your clocks to separate clock pins and to use a different download to connect the required clock. Of course if your clock is not used externally to the chip so that you don't have to worry about clock delays between the FPGA and other chips, then using a mux is not a problem. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44132
Noddy wrote: > > Hi, > > I know that one should place 0.1uF and 0.01uF caps on all power supply pins > on the FPGA... does this include both Vcco and Vccint, or can one get away > with just Vccint and then put only 0.1uF on Vcco. I am seriously running out > of room on my PCB, and increasing the PCB size is not an option! > > adrian My experience is that there is a lot of "voodoo" floating around when it comes to supply bypassing. I have NEVER seen adequate justification for using both 0.1 uF and 0.01 uF caps on the same supply rail. I know the argument that the smaller caps have a higher self resonant frequency (SRF), but that does not hold water. The SRF is higher, but the SRF is not what we care about. The important spec is the impedance at the frequency of interest. If you go to the cap manufacturer's web site and download the docs, you will see that the impedance curves for different value caps are nearly identical at the frequencies of interest. The larger caps have lower impedance below SRF and of course the SRF point is the minimum. So at the point of SRF for the smaller cap, the impedance is lower. But above SRF, which is where most of the noise on a board lies, the impedance is nearly the same. Above SRF the impedance is much more impacted by the cap size and shape. So using two sizes of caps is not warranted. Try to use one cap on each power pin with as short a lead as possible. The longer the lead, the worse the added inductance and increased impedance. But if the power pins are very close and more caps just can't be squeezed in, I use one cap for two or even three pins. The main thing is to keep the traces short to keep down the parasitic inductance. Oh, you don't need tantalum caps for each chip either. They only provide effective bypassing at freqs below 1 MHz or so. At these freqs the location on the board is not an issue since the ground and power planes have a very low impedance. So there is little reason to use 10 tantalums of 10 uF instead of one 100 uF part. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44133
Hi, What is the smart way to constrain something like an interface to external async. ram ? (reading only) I guess I could setup a timespec from FF's to address pads and from data pads to FF's have the two time specs plus the ram access time be equal to my desired clk period. But, as fas as I can tell that means I'd have to have a pretty good guess on how the delays are distributed before and after the ram. Is there way that i can constrain it all in one go? , because I really don't care how the FF's to address pads and data pads to FF's delays are, as long as I can get all the way within my period, less the ram access time. thanks, -Lasse -- // Lasse Langwadt Christensen // Aalborg, DanmarkArticle: 44134
"Roger King" <roger@king.com> schrieb im Newsbeitrag news:lRvN8.287033$t8_.195817@news01.bloor.is.net.cable.rogers.com... > I don't have the info, but what about the XC2S50 chip/family? XC2S50 is a Spartan-II, 50k gates (whatever gates means . .;-) It has also 6 BlockRams, 4kbit each. > and is that a good number? XC2S50 is a nice chip to start with. But as others already said, go for a 200K or 300K gates device, they cost not much more (together with a demoboad). Also remember, the bigger the device, the cheaper the logic funktions ($/LUT), with some minor exceptions. -- MfG FalkArticle: 44135
Is there a uClinux or other MMU-less Linux/xBSD port available for MicroBlaze? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 44136
Patrick Robin wrote: > Al Williams wrote: > > > > How do I define a specific pin to be a "virtual ground" on a Xilinx > > > XC9572 CPLD. > > > > > > > I'm sure there is more than one way to do this. Here's one way: > > > > In Project Navigator's process view, right click on Implement design > > and select properties. > > > > On the Basic tab check "Create Programmable GND pins on unused". > > > > That's it! All the unused pins will be held to ground. > > I am aware of this option but I don't see how you can select the pins to > be held at ground individually. > > My goal is to have the clock input surrounded by one ground on each side. > So far I was able to pin down > the clock location and "prohibit" the pins on each side but that doesn't > mean the prohibited pins are connected to > ground internally from what I read? > > Thanks > > Patrick > > This question - putting some extra GNDs either side of a clock pin - has come up on this NG in the FPGA context. Someone from Xilinx (Austin Lesea IIRC) suggested taking making the IOs either side of the clock into outputs, driving them to 0 and connecting the correspondings pins to GND on the PCB. Dunno if this will work the same trick for CPLDs.Article: 44137
There are multiple ways of doing it, 1) At synthesis, you tell your tool to make your ports into I/O cells. 2) There is some P&R directive that says in effect "Ports are pads" "Ken Mac" <aeu96186@yahoo.co.uk> wrote in message news:<ae6uu1$bv8$1@dennis.cc.strath.ac.uk>... > Jay, > > Thanks for your response. > > I would like to try your suggestion about using primary I/O's. > > Can you just confirm exactly how I connect my ports to primary I/O's - do I > do it in my VHDL, or in my UCF? > > Thanks, > > Ken > > "Jay" <kayrock66@yahoo.com> wrote in message > news:d049f91b.0206110904.856dfbc@posting.google.com... > > Good point about the post -MAP time, I think thats best case timing, > > and also, to answer your question "Does my choice of LOCs effect > > circuit speed?" the answer is yes, the placer does its best but if > > you tie its hands then it can only do its best. It gave a really good > > hint about higher placement effort because it could see the long > > routing delay. Instead of using LOCs to stop your circuit from being > > optimized away, connect your ports to primary I/O's- unassigned, and > > see what the tool does for you. > > > > and to answer the other gentlemans question about what to do with high > > fanout nets, most modern synthesizers will reduce your fan (when > > instructed) out by trying first to duplicate the driving logic, and > > secondly by buffering. > > > > Regards > > > > Davis Moore <davism@NOSPAMxilinx.com> wrote in message > news:<3D050729.E51EDBBC@NOSPAMxilinx.com>... > > > Ken, > > > > > > The post-MAP timing report will always report a clock frequency greater > > > than the post-PAR timing report. This is because the post-MAP NCD > > > does not contain any routing delay information as the design has not yet > > > been placed or routed. > > > > > > Ken Mac wrote: > > > > > > [...SNIP...] > > > > > > Anyway, after mapping, the maximum clock frequency is reported to be > > > 138.947MHz. > > > > > > But, after place and route, the max clock freq. is reported to be > 91.166MHz. > > > > > > Where could I be losing so much MHz? Can my choice of LOCs in the UCF > > > affect the max clock freq.? > > > > > > [...SNIP...]Article: 44138
Hi Thijs, I have looked at doc1417.pdf. If I understand it the right way, then you are not able to program the FPGA directly with this board. Instead you have to program an AT17Cxx serial EEPROM (called "configurator") using this board. You can then use the AT17Cxx to program the XC3030A in master serial mode. AT17Cxx works fine with XC3000, I use it in this way. But where do you get the AT17Cxx? For which price? I would recommend to use a Xilinx parallel programming cable III. You could find the schematics at www.xilinx.com. Make a .mcs file with your xilinx student version. Impact (part of the free webpack software) should be able to read this file and to program the 3030A in slave serial mode (but I have not tested it). For cheap single FPGAs try www.schukat.de Good luck! Werner Thijs wrote: > > hi all, > > I've could buy a cheap (used) xilinx XC3030A fpga, > now i'd like to make my own pcb for it, > > Atmel has a pin-layout for a simple parallel programming cable, > and claims it works for xilinx devices > http://www.atmel.com/atmel/acrobat/doc1417.pdf > > does anyone have any experience with this? > > if not, does anyone know another programming software which > works with an XC3030A and a home made programming cable ? > > Greetz, > > ThijsArticle: 44139
I was hoping you were right and it got fixed in 7.1. It didn't. I just got the new Synplify version running and the same FDRE primitive I instantiated a week ago - the one that got optimized on me prompting my creation of an FDREdammit primitive with syn_hier="hard" - still gets optimized for me if I use the FDRE. I'm considering adding a syn_hier="hard" to Synplify's Xilinx primitive files. Ray Andraka wrote: > You can always instantiate the FDRE or FDSE. Then again, you may still need > syn_keeps on any logic you put in front of them. Synplicity has recently (v7.03) > ripped up instantiated components and 'optimized' them on me. Apparently there is > an optimize phase after synthesis to primitives and at that point it can't tell > the difference between an inferred and an instantiated primitive. I think this > one got fixed in 7.1, but it also isn't the first time I've seen Synplicity > ripping up stuff that I instantiated. I think it needs an internal > syn_the_user_instantiated_this_primitive_so_I_better_leave_it_alone flag on > instantiated primitives (it should be easy to identify anything that is > black-boxed when parsing the code in the first pass, especially if there is a > syn_black_box atribute on the component. > > John_H wrote: > > > I like the directive thought... > > > > /* synthesis syn_for_all_that_is_holy_please_oh_please_use_an_FDSE */; > > > > Rick Filipkiewicz wrote: > > > > > What we need is a directive like ``syn_carry_chain'' or, to make quite sure, > > > > > > ``syn_this_is_a_carry_chain_so_just_do_it_and_dont_ask_questions''. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 44140
For minimum "impedance at the frequency of interest," the SRF *is* what we care about (along with the equivalent series resistance). If you use a cap with a higher SRF, the impedance will be higher than you could otherwise achieve. If you use a cap with a lower SRF you are - once again - losing out on the impedance because of the inductive effect. The different packages tend to allow either deeper curves (lower impedance across the frequency range around the SRF) and/or wider "bottoms" where the impedance is comfortably low. We could just add capacitors until there's no more room on our boards and the paralleled impedances at the frequency of interest might be near where we want them. A judicious choice of caps "near" the chip (1/10 wavelength for the frequency of interest, perhaps) - not for each power/ground pin pair - might be a best fit. Might. Plane inductances to the caps and to the devices do play a part. It really is voodoo. rickman wrote: > I know the > argument that the smaller caps have a higher self resonant frequency > (SRF), but that does not hold water. The SRF is higher, but the SRF is > not what we care about. The important spec is the impedance at the > frequency of interest. If you go to the cap manufacturer's web site and > download the docs, you will see that the impedance curves for different > value caps are nearly identical at the frequencies of interest.Article: 44141
In cases like this I've just driven an output cell to logic zero in the schematic or HDL, the tools have no problem with this. That big N-channel FET turns on and stays on providing a low impedance path to ground. For shielding you could theoretically use either supply rail, but the N-channel FETS are almost always lower resistance so have some benefit over the P-channel. Regards Patrick Robin <circaeng@hotmail.com> wrote in message news:<3D069775.8EE7E0E3@hotmail.com>... > Hi > > How do I define a specific pin to be a "virtual ground" on a Xilinx > XC9572 CPLD. > > I have a couple of unused I/Os that I would like to locate on each side > on my input clock signal and use as extra grounds to the CPLD. > > I am using Xilinx WebPack and Verilog source. > > Thanks > > PatrickArticle: 44142
As noted, you need pulldown resistors for PECL outputs. You can terminate a differential PECL pair by either combining the DC bias and line termination functions - a pair of 50 ohm pulldowns to VCC-2V (or the Thevenin equivalent) at the load, or provide the DC bias current through pulldown resistors to ground close to the driver and line termination by 100 ohms across the pair at the load - so-called "Standard pair" termination. It was this second method that the app note writer had in mind, perhaps because it would work with both the Xilinx drive scheme and (LV)PECL devices. The messy part is choosing the optimum PECL pulldown resistor to balance AC and DC requirements - it's somewhere between 142 and 200 ohms for 3.3V supplies depending on the tradeoffs chosen. There's a fairly recent (2001) app note on termination of modern ECL devices at http://www.onsemi.com (formerly Motorola) - look for AND8020/D. Also Maxim has a good one: "Introduction to LVDS, PECL, and CML", HFAN-1.0. Huy Nguyen wrote: > > Hello, > > I am trying to interface a Virtex-II chip to a standard LVPECL device with open-emitter output driver. This type of circuit requires a sink current for emitters, which is not provided by the differential termination scheme in Xilinx AppNote133. > > Is this differential termination scheme applicable for Xilinx's pseudo LVPECL drivers only, or also for standard LVPECL as well ? > > Thank you. > > Huy -- Tom Burgess Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 44143
What do you do with the output of the Hilbert transform? The way I've seen it done is to find the derivative (just the delta between samples) of arctan(I/Q) and make the demodulated output proportional to that. Calculating arctan requires some sort of Taylor polynomial calculator though unless you have a big LUT. -Kevin "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3D075DE6.F274C3B1@xilinx.com... > John, > > You need to get the I and Q signals to do a digital FM demod using the Hilbert > transform. > > You can look for references by searching on "digital FM demodulation." Or you > can read up on it in the ARRL Handbook. > > A number of high end ham transceivers use DSP to perform all signal processing > (USB, LSB, AM, FM, CW, speech processing, variable bandwidth filters) at the IF > frequency right down to the audio. Some even use DSP to go the other way, and go > from USB, LSB, AM, FM, CW all the way back to IF with filters, compression, etc. > > The IF in this case is shifted down to where a DSP chip can handle it. The rates > are not high enough to warrant using a FPGA. > > Austin > > John_H wrote: > > > www.analog.com is where I'd go as well. > > > > Since the application is FM, the (up to) 200kHz bandwidths wouldn't > > quite be compatible with a 455kHz filter. The 10.7MHz filters are > > available specifically for FM. > > > > The 90 degree transform is interesting - do you mean quadrature > > sampling? By sampling the signals at points 90 degrees out of phase, > > two independent signals can be extracted from a quadrature modulated > > signal without additional processing. Does the FM encode anything in > > quadrature? It's been too long since I've played with it. > > > > Analog devices also has nice resolution in the dual-channel devices but > > it sounds like quadrature is overkill. > > > > Sampling the 10.7MHz at an odd multiple of 10.7MHz will eliminate the > > problem of catching the "peak" of the signal. Consider sampling a > > 10.7MHz sine wave at 21.4MHz... there's a chance (without some form of > > phase lock) that the sampling will occur at the zero crossings instead > > of the peaks. Since "40MHz" is a popular A/D speed, perhaps sampling at > > 32.1 MHz will give you the data you need to avoid quadrature processing > > or frequency control in the analog realm. > > > > Have fun! > > > > Bevan Weiss wrote: > > > > > > Analog Devices have some pretty nice high speed ADC's. > > > AD6645 : 14bits @ 105MSPS > > > AD9430 : 12bits @ 200MSPS > > > AD9410 : 10bits @ 210MSPS > > > AD9054 : 8bits @ 200MSPS > > > > > > So it becomes a bit of a tradeoff between speed and resolution. And then > > > there's cost... > > > And power dissipation... > > > > > > You've also got to remember that any mixing(intentional or not) that you do > > > will create intermodulation products, some of these will most likely fall > > > within the bandwidth of any basic (non-crystal/ceramic-resonator) filter. > > > > > > You could always use a 455kHz IF. Btw, why did you choose the 10.7MHz IF?? > > > > > > With a 455kHz IF you could probably then just follow it up with a low > > > pass/bandpass filter that would create a narrow enough signal to feed into > > > your ADC's. Then do most of the more specific filtering in the FPGA > > > hardware (if you've got the room). > > > As for the actual FPGA implementation, you could use something like a > > > 90degree transform and then the CORDIC algorithm on both the phase and > > > quadrature signals. This will get you the magnitude, and the angle. Over > > > time that's also the frequency. > > > > > > "jaideep" <jaideep@sasken.com> wrote in message > > > news:c4312ee4.0206120057.65e089f@posting.google.com... > > > > Hi Newsgroup, > > > > > > > > In continuation to my earlier post with the same subject, I would > > > > appreciate very much, if someone can provide me with the following > > > > answer: what is highest frequency analog signal that I can sample with > > > > the currently available data converters. I am considering 2 sampling > > > > rates; one Nyquist and the other 4x upsampling. > > > > > > > > Thanks to Noddy for providing the information. I forgot to mention > > > > that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around > > > > another subcarrier located 70KHz from the center of 10.7 MHz. The FM > > > > data BW is 10 KHz around this subcarrier. Therefore I guess we need to > > > > have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any > > > > suggestion/discussion on this subject and also as how to implement > > > > this in FPGA. > > > > > > > > Thanks in advance. > > > > > > > > Jaideep Bose >Article: 44144
O.k. I think I've found it. I removed the RLOCs on the MUXCYs just leaving them on the LUTs themselves and MAP survived so I could see the results. Basically the RPM is implementing a function: ((addr[8:0] & mask[8:0]) != 0) 2 bits at a time via the carry chain. In the situation I have there are some builds with only small, 256MB, memory space where the top 3 bits of the mask function are ifdef'ed to 0 so. Since its all instantiated Synplify doesn't (this time) try and do any optimisation and leaves the full 5 element chain in place for both builds. MAP is much cleverer and realises that in the small build the top 2 LUT outputs are always 1 => carry chain pass through => ``Hey I can optimise/trim those 2 LUTs'' and move the output down 2 steps. For some reason this causes something to go horribly wrong in the pack phase of MAP. I'd guess that with RLOCs on the top 2 MUXCYs they were not being trimmed along with their associated LUTs - or some such.Article: 44145
I've only recently taken up the whole RF/IF mixing etc (Telecommunications) Could you please explain why the 455kHz IF is too low for FM. I would have thought that a 200kHz mod on the incoming signal would of produced a deviation of 255kHz->655kHz. This falls easily within the capabilities of a high speed ADC. Then once inside the digital realm the Hilbert transform (filter) can be applied (forgot the name of the damn thing last time...) Once in quadtrature and digital, you can use the CORDIC algorithm to obtain the magnitude of the input signal (the change of time of which gives AM). And the phase of the input signal (inv_tan(q/i)), change in phase over time is frequency. and change in frequency over time is FM. "John_H" <johnhandwork@mail.com> wrote in message news:3D075DA5.D9DE7D87@mail.com... > www.analog.com is where I'd go as well. > > Since the application is FM, the (up to) 200kHz bandwidths wouldn't > quite be compatible with a 455kHz filter. The 10.7MHz filters are > available specifically for FM. > > The 90 degree transform is interesting - do you mean quadrature > sampling? By sampling the signals at points 90 degrees out of phase, > two independent signals can be extracted from a quadrature modulated > signal without additional processing. Does the FM encode anything in > quadrature? It's been too long since I've played with it. > > Analog devices also has nice resolution in the dual-channel devices but > it sounds like quadrature is overkill. > > Sampling the 10.7MHz at an odd multiple of 10.7MHz will eliminate the > problem of catching the "peak" of the signal. Consider sampling a > 10.7MHz sine wave at 21.4MHz... there's a chance (without some form of > phase lock) that the sampling will occur at the zero crossings instead > of the peaks. Since "40MHz" is a popular A/D speed, perhaps sampling at > 32.1 MHz will give you the data you need to avoid quadrature processing > or frequency control in the analog realm. > > Have fun! > > > > Bevan Weiss wrote: > > > > Analog Devices have some pretty nice high speed ADC's. > > AD6645 : 14bits @ 105MSPS > > AD9430 : 12bits @ 200MSPS > > AD9410 : 10bits @ 210MSPS > > AD9054 : 8bits @ 200MSPS > > > > So it becomes a bit of a tradeoff between speed and resolution. And then > > there's cost... > > And power dissipation... > > > > You've also got to remember that any mixing(intentional or not) that you do > > will create intermodulation products, some of these will most likely fall > > within the bandwidth of any basic (non-crystal/ceramic-resonator) filter. > > > > You could always use a 455kHz IF. Btw, why did you choose the 10.7MHz IF?? > > > > With a 455kHz IF you could probably then just follow it up with a low > > pass/bandpass filter that would create a narrow enough signal to feed into > > your ADC's. Then do most of the more specific filtering in the FPGA > > hardware (if you've got the room). > > As for the actual FPGA implementation, you could use something like a > > 90degree transform and then the CORDIC algorithm on both the phase and > > quadrature signals. This will get you the magnitude, and the angle. Over > > time that's also the frequency. > > > > "jaideep" <jaideep@sasken.com> wrote in message > > news:c4312ee4.0206120057.65e089f@posting.google.com... > > > Hi Newsgroup, > > > > > > In continuation to my earlier post with the same subject, I would > > > appreciate very much, if someone can provide me with the following > > > answer: what is highest frequency analog signal that I can sample with > > > the currently available data converters. I am considering 2 sampling > > > rates; one Nyquist and the other 4x upsampling. > > > > > > Thanks to Noddy for providing the information. I forgot to mention > > > that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around > > > another subcarrier located 70KHz from the center of 10.7 MHz. The FM > > > data BW is 10 KHz around this subcarrier. Therefore I guess we need to > > > have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any > > > suggestion/discussion on this subject and also as how to implement > > > this in FPGA. > > > > > > Thanks in advance. > > > > > > Jaideep BoseArticle: 44146
I think you'd be hard-pressed to fit even a couple of floating-point multipliers in 20k gates, so doing actual computing is out. You may be able to build some simple logic circuits. Tyler Reed "Roger King" <roger@king.com> wrote in message news:iqvN8.251995$ah_.246227@news01.bloor.is.net.cable.rogers.com... > Ok, let me give you a better statistic, 384 CLBs? 384 sounds like a really > low number, it looks like I can only develop extremely simple projects. > > > > "Roger King" <roger@king.com> wrote in message > news:CUmN8.248826$ah_.140060@news01.bloor.is.net.cable.rogers.com... > > Is 20,000 gates enough for creating a nice project? What are some projects > > one can create by using 20,000 gates? I am trying to decide if 20,000 > gates > > fpga board would be sufficient for a hobbyist that wants to use it for > about > > 2 years. > > > > I have another question. How many megs of RAM will I be able to develop > > using 20,000 gates fpga? I mean if I want to use the fpga as a ram. > > > > > > > > > >Article: 44147
John_H wrote: > Bleah. I go to 13 bits and it's still implementing a tree. At least my big > comparator I mentioned is still implemented as a carry chain. > > (BTW - I forgot to specify the "== 0" for each of the elements in the example > below) > > I've had troubles with Synplify messing up my carry chains throughout my coding > experience. One version to the next things seem to change for the worse. > > I hope all my improvements don't get unimproved over time! > > John_H wrote: > I just found a case where Synplify has spontaneously used "carry chain" logic for a comparator. Thing is its a 24 bit comparison. Playing around a bit it seems that the trip point, at least for a simple comparator, is 16 bits, for 16 bits and above it uses the carry chain. I think what's happening is that Synplify has a very naive/unrealistic idea of what the routing delays in a well placed logic tree *should* be whereas we know that PAR is very poor at placing related LUTs close to each other so routing delays are always much greater than Syn assumes when doing its mapping. I got the impression at the v6.x stage that Synplify was beginning to try & contruct its own RPMs but v7.x has backed away from this.Article: 44148
From pure numbers, 455kHz is fine. Practical applications require 1) good bandpass filters, 2) good places to pre-filter the image before mixing down to IF. If you convert radio station 105.9 (MHz) down to 10.7MHz, you either have an image at 84.5MHz or at 127.3MHz (+2x10.7MHz or -2x10.7MHz). It's tough to filter +/-910kHz from a 100MHz signal. Once the IF is produced from the pre-filter/mix arrangement, a further bandpass gets rid of high power adjacent channels so an AGC can give you nice dynamic rance on the signal you sample with the ADC. Radio is neat. Bevan Weiss wrote: > I've only recently taken up the whole RF/IF mixing etc (Telecommunications) > > Could you please explain why the 455kHz IF is too low for FM. I would have > thought that a 200kHz mod on the incoming signal would of produced a > deviation of 255kHz->655kHz. This falls easily within the capabilities of a > high speed ADC. Then once inside the digital realm the Hilbert transform > (filter) can be applied (forgot the name of the damn thing last time...) > > Once in quadtrature and digital, you can use the CORDIC algorithm to obtain > the magnitude of the input signal (the change of time of which gives AM). > And the phase of the input signal (inv_tan(q/i)), change in phase over time > is frequency. and change in frequency over time is FM. > > "John_H" <johnhandwork@mail.com> wrote in message > news:3D075DA5.D9DE7D87@mail.com... > > www.analog.com is where I'd go as well. > > > > Since the application is FM, the (up to) 200kHz bandwidths wouldn't > > quite be compatible with a 455kHz filter. The 10.7MHz filters are > > available specifically for FM. > > > > The 90 degree transform is interesting - do you mean quadrature > > sampling? By sampling the signals at points 90 degrees out of phase, > > two independent signals can be extracted from a quadrature modulated > > signal without additional processing. Does the FM encode anything in > > quadrature? It's been too long since I've played with it. > > > > Analog devices also has nice resolution in the dual-channel devices but > > it sounds like quadrature is overkill. > > > > Sampling the 10.7MHz at an odd multiple of 10.7MHz will eliminate the > > problem of catching the "peak" of the signal. Consider sampling a > > 10.7MHz sine wave at 21.4MHz... there's a chance (without some form of > > phase lock) that the sampling will occur at the zero crossings instead > > of the peaks. Since "40MHz" is a popular A/D speed, perhaps sampling at > > 32.1 MHz will give you the data you need to avoid quadrature processing > > or frequency control in the analog realm. > > > > Have fun! > > > > > > > > Bevan Weiss wrote: > > > > > > Analog Devices have some pretty nice high speed ADC's. > > > AD6645 : 14bits @ 105MSPS > > > AD9430 : 12bits @ 200MSPS > > > AD9410 : 10bits @ 210MSPS > > > AD9054 : 8bits @ 200MSPS > > > > > > So it becomes a bit of a tradeoff between speed and resolution. And > then > > > there's cost... > > > And power dissipation... > > > > > > You've also got to remember that any mixing(intentional or not) that you > do > > > will create intermodulation products, some of these will most likely > fall > > > within the bandwidth of any basic (non-crystal/ceramic-resonator) > filter. > > > > > > You could always use a 455kHz IF. Btw, why did you choose the 10.7MHz > IF?? > > > > > > With a 455kHz IF you could probably then just follow it up with a low > > > pass/bandpass filter that would create a narrow enough signal to feed > into > > > your ADC's. Then do most of the more specific filtering in the FPGA > > > hardware (if you've got the room). > > > As for the actual FPGA implementation, you could use something like a > > > 90degree transform and then the CORDIC algorithm on both the phase and > > > quadrature signals. This will get you the magnitude, and the angle. > Over > > > time that's also the frequency. > > > > > > "jaideep" <jaideep@sasken.com> wrote in message > > > news:c4312ee4.0206120057.65e089f@posting.google.com... > > > > Hi Newsgroup, > > > > > > > > In continuation to my earlier post with the same subject, I would > > > > appreciate very much, if someone can provide me with the following > > > > answer: what is highest frequency analog signal that I can sample with > > > > the currently available data converters. I am considering 2 sampling > > > > rates; one Nyquist and the other 4x upsampling. > > > > > > > > Thanks to Noddy for providing the information. I forgot to mention > > > > that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around > > > > another subcarrier located 70KHz from the center of 10.7 MHz. The FM > > > > data BW is 10 KHz around this subcarrier. Therefore I guess we need to > > > > have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any > > > > suggestion/discussion on this subject and also as how to implement > > > > this in FPGA. > > > > > > > > Thanks in advance. > > > > > > > > Jaideep BoseArticle: 44149
I'm having MUXCY trimming problems *right now*. I tried to take my 29 MUXCY instantiations and convert them into an array of instances. Yuck! The physical implementation of my chain became toast once Synplify started "optimizing" the pass elements out of the chain (I have several in the middle). The inclusion of oh-so-many LUT1_2 elements is getting at my nerves as well: I tried a MUXCY primitive redefinition (I called it MUXCYdammit) with syn_hier="hard" like I did earlier with an FDRE but if you push down into the instance in HDL_Analyst, there's a pass-LUT on the sel input. Once again Synplify knows better. Oy. The apps engineers are looking at my chain, but I imagine it's back to the 29 individual instances. I hope those aren't broken! - John_H Rick Filipkiewicz wrote: > O.k. I think I've found it. I removed the RLOCs on the MUXCYs just leaving them > on the LUTs themselves and MAP survived so I could see the results. Basically > the RPM is implementing a function: > > ((addr[8:0] & mask[8:0]) != 0) > > 2 bits at a time via the carry chain. In the situation I have there are some > builds with only small, 256MB, memory space where the top 3 bits of the mask > function are ifdef'ed to 0 so. Since its all instantiated Synplify doesn't (this > time) try and do any optimisation and leaves the full 5 element chain in place > for both builds. > > MAP is much cleverer and realises that in the small build the top 2 LUT outputs > are always 1 => carry chain pass through => ``Hey I can optimise/trim those 2 > LUTs'' and move the output down 2 steps. > > For some reason this causes something to go horribly wrong in the pack phase of > MAP. I'd guess that with RLOCs on the top 2 MUXCYs they were not being trimmed > along with their associated LUTs - or some such.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z