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In article <1111722059.509960.148040@z14g2000cwz.googlegroups.com>, Marc Randolph <mrand@my-deja.com> wrote: > Or as Bob posted, you could go ahead and chew up 2x the number of pins > and bias the _n input of a differential receiver to the mid-point. This is probably best as I was prepared to do that anyway in the parallel univered where On Semi made the outputs of the 445 differential. ;-) It's an XC2V4000 in a BF957 package. It's the 64 signals in and then another 64 out on the far side. That's 90% of this chip's I/O. The rest is just control lines and a serial data link from another FPGA. Thanks for the tips, guys.Article: 81501
Hi all, Can anyone tell me what is the threshold point(memory size) to opt for Onchip SRAM instead of FlipFlops , considering the Power&Area. In a module I have ~5Kbit of memory implemented as verilog registers. I would like to know the Power/Area savings if I switch to SRAM instead of Flipflops. I use .13u process. Any links/documents in this regard are highly welcome. Thanks Deepu JohnArticle: 81502
John, your question seems to relate to ASIC design. This newsgroup deals with FPGAs where you select and then use a given architecture. That means the trade-offs are different. Modern FPGAs have SRAM blocks of various sizes, from 512 bits to 18 k bits and even larger. Xilinx offers the RAM option in the Look-up Tables (LUTs), which can even be used as shift registers. The designer's decision is to use available resources, not to design latches or flip-flops. This can lead to peculiar design optimizations when a certain resource is abundant and not all used, e.g. BlockRAMs. 5k bit fits very comfortably in one 18 kbit dual-ported BlockRAM, but would take an inordinate amount of LUTs, even at 16 bits per LUT. You decide. Peter Alfke, XilinxArticle: 81503
Jochen Frensch wrote: > you'll have to wait for 100 ns (if you didn't set it to another > values) for the GSR-Net (global set-/reset-net) to become inactive... Nailed it on the first try. 200 ns of padding out front solved the problem. Thanks for your help.Article: 81504
Quiet Desperation wrote: > In article <1111722059.509960.148040@z14g2000cwz.googlegroups.com>, > Marc Randolph <mrand@my-deja.com> wrote: > > > Or as Bob posted, you could go ahead and chew up 2x the number of pins > > and bias the _n input of a differential receiver to the mid-point. > > This is probably best as I was prepared to do that anyway in the > parallel univered where On Semi made the outputs of the 445 > differential. ;-) It's an XC2V4000 in a BF957 package. It's the 64 > signals in and then another 64 out on the far side. That's 90% of this > chip's I/O. The rest is just control lines and a serial data link from > another FPGA. Reminds me of a new 4VFX60 design that we've started... 40 general purpose I/O pins (all CPU and clock related) + some RocketIO channels. The ideal package to allow movement to a larger device if neccessary, would be the FF1152 pkg. Talk about having a few unused pins! Have fun, MarcArticle: 81505
Hi, I have downloaded Xilinx ISE 7.1 webpack and Modelsim 6 free edition. I need Xilinx for my digital circuits course. During the course laboratory we were using Xilinx foundation 2.1. After designing simple circuit I have attached some probes to inputs and output and then in simulator bound some keys in order to change input signals' from 0 to 1 and test the output. The problem is I don't know how to do the same in 7.1 + ModelSim. First of all there is no such thing as "simulation toolbox" as in 2.1. I was able to run Modelsim and apply clocks to input signal but it is not what I want. Is it possible to change input signals from 0 to 1 etc on the fly? With keyboard for example? Cheers, Mike, leet.geezerDONT_SPAM_ME_PLS@gmail.comArticle: 81506
Joseph, Xilkernel is not an SMP (Shared multi-processor) kernel. So, in that sense - No, it cannot run on two PPCs. If you mean, can you run it on two different PowerPCs independently, then there is no reason why it would not work. Both the kernels would be completely independent and ignorant of the other. There are also no constructs to managed shared memory between the two processors in Xilkernel. thanks, Joseph wrote: >Is xilkernel configurable to use 2 PPCs in a Virtex II? It seems that >all the Xilinx literature I have found has xilkernel running only one >PPC. I know the xilkernel source is available, but would like to stay >away from it if possible. Anyone gotten a dual-core running with >xilkernel? Thanks. > > >Article: 81507
> Marc Randolph <mrand@my-deja.com> wrote: > > This is probably best as I was prepared to do that anyway in the > parallel univered where On Semi made the outputs of the 445 > differential. I haven't used any of them recently, but I think there are several 1-10 Gbps shift register/demux parts with diff. outputs available, from the other usual suspects ( Micrel/Vitesse/Maxim/etc. ) http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1432/ln/ http://www.rsc.rockwell.com/highspeed/files/PB_0030XA0-1103.pdf BrianArticle: 81508
Ljubisa Bajic wrote: > Hi, > > I just finished viewing the fpga power consumption net seminar that > Vaughn presented today. I found it informative and, to me, it apeared > to be objective. > > According to Vaughn's experiments and measurements, Stratix 2 exhibits > lower dynamic power dissipation in the core and similar power > dissipation in the IO; beyond that his experimental results contend > that the highly touted static/leakage power advantage that V4 is > supposed to have is very minor; some might even say negligable. > > I am very curious to read Austin and Peter's opinions of this > presentation. > > Ljubisa Bajic > ATI Technologies > ---------- My opinions do not represent those of my employer. These guys are all biased. When you look at details, they show their side of the story. Power ? Big deal ! There are other more pressing issues ! High end FPGAs hardly go in portable devices ! ;-)Article: 81509
Koan Corporation has released the first version of the Reconfigurable Computing Management System, RCMS. It integrates with Linux and Windows file systems, as well as relational databases and has an interface to Nallatech's Dime-II hardware platorm. RCMS also sports datatype management, easy environment porting & management and built-in logging/benchmarking. Essentially, RCMS is middleware for FPGA-based computing. There's a Cray XD1 interface in the works, along with cvs integration and an embedded scheduler. We're considering a free version with a Spartan-3 Starter Kit interface. Info can be found at www.koancorporation.com Thanks, Tyler tyler.reed@koanSPAMISBADcorporation.comArticle: 81510
"Antti Lukats" <antti@openchip.org> wrote in message
news:d1r2nh$al1$04$1@news.t-online.com...
> Hi
>
> below is possible the most dense divide by 2^n ever implemented on any
FPGA:
> divide by 2^37 takes only 3 Virtex Slices! (4 slices on spartan-3)
>
> Antti
<snip of the original code>
Antti -
I'm truly amazed by the approach. I think I did things right in making a
Verilog 32-bit, bit-serial NCO below. (Formats nicely with fixed space
fonts). Only 1 level of logic makes for sweet timing. Thanks for bringing
this approach to light.
- John_H
// This is a bit-serial NCO with an initial
// divide-by-32 implementing a 32-bit NCO word.
//
// Original credit is given to Antti Lukats
// from a comp.arch.fpga posting 22 Mar 05.
//
// This version produced by John Handwork
// with Synplify V8.0 for a Xilinx target.
// - Some reg_input_delay route values (1.4ns)
// were applied to Add, Cry in Synplify
// to keep the logic to 1 level.
// - Note that the intializations don't synthesize.
// - Xilinx ISE v7.1 pushes 500MHz in the slow (-4)
// XC3S50, limited by routing to the I/O cell.
// - 4 Slices and an IOB is all it takes.
//
`define SRL /* synthesis syn_srlstyle = "select_srl" */
//
module TinyNCO ( input clk
, output reg Fout /* synthesis syn_useioff = 1 */
);
parameter STEP = 32'd1000000;
reg [31:0] End `SRL = 32'h0000_0001;
reg [31:0] Inc `SRL = STEP;
reg [30:0] Acc `SRL = 32'h0000_0000;
reg Cry = 1'b0;
reg Add = 1'b0;
always @(posedge clk)
begin
End <= {End[0], End[31:1]};
Inc <= {Inc[0], Inc[31:1]};
Acc <= {Add , Acc[30:1]};
{Cry,Add} <= Inc[0] + Acc[0] + (~End[0] & Cry);
if( End[0] )
Fout <= Add;
end
endmodule
Article: 81511I'll take a look at it. Any idea of what market penetration PADS has w/respect to others? How strong is their user base? -Martin "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:42425136$1@clear.net.nz... > Martin wrote: >> We've been using Altium's P-CAD for a few years (started as TangoEDA). >> Currently running 2002 and very unlikely to upgrade as, in my opinion, it >> is not a very good product and the company just loves to collect their >> $1,500 a year by releasing bogus "service packs". Still lots of very >> fundamental issues that remain without attention. >> >> Anyhow, the question is, what do we move up to? Not looking for the >> $100K+ packages. What are people using that performs well for designing >> (schematic) and laying out high-speed, high-complexity PCB's? I've heard >> that PADS may have the largest installed base out there. I remember >> getting a demo of Mentor's Expedition at a tradeshow. It seemed like a >> pretty serious tool, although I'd suspect it comes at a hefty price. >> >> Any recommendations? The need will be here in another six months or so. >> I want to do my research well ahead of that. > > Download the new PADS 2005 demo, from the Mentor website. > This is fully functional, but has a low ceiling (rather than time-bombed), > so you can try all features on simple designs, > and take as long as you want to evaluate. > If you load in a large design, all saves are disabled. > > You may also be able to get an early copy of the PCAD-PADS translator, > and trial migrating your databases.... > > -jg >Article: 81512
I should clarify that the reason for being concerned about this has to do with being able to move projects back and forth with vendors, collaborate and even farm out some of the work. With so many file formats out there, it'd be simpler to purchase the EDA system that has the most seats. -Martin "Martin" <0_0_0_0_@pacbell.net> wrote in message news:Xw21e.15525$C47.5467@newssvr14.news.prodigy.com... > I'll take a look at it. > > Any idea of what market penetration PADS has w/respect to others? How > strong is their user base? > > -Martin > > > "Jim Granville" <no.spam@designtools.co.nz> wrote in message > news:42425136$1@clear.net.nz... >> Martin wrote: >>> We've been using Altium's P-CAD for a few years (started as TangoEDA). >>> Currently running 2002 and very unlikely to upgrade as, in my opinion, >>> it is not a very good product and the company just loves to collect >>> their $1,500 a year by releasing bogus "service packs". Still lots of >>> very fundamental issues that remain without attention. >>> >>> Anyhow, the question is, what do we move up to? Not looking for the >>> $100K+ packages. What are people using that performs well for designing >>> (schematic) and laying out high-speed, high-complexity PCB's? I've >>> heard that PADS may have the largest installed base out there. I >>> remember getting a demo of Mentor's Expedition at a tradeshow. It >>> seemed like a pretty serious tool, although I'd suspect it comes at a >>> hefty price. >>> >>> Any recommendations? The need will be here in another six months or so. >>> I want to do my research well ahead of that. >> >> Download the new PADS 2005 demo, from the Mentor website. >> This is fully functional, but has a low ceiling (rather than >> time-bombed), so you can try all features on simple designs, >> and take as long as you want to evaluate. >> If you load in a large design, all saves are disabled. >> >> You may also be able to get an early copy of the PCAD-PADS translator, >> and trial migrating your databases.... >> >> -jg >> > >Article: 81513
Che Fing and Ljubisa.
I wanted to comment on the static/leakage power advantage of V4 vs
Stratix II, which is claimed to not exist based on Vaughn's experiments. I
have personally measured Static Power in both Virtex-4 LX60, LX100, 2S60,
and 2S90. Virtex-4 has 3-4x lower Static Power.
1) He did not make quote experimental results as yielding almost identical
static power for Virtex-4 and Stratix II. If you look carefully at all
actual bench measurements of total power for various designs, which were
presented. They have total power (at 25 C). They all show a significant
advantage for Virtex-4 (look at the DC i.e. zero frequency data points in
the slides).
2) Vaughn's method for calculating Virtex-4 and Stratix II worst case power
was as follows:
a) For Altera's Stratix II he did the following:
i) Use Power Play 2.1 and Select a Part and then select worst
case.
ii) Set the ambient temperature in such a way that it results in
an 85 C junction temperature, including rise of junction due to ThetaJA
iii) Record the sum of Vccint Power and VccPD power as Static
Power.
b) For Xilinx he did the following:
i) Use Xilinx Web Power 4.1 and Select a Part. Xilinx doesn't
report worst case static power as part of its tool, but does report Static
Power versus junction temperature, similar to the PowerPlay 2.1 tool
ii) Vaughn say he then uses a 2.5x worst case to typical ratio for
Static Power that has been publicly touted by Xilinx as a guideline to
customers.
iii) He then sums the Vccint Power and the VccAux power. He then
multiplies the sum by 2.5x.
The conclusion is that Virtex-4 and Stratix II have similar Static
Power and further that Vccaux power in Virtex-4 is 21-40% of total Static
Power when we consider, when we consider worst case.
Here's the error. Xilinx doesn't have a multiplier on Vccaux power of 2.5
(we have never stated this publically or privately). We have stated a 2.5x
multiplier ONLY on Vccint power for typical to worse case. There is no
scaler applied to Vccaux power, because the number is the Xilinx tools is
in fact quite invariable over process. Even the 2.5x value on Vccint only
is very conservative.
This error in using the 2.5x multiplier on Vccaux results in the Xilinx
Virtex-4 having the originally stated huge advantage in Static Power
compared to Stratix-II, both in typical and worst case.
Matt
che_fong wrote:
> Ljubisa Bajic wrote:
> > Hi,
> >
> > I just finished viewing the fpga power consumption net seminar that
> > Vaughn presented today. I found it informative and, to me, it apeared
> > to be objective.
> >
> > According to Vaughn's experiments and measurements, Stratix 2
> exhibits
> > lower dynamic power dissipation in the core and similar power
> > dissipation in the IO; beyond that his experimental results contend
> > that the highly touted static/leakage power advantage that V4 is
> > supposed to have is very minor; some might even say negligable.
> >
> > I am very curious to read Austin and Peter's opinions of this
> > presentation.
> >
> > Ljubisa Bajic
> > ATI Technologies
> > ---------- My opinions do not represent those of my employer.
>
> These guys are all biased. When you look at details, they show their
> side of the story. Power ? Big deal ! There are other more pressing
> issues ! High end FPGAs hardly go in portable devices ! ;-)
Article: 81514Hi, a few months ago I purchased a Spartan-3 Starter Kit from Xilinx. It had been working fine up until recently. I never had any problems configuring the device via iMPACT (using the Parallel III cable included in the kit), but now whenever I run Boundary-Scan Mode I get the error code "585", with it saying: // *** BATCH CMD : Identify PROGRESS_START - Starting Operation. Identifying chain contents .... done. ERROR:iMPACT:585 - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. PROGRESS_END - End Operation. When I load the ".cdf" file I had saved from previous download attempts that were successful, I get the error "1210": // *** BATCH CMD : setMode -bs Validating chain... INFO:iMPACT:1209 - Testing for '0' at position 12.The Instruction capture of the device 2 does not match expected capture. INFO:iMPACT:1206 - Instruction Capture = '11111111111111' INFO:iMPACT:1207 - Expected Capture = 'XXXX01000XX001' ERROR:iMPACT:1210 - '2':Boundary-scan chain test failed at bit position '1'. A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. I don't have any idea why this would happen. The only wires connected to the board is the power supply's wire and the JTAG cable. It is set in the mode I have used in the past to configure the device. The power supply hasn't changed either. I've tried using different designs to download to it but they give me the same error as well. Can anyone help me? I have searched Google for an answer but the only things I saw were too general and didn't seem to apply to my situation. Sorry if anything I said didn't make sense; I'm a beginner to the FPGA scene. Thanks for your help. Sincerely, Darien A. GothiaArticle: 81515
Hi, Subroto Datta wrote: > Hi Big, > > We'd like to hear your view about how Quartus can be made better for > your needs. Remove the 150 day restriction for the web edition. make it time unlimited as the ISE WebPack. This is the main factor for me to use Xilinx instead of Altera. And I am sure that for many more too. It is prefereable that it does not work for high-end FPGAs, CPLDs or Structured ASICs, and only for low/mid range devices, but works unlimited in time. > - Subroto Datta > Altera Corp. JaaCArticle: 81516
In article <1111782597.058021.232490@z14g2000cwz.googlegroups.com>, Brian Davis <brimdavis@aol.com> wrote: > I haven't used any of them recently, but I think there are several > 1-10 Gbps shift register/demux parts with diff. outputs available, > from the other usual suspects ( Micrel/Vitesse/Maxim/etc. ) Yeah, looked through all those before settling on the EP445. A lot of those are either overkill for my input, only 1:4 or they're really only good for SONET rates. What I want is a programmable 1:N and N:1 serializer, deserializer pair of chips with N = 2 to 16.Article: 81517
Quiet Desperation wrote: > In article <1111782597.058021.232490@z14g2000cwz.googlegroups.com>, > Brian Davis <brimdavis@aol.com> wrote: > > > I haven't used any of them recently, but I think there are several > > 1-10 Gbps shift register/demux parts with diff. outputs available, > > from the other usual suspects ( Micrel/Vitesse/Maxim/etc. ) > > Yeah, looked through all those before settling on the EP445. A lot of > those are either overkill for my input, only 1:4 or they're really only > good for SONET rates. > > What I want is a programmable 1:N and N:1 serializer, deserializer pair > of chips with N = 2 to 16. For what data-rate(s)? MarcArticle: 81518
Hi, Given a Spartan 3 chip, what I'd like to do is arrange two pins as an LVDS receiver *and* simultaneously have a regular 3.3 volt tristatable driver drive one of those pins. From what I know of the output cell architecture, it looks pretty likely that the hardware resources exist. My guys are using ISE with schematic entry, and I'm not an ISE driver, but they say it can't be done, or at least ISE won't let them do it. Any ideas? It would be very cool if this would work; it would save us a bunch of pins and a bunch of picofarads. Thanks, JohnArticle: 81519
In article <1111809749.291888.193280@f14g2000cwb.googlegroups.com>, Marc Randolph <mrand@my-deja.com> wrote: > For what data-rate(s)? Up to 3 Gbps on the fast side. Oh, and programmable logic levels, too. :) My currrent design is getting NCML from the upstream units. NCML. There's three other people in the world using NCML as far as I can tell. High level is 0 V, low level is -0.5V. Who invented that one? Thank goodness for On's Gigacomm parts. With differential signal they take almost anything from 0 to -2V. Those "any level in" buffers would be real nice in an FPGA. Hint, hint, Xilinx. And I want to go into an FPGA at 3 Gbps without any special Rocket I/O stuff. And as long as I'm dreaming, I'd like a pony.Article: 81520
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag
news:Vg21e.16$Xu3.385@news-west.eli.net...
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:d1r2nh$al1$04$1@news.t-online.com...
> > Hi
> >
> > below is possible the most dense divide by 2^n ever implemented on any
> FPGA:
> > divide by 2^37 takes only 3 Virtex Slices! (4 slices on spartan-3)
> >
> > Antti
>
> <snip of the original code>
>
> Antti -
>
> I'm truly amazed by the approach. I think I did things right in making a
> Verilog 32-bit, bit-serial NCO below. (Formats nicely with fixed space
> fonts). Only 1 level of logic makes for sweet timing. Thanks for
bringing
> this approach to light.
>
> - John_H
>
>
> // This is a bit-serial NCO with an initial
> // divide-by-32 implementing a 32-bit NCO word.
> //
> // Original credit is given to Antti Lukats
> // from a comp.arch.fpga posting 22 Mar 05.
> //
> // This version produced by John Handwork
> // with Synplify V8.0 for a Xilinx target.
> // - Some reg_input_delay route values (1.4ns)
> // were applied to Add, Cry in Synplify
> // to keep the logic to 1 level.
> // - Note that the intializations don't synthesize.
> // - Xilinx ISE v7.1 pushes 500MHz in the slow (-4)
> // XC3S50, limited by routing to the I/O cell.
> // - 4 Slices and an IOB is all it takes.
> //
> `define SRL /* synthesis syn_srlstyle = "select_srl" */
> //
> module TinyNCO ( input clk
> , output reg Fout /* synthesis syn_useioff = 1 */
> );
> parameter STEP = 32'd1000000;
>
> reg [31:0] End `SRL = 32'h0000_0001;
> reg [31:0] Inc `SRL = STEP;
> reg [30:0] Acc `SRL = 32'h0000_0000;
> reg Cry = 1'b0;
> reg Add = 1'b0;
>
> always @(posedge clk)
> begin
> End <= {End[0], End[31:1]};
> Inc <= {Inc[0], Inc[31:1]};
> Acc <= {Add , Acc[30:1]};
> {Cry,Add} <= Inc[0] + Acc[0] + (~End[0] & Cry);
> if( End[0] )
> Fout <= Add;
> end
>
> endmodule
>
Hi John,
nice :) !
would it be ok to add your code to the 'xilcores' project?
http://gforge.openchip.org
? you are of course welcome todo it yourself, just register
and I will add you to the project developers
Antti
Article: 81521"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote in message news:bhq941lt94e85vk90uvgvh0472sm883csj@4ax.com... > Hi, > > Given a Spartan 3 chip, what I'd like to do is arrange two pins as an > LVDS receiver *and* simultaneously have a regular 3.3 volt tristatable > driver drive one of those pins. From what I know of the output cell > architecture, it looks pretty likely that the hardware resources > exist. My guys are using ISE with schematic entry, and I'm not an ISE > driver, but they say it can't be done, or at least ISE won't let them > do it. > > Any ideas? It would be very cool if this would work; it would save us > a bunch of pins and a bunch of picofarads. > > Thanks, > > John > John, I can't imagine why you need to do something like this (LVDS diff input with one pin (p or n) also being an LVTTL output?), but here are some ideas. The first problem is that the LVDS for Spartan 3 is only defined for VCCO of 2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O) at the same time. You could add a third IOB (in a separate 3.3V VCCO bank) and connect it to one of your LVDS pins (in the 2.5V VCCO bank), but you'll have to play some tricks to insure that you don't overdrive the input-to-supply diode on the LVDS input (when the LVTTL output drives high). This trick could be as simple as adding a series resistor between the LVTTL pin and the LVDS pin -- to insure that the input diode never draws more than 10mA when the 3.3V output is driving high. BobArticle: 81522
Hi http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter there is prelimary info about Application that turns any FPGA into 8 channel frequency meter - all you need is FPGA and download cable (and the Frequency meter SW application of course) initial support is for Xilinx FPGA's only, Altera/Lattice will be added later AnttiArticle: 81523
Subroto Datta wrote: > We'd like to hear your view about how Quartus can be made better for > your needs. > > - Subroto Datta > Altera Corp. Please couple Quartus with the free version of ModelSim or whatever other Simulator that supports TestBench. A prof. in my Alma Mater insisted on using MaxPlus II and Quartus, and I hated it so much because the simulator that comes with it doesn't support testbench at all. Not to mention its clumsy user interface. I would just use Altera software for synthesis, map and PR, but for the simulation I prefer ModelSim or any other dedicated Simulator. HendraArticle: 81524
If you add the I/O symbols like IBUFGDS_LVDS_25(clock input) or IBUF_LVDS_25(normal input) to your schematic you will get a proper LVDS input implementation. With Spartan-3 you will need an external terminating resistor for input LVDS. For information on buffer types etc look in the "libraries guide". You will need to dig for the LVDS in particular as text searching this document does work well for finding a particular I/O standard buffer type. I think you can mix LVDS (input only and not DCI mode) with a 3.3V output but either check that with your FAE or try in on a development board. I have done this exactly on a Virtex2-Pro but personally have not tried this combination on Spartan-3. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote in message news:bhq941lt94e85vk90uvgvh0472sm883csj@4ax.com... > Hi, > > Given a Spartan 3 chip, what I'd like to do is arrange two pins as an > LVDS receiver *and* simultaneously have a regular 3.3 volt tristatable > driver drive one of those pins. From what I know of the output cell > architecture, it looks pretty likely that the hardware resources > exist. My guys are using ISE with schematic entry, and I'm not an ISE > driver, but they say it can't be done, or at least ISE won't let them > do it. > > Any ideas? It would be very cool if this would work; it would save us > a bunch of pins and a bunch of picofarads. > > Thanks, > > John >
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