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I am using single port generator, and my matlab programs generates RAM contents. Where can I find information on the format of .COE file required in Coregen?Article: 81576
Generally asynchronous resets have the same problems as any asynchronous
signal being used in synchronous logic. If the input fails set-up and hold
timing then some flip-flops may react to the reset on one clock edge and
some on the next. This is mainly a problem where flip-flop values are used
together in something like a state machine. The consequence of this is that
the state machine enters an unwanted state.
Personally my approach is to use a single flip-flop which the input reset
signal asynchronous resets (reset active) but the exit from the active reset
state is synchronous. Typically I would write this in VHDL as the example
below which has active high resets.
process(input_reset, clk)
begin
if (input_reset = '1') then
main_reset <= '1';
elsif (clk'event and clk = '1') then
main_reset <= '0';
end if;
end process;
The advantage with this structure is that get the best benefits of
asynchronous resets but get the also the advantage that the "main_reset"
signal is pulled into the timing analysis for the design.
John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk
"KCL" <kclo4_NO_SPAM_@free.fr> wrote in message
news:42468143$0$3131$8fcfb975@news.wanadoo.fr...
> Is there any hazard to mix synchronous and asynchronous reset?
> I am making an RS232 controller and I generally use asynchronous reset in
> my design except in a process that serve to load the control word
> (indicate speed, data length, parity...) where I load the control word
> when reset = '1' or ctr_load ='1' , like that it load the control word at
> every reset and when we ask to reload it by ctrl_load
>
> Regards
>
> Alexis
>
> my code :
>
> decodeur : process(clk,rst)
> begin
>
> if rising_edge(clk) then
> if ctl_load='1' or rst='1' then
> parity_bit <= ctl_word(2);
> parity_type <= ctl_word(1);
> stop_bit <= ctl_word(0);
> case ctl_word(7 downto 5) is
> when "000" => nb_count <=
> std_logic_vector(to_unsigned((1843200/frequency_0-1),log2(1843200/frequency_0)));
> when "001" => nb_count <=
> std_logic_vector(to_unsigned((1843200/frequency_1-1),log2(1843200/frequency_0)));
> when "010" => nb_count <=
> std_logic_vector(to_unsigned((1843200/frequency_2-1),log2(1843200/frequency_0)));
> when "011" => nb_count <=
> std_logic_vector(to_unsigned((1843200/frequency_3-1),log2(1843200/frequency_0)));
> when "100" => nb_count <=
> std_logic_vector(to_unsigned((1843200/frequency_4-1),log2(1843200/frequency_0)));
> when "101" => nb_count <=
> std_logic_vector(to_unsigned((1843200/frequency_5-1),log2(1843200/frequency_0)));
> when "110" => nb_count <=
> std_logic_vector(to_unsigned((1843200/frequency_6-1),log2(1843200/frequency_0)));
> when "111" => nb_count <=
> std_logic_vector(to_unsigned((1843200/frequency_7-1),log2(1843200/frequency_0)));
> when others =>
> end case;
> case ctl_word(4 downto 3) is
> when "00" => data_bit <= "00010000";
> when "01" => data_bit <= "00100000";
> when "10" => data_bit <= "01000000";
> when "11" => data_bit <= "10000000";
> when others =>
> end case;
>
> end if;
> end if;
> end process decodeur;
>
Article: 81577"Sea Squid" <Sea.Squid@hotmail.com> wrote in message news:4247a8cd@news.starhub.net.sg... > I am using single port generator, and my matlab programs generates > RAM contents. Where can I find information on the format of .COE > file required in Coregen? > > > Found it in <XILINX>/coregen/data/ already.Article: 81578
Hi since there seems to be quite a lot of interest of the advance use of SRL16 in Xilinx FPGA's I decided to sponsor a little mini Contest for the best SRL16 based micro IP-Core design. http://wiki.openchip.org/index.php/Contest:SRL16 I think and hope that there are a lot more advance use possibilities in addition to what I have discovered or what have been published by Xilinx. antti@truedream.orgArticle: 81579
I am using NCVerilog and Virtex2-6000. I tied RST pin of the DCM1 to 1'b0
in RTL code. RTL simulation was all right, but gate level simulation failed
after
at first rising clock edge.
SST2 Database Write API -- DWAPI Version 05.10-s016 -- 09/15/2004
Copyright 1997-2003 Cadence Design Systems, Inc.
Timing Violation Error : RST on instance sim_sincos.i_sincos.DCM1 must be
asserted for 3 CLKIN clock cycles.
Warning! Timing violation
$setuphold<setup>( posedge I0:675 PS, negedge S:136 PS, 553 :
553 PS, 0 : 0 FS );
File: /home/qijun/projects/wlan_test/sincos/fpga/sincos.v, line
= 1465
Scope: sim_sincos.i_sincos.buf_80m_n
Time: 675 PS
Article: 81580Go to Opencores.com "KCL" <kclo4_NO_SPAM_@free.fr> wrote in message news:4247e494$0$808$8fcfb975@news.wanadoo.fr... > Hi, > As I am making a PS/2 keyboard vhd , I am looking for scancodes of an azerty > keyboard to convert code from keyboard to ascii code. Does anyone know where > i can find that because I only found it for qwerty keyboard. > > Thanks > > Alexis > >Article: 81581
Ken Smith wrote: > In article <d272lg$80c$1$830fa7a5@news.demon.co.uk>, > Andrew Holme <andrew@nospam.com> wrote: >> Is there any way to use the JTAG pins of an EPM7128S for user I/O, >> without permanently commiting them as I/O and thereby losing the >> JTAG capability? I want to download data from the PC, via a >> ByteBlaster cable, into a 2kx8 static RAM connected to the CPLD. I >> suppose I could add some jumpers for re-patching the 10-way header >> to standard I/O pins; or have a second, dedicated header for the RAM >> download; but I would prefer to use the JTAG pins if possible. > > I believe that you can make the other pins of the CPLD go high and > low via the JTAG port. I don't have my Altera data book here. It > will be very slow. Thanks Ken. I probably won't need to fill more than 256 bytes of the RAM and I don't mind if it takes a couple of seconds. Does anyone know where I can find info on how to do this? I have the "Altera ByteBlaster" device and the "Altera JTAG Server" service running on Windows NT. Are the APIs documented? I also have Quartus II 4.1 Web Edition installed. Could someone Does anyone know how to do this?Article: 81582
"Andrew Holme" <andrew@nospam.com> schrieb im Newsbeitrag news:d28qta$8qs$1$8302bc10@news.demon.co.uk... > Ken Smith wrote: > > In article <d272lg$80c$1$830fa7a5@news.demon.co.uk>, > > Andrew Holme <andrew@nospam.com> wrote: > >> Is there any way to use the JTAG pins of an EPM7128S for user I/O, > >> without permanently commiting them as I/O and thereby losing the > >> JTAG capability? I want to download data from the PC, via a > >> ByteBlaster cable, into a 2kx8 static RAM connected to the CPLD. I > >> suppose I could add some jumpers for re-patching the 10-way header > >> to standard I/O pins; or have a second, dedicated header for the RAM > >> download; but I would prefer to use the JTAG pins if possible. > > > > I believe that you can make the other pins of the CPLD go high and > > low via the JTAG port. I don't have my Altera data book here. It > > will be very slow. > > Thanks Ken. I probably won't need to fill more than 256 bytes of the RAM > and I don't mind if it takes a couple of seconds. > > Does anyone know where I can find info on how to do this? I have the > "Altera ByteBlaster" device and the "Altera JTAG Server" service running on > Windows NT. Are the APIs documented? I also have Quartus II 4.1 Web > Edition installed. > > > Could someone Does anyone know how to do this? > > sure someone knows! there are many ways todo it, the most easy is possible to write a small JAM (STAPL) program that will do what you need. in case you are able able to use Delphi we also have and application that reprograms parallel flash that is connected to several Altera PLDs that could be a start point, hmm that code could serve as reference in any case? hm I was about to upload this project to http://gforge.openchip.org with sources but havent had time yet anttiArticle: 81583
Hi Someone must have ask this question before. Is it a good idea to use verilog's reg to declare a large block of memory and expect it will be synthesizable? ThanksArticle: 81584
Peter Alfke wrote: [...] > Spartan-3 has lower performance than Virtex-II, Howdy Peter, Could you expand on this? I know that Xilinx likes to push Virtex as the performance family and advertises V2 as being faster than S3 (and on a few things it is)... but looking at the detailed speedprint numbers, on average they look to be quite quite comparable, and on some parameters, S3 is noticably faster - presumably due to 90nm. > and the TQ144 is > probably the worst available package from a signal-integrity point of > view. [...] Agreed. If he can somehow swing getting to a BGA, it could possibly solve his I/O problem as well. MarcArticle: 81585
Several more tests were conducted using the same test configuration. During this test I monitored the state of the done/program pins of all of the devices prior to the failure. The test would read and store the D/P pins status, attempt to program the devices, if failed to program all eight after five attempts then report the original status of the D/P pins. Then report the status of the D/P pins after an attempt was made to program the devices. I wanted to also collect enough data in an attempt to determine if the failure of the internal oscillator could be duplicated. I was able to replicate the failure three more times and it would appear that when the device fails, the initial state of the D/P pin is high. After an attempt was made to program the devices, the D/P pin latched in the low state. It also appears that with every failure that something happens with the 16MHz oscillator in that I no longer see anything in that area. What is interesting is that if the oscillator was dead, I would not expect the D/P pin to latch low. Maybe it is not a sampled input but is trully edge triggered. Also note that once the power was cycled, that in all three cases the oscillator returned to normal and the devices were able to be programmed.Article: 81586
Marc, Peter, and everyone else who has been helping me, I think I've come
up with a solution.
My goal was to be able to get 1 Gbps TO each FPGA and to aggregate 1 Gbps
total from all the FPGAs, and Marc's suggestions tipped me off as to how I
might do this: arrange them in a ring.
I have enough pins (barely) that each FPGA n can have 14 DDR LVDS pairs in
from the n-1 fpga, and 14 DDR LVDS pairs out to the n+1 FPGA. We partition
these in the following way:
1. 5 in / 5 out are used for the broadcast data bus
2. 5 in / 5 out are used for the aggregate data bus
3. 4 in / 4 out are used for direct inter-FPGA communication
So I'll have this 20 FPGA "ring" with one extra link: the source/sink FPGA
which will also talk to my gig-E nic.
Now, to broadcast data to all of the FPGAs, the master FPGA first sends
the data to FPGA 0, which makes a copy in an internal buffer and then
sends it to FPGA 1, etc. We use the 5 high speed lines: 4 for data and one
for an EN pulse.
To aggregate data from the FPGAs, the bus master FPGA first streams an
empty packet to FPGA 0; fpga zero passes this packet unchanged to fpga 1,
but notes that "packet -1 just went by", and so next sends its own output
to FPGA 1 (or a null packet, saying "I have no data to send"). FPGA 1
waits until it has passed FPGA 1's packet through before sending its own;
and so on. In this way, FPGA n waits until n-1 has sent, and then sends
N+1. At the end, the bus master FPGA collects all of this data and then
restarts the cycle.
There are a number of advantages here:
1. Routing: each FPGA has a 2-3" LVDS connection with its neighbors;
that's it. ~700 ps delay there on FR4 board (if I'm remembering my High
Speed Digital Design numbers right).
2. Clock skew. The clock skew between two adjacent FPGAs is likely to be
very very small, because even if they're fed by a long clock line from the
clock source, the differential in that clock line between them is probably
small.
3. Cost: I can route almost all of these traces on the top layer of my
board; I can probably get away with using a 4-layer board now.
4. Flexibility: If I have an application where, say, what I really want is
to have a long chain of FPGAs, with n passing computed data to n+1 for
further processing, I can do it this way.
5. physical geometry:
I can snake them around my board like:
4 5 14 15
3 6 13 16
2 7 12 17
1 8 11 18
0 9 10 19
MASTER
NIC
which means that the master FPGA is still relatively close to the two
FPGAs it needs to talk to, 0 and 19.
> If the clock nets going to each target device are kept the same length,
> clock skew should not be a concern. The window is more of a
> challenge...
>
> Approximate worst case timing:
>
> Tickofdcm: 1.75 ns (basicly clk to out)
> prop delay:~1.45 ns (approx prop delay of 8 inches of trace)
> Tiopick: 1.89 + 0.75 ns (setup time for LVDS)
> ---------------------
> total: 5.84 ns
>
> WAG at best case (just to have some numbers to throw around):
>
> Tickofdcm: 1.25 ns (basicly clk to out)
> prop delay:~1 ns (prop delay of approx 6 inches of trace)
> Tiopick: 2 ns (setup time for LVDS)
> ---------------------
> total: 4.25 ns
>
> So if these numbers are close to correct (they might not be), the data
> would appear at the next chip as if it had been delayed by a clock
> cycle (although the best case WAG cuts the margin very close).
Unfortunately, for the above configuration the WAG would likely be much
shorter, and thus it might not work. The worst case would be
Tickofdcm: 1.75 ns
prop delay: 600 ns
Tiopick: 1.89 +0.75 ns
--------------------
5 ns
and the WAG best would be 3.85 ns. Ouch. And this is with using all the
tricks I know, like registers on all the IOBs, etc.
Given that, and the very short distances (compared to before) these traces
are going, would it be wise to abandon lvds and DDR and just have adjacent
links be 125 MHz single-ended?
Oh, my kingdom for an ibis simulator!
Thanks again to everyone for the help!
...Eric
Article: 81587
On Mon, 28 Mar 2005 09:27:14 -0500, Eric <acetylcholinerd@gmail.com> wrote:
>Marc, Peter, and everyone else who has been helping me, I think I've come
>up with a solution.
>
>My goal was to be able to get 1 Gbps TO each FPGA and to aggregate 1 Gbps
>total from all the FPGAs, and Marc's suggestions tipped me off as to how I
>might do this: arrange them in a ring.
>
>I have enough pins (barely) that each FPGA n can have 14 DDR LVDS pairs in
>from the n-1 fpga, and 14 DDR LVDS pairs out to the n+1 FPGA. We partition
>these in the following way:
> 1. 5 in / 5 out are used for the broadcast data bus
> 2. 5 in / 5 out are used for the aggregate data bus
> 3. 4 in / 4 out are used for direct inter-FPGA communication
>
>So I'll have this 20 FPGA "ring" with one extra link: the source/sink FPGA
>which will also talk to my gig-E nic.
You may want to do a google search on the following two keywords: splash FPGA
If you look at the sixth hit, page 3, you see a bunch of FPGAs in a
configuration similar to yours (from about 12 years ago):
http://www.ecs.umass.edu/ece/tessier/courses/697ff/lect16-ece697f.ppt
There is lots more out there on Splash and Splash2.
Another research FPGA project that may interest you would start with the
google search of: PAM FPGA
Philip
Philip Freidin
Fliptronics
Article: 81588well the realization i arrived at was that probably the Spartan 3 would not be the platform to try and do complex math ops, but instead to do all the complex design stuff up front and only have the processor do the simple arithmetic ops to get the data I needed. -htArticle: 81589
"Antti Lukats" <antti@openchip.org> wrote in message news:d2348g$cjb$04$1@news.t-online.com... < snip> > Hi John, > > nice :) ! > would it be ok to add your code to the 'xilcores' project? > http://gforge.openchip.org > ? you are of course welcome todo it yourself, just register > and I will add you to the project developers > > Antti Since I hadn't run a full simulation, I'd be hesitant to throw it in there without a solid double-check but feel free to add the code yourself if you like. Anyone is welcome to try to leverage this approach whether for your contest or for commercial projects. Anyone working with SRLs in this sense should be aware: the global reset to the Xilinx device could deassert asynchronously to different SRLs at different clocks, knocking off the needed alignment between the SRLs. I'd suggest working in a global enable for all the SRLs that waits a few clock cycles before letting everything run. Another approach would be to use the BUFGCE primitive in the newer families using the same delayed enable to gate the clock to the entire FPGA rather than just the enables to the SRLs. I also want to double check with ISE v7.1 service pack 1 and/or the hotline to see if the minimum clock cycle for the SRLs is communicated properly. ISE v6.3.3i gave warnings if I tried to run too fast and 7.1i didn't complain at all about shift frequencies approaching 500 MHz. The SRL performance numbers have either improved *significantly* over the previous speed files or the information got lost. I'm hoping the former is true. - John_HArticle: 81590
http://www.computer-engineering.org/ KCL wrote: > Hi, > As I am making a PS/2 keyboard vhd , I am looking for scancodes of an azerty > keyboard to convert code from keyboard to ascii code. Does anyone know where > i can find that because I only found it for qwerty keyboard. > > Thanks > > Alexis > >Article: 81591
I do not have FPGA experience, and I am not sure if my question make sense. Assume that we have a set of C++ code of various set of signal processing, filtering, decision making, neural network, fuzzy logic etc. Is it possible to convert (some how) these C++ code to run in FPGA ? Is there a tool to convert C++ to FPGA code?Article: 81592
> I was able to replicate the failure three more times and it would > appear that when the device fails, the initial state of the D/P pin is > high. After an attempt was made to program the devices, the D/P pin > latched in the low state. I need to retract the above statement. As it turns out, the software that was being used to monitor the status of these pins inverted them prior to displaying it. So, the devices appear to go into the program state. In this last test I wanted to try and decouple the CORE that was being loaded into the device. For this test, all that was done was to cycle the supply. I used a 5mS off time and cycled at 100Hz. Using the spectrum analyzer I monitored the 16MHz clock. After about 10 minutes of testing, the oscillator had failed to start. I probed the remaining devices and found that three others also had failed to start. I then started to increase the off time using the one-shot mode. I noted that at about 200mS - 250mS two of the devices oscillators restarted. The third device took more than a second of off time before starting. During the about tests, I noted that the D/P pin was low for all devices during the test, reguardless of the state of the oscillator. Also, during the tests, no attempt was made to reprogram the devices. Only the spectrum analyzer with the near field probe was used to determine if the part had failed.Article: 81593
I bought the Digilent XC2 board (Xilinx CoolRunner II XC2C256 TQ144) a while back for electronics hobby stuff and I was wondering anyone could help with ... I want to expand/add to the board some LEDs and slide switches so I can experiment with more stuff. I want to add a buffer in between the switches and LEDs but I am not sure types to use. 1.) I see in the manual that the XC2C256 on the board has different types of IOs (LVTTL, LVCMOS33, etc.). Am I correct in assuming that I can pick a buffer (like say one that is LVTTL) and then when I program the chip just select that type for the IO for each pin in the WebPack ISEs "Assign Package Pins" and that will be OK? 2.) Do you have recommendation for what is best IO type to use (I think the board has power supply for 3.3 volts - -I use the batteries)? 3.) Is putting buffers between LEDs and switches correct thing to do in order to ensure safety for the main XC2C256 chip or does the chip have protection and I can put an LED directly to the IO of the chip (with a resistor -- size?)? Any recomendations or ideas and any hobby level infor fo rthe XC2 board would be greatly appretiated!Article: 81594
Gregory C. Read wrote: >"Thomas Rudloff" <thomas_rudloff_REMOVE_SPAM@gmx.net> wrote in message >news:3ao6ojF6decsqU1@individual.net... > > >>KCL wrote: >> >> >> >>>Is there a way to make a global reset on startup of fpga?? >>> >>>Thanks >>> >>>Alexis >>> >>> >>> >>> >>> >>> >>You do not need to think about this. It happens automaticly every time >>the FPGA is loaded. >> >>Regards >>Thomas >> >> > >Sure, my Actel anti-fuse FPGA resets every time it is loaded.....NOT. It >does depend on the technology. I have used a simple RC to accomplish a >necessary reset. But there is usually some kind of system reset that can be >used. > > > Sorry I was focused on SRAM based FPGAs. But I guess your antifuses get reset as well when you "reload" them.Article: 81595
Catapult C by Mentor Graphics Ustuiosima Huslova wrote: > I do not have FPGA experience, and I am not sure if my question make sense. > > Assume that we have a set of C++ code of various set of signal processing, > filtering, decision making, neural network, fuzzy logic etc. > Is it possible to convert (some how) these C++ code to run in FPGA ? > Is there a tool to convert C++ to FPGA code? > > >Article: 81596
You can use the FPGA I/O directly, if you apply some common sense. The sink or source current should be limited to 20 mA ( this may be overly conservative, but I like to play it safe), so LEDs must have a current-limiting resistor. Avoid pulling the pins higher than Vcc or lower than Ground, but there are also protective diodes that prevent excessive voltages. Use reasonable care against electrostatic discharge (walking over a nylon carpet in low-humidity environments can easily generate 10 000 V or more.) Do not discharge this directly into the pins. Peter Alfke, Xilinx Applications.Article: 81597
Eric wrote:
> Hello! I'm trying to build a 20-FPGA (spartan-3s, XC3S400-TQ144s) board
> for a class project to investigate the use of FPGA arrays for accelerating
> scientific competition.
Forgive my curiosity, but why are you going to use a cluster of FPGAs
to perform scientific computations? Wouldn't a bunch of high-speed
floating-point DSP processors be better? FP calculations, which are
not well supported by the low-cost FPGA chips (huge amount of shifting
etc.), are the core of most scientific computations.
Best regards
Piotr Wyderski
Article: 81598Hi, I'm picking up FPGA/CPLD design after a brief introduction in school a long time ago. My tool setup is the utilities supplied by Xilinx ISE 7.1 on Linux, with Icarus Verilog and gtkwave for pre and post synthesis simulation. Am I correct in thinking that Xilinx left some of the built in simulation capability out of the Linux version of their Webpack? Anyone else out there in the same boat? Are there any good FAQs out there to get me quickly started using this sort of chain? Are there any classes or seminars based around a Xilinx+Icarus combination, especially in the Portland, OR area? regards, Alex Alex at dee en el en kay dot comArticle: 81599
"John_H" <johnhandwork@mail.com> wrote in message news:wkW1e.1$4R6.126@news-west.eli.net... <snip> > I also want to double check with ISE v7.1 service pack 1 and/or the hotline > to see if the minimum clock cycle for the SRLs is communicated properly. > ISE v6.3.3i gave warnings if I tried to run too fast and 7.1i didn't > complain at all about shift frequencies approaching 500 MHz. The SRL > performance numbers have either improved *significantly* over the previous > speed files or the information got lost. I'm hoping the former is true. > > - John_H For those who care, in the slower version of the XC3S50 (-4) the registered SRL limits the frequency to 285 MHz. I couldn't get the newer software to report this limit; there is now a change request to make this value visible.
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