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There is also a cost advantage with fpgas until you get into high
volumes. The fact of the matter is FPGAs are on 90nm technology now,
and will compete head to head with ASIC on a 0.25 micron fab. Most ASIC
starts can get away with less than bleeding edge geometries, so that
will tend to lessen the gap between the performance of an FPGA vs
performance of an ASIC done with the coarsest geometry that wil get the
job done.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81176"Douglas Sykora" <djsykoraNOSPAMM@execpc.com> wrote in message news:113lae56ejqj0f5@corp.supernews.com... > > "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message > news:1111083250.701659.304200@o13g2000cwo.googlegroups.com... > > Hi Doug, Tommy: > > > > > Strange. > > > > Our DSE guys are equally confused. Things are working fine for us... > > > > For us to be able to completely debug your issues we need see your > > design, or at least the full DSE output logs (*.dse.rpt) with the > > -debug flag on. > > > > We tried using seeds in the form n1-n2 and it seemed to work fine for > > us on 4.2 SP1. Maybe you can try separating your seeds with commas in > > case there is something weird there. Another possibility is that your > > base compile has an error or no-fit, which causes compilation to halt > > in a similar way to what you describe. > > > > Regards, > > > > Paul Leventis > > Altera Corp. > > > Paul, > I submitted a mysupport SR two weeks ago and I am waiting for some support > to > help me out here. (SR#10490208) I attached lots of reports and my design. > I talked to one of the engineers at mysupport late yesterday and they said > they are > now bumping it up to the higher level engineers. Any help you can provide > will be greatly > appreciated. > > I was not aware of the -debug flag. I will attempt to run DSE with this > flag on and > get another update to the mysupport engineers. > > Also, my design does fit. There is no "no-fit" error. That would at least > produce an error message. In my case there is no error message. > > Thanks for your help Paul, > > Doug > > I looked through all the DSE documentation and could find nothing about a -debug flag for DSE. I also tried running DSE from the command line, which I never tried before, and it ran without the stopping after compiling the base. I tried it in both the local and in the distributed computing mode. Both worked! This weekend I will try running it with five or six distributed computers okay. I'll let you know how it goes. DougArticle: 81177
Hi Luc, I don't have much to add -- Ben has covered most of the high points. > Has someone seen samples yet, knows something more how they compare > (performance, pricewise). On a performance front, you will find that Cyclone and Cyclone II have a significant performance advantage over Spartan-3. We're talking 50-60% (core performance on 100+ designs, comparing fastest speed grade to fastest speed grade using best-possible software settings). But don't take my word on it. Download our freely available Quartus II Web Edition and give your design a whirl in Cyclone/Cyclone II. Do the same for Spartan-3. Regards, Paul Leventis Altera Corp.Article: 81178
After waiting an hour for Xilinx to return my phone call, I decided to attempt further tests. From previous failures it seemed that the supply had to be turned off for a long time in order to recover from this failure. Using the dual FET test setup I started pulseing the power to the FPGAs. Using a scope which was connected to the device, I started out pulsing the power off for 10uS. I then tried to program the device 5 times. The device was in the same state, so I increased the off time and repeat the process. At 1ms (0.001 seconds) the part would still not recover. Thinking that the device may have actually been damaged I decided to try a much longer power cycle of about 5 seconds and sure enough, the part came back to life. Of course, none of this helps me. I have started another test where I do not attempt to reprogram the devices. This will allow me to determine the state of the control pins prior to attempting the reload. I am starting to suspect that the devices internal oscillator has a problem. There is very little information about it. There appears to be no way to detect it's failure. Has anyone seen any detailed information about how the oscillator was designed? Was the same design used for all Xilinx devices? I am thinking to try and detect the internal oscillator with a spectrum analyzer.Article: 81179
On Sun, 13 Mar 2005 16:06:53 +0100, "Piotr Wyderski"
<wyderskiREMOVE@ii.uni.wroc.pl> wrote:
>Hello,
>
>I would like to start a serious adventure in FPGA development,
>so which HDL would you recommend me? I can restrict myself
>to a single chip vendor (i.e. Altera, because their chips are quite
>cheap and very easy to obtain in small quantities in Poland),
>thus the spectrum of alternatives should be wider. The most
>important thing is good support of genericity, for instance:
>
> generic type vector{N} where {const N : positive} is group of N bits
> x : vector(32); -- x : std_logic_vector(31 downto 0)
>
>or even constants:
>
> generic const square{N} : type of N where {const N} is N*N;
> const nine : int is square{3};
>
>The languages I know about are:
>
>VHDL: very disappointing, the nicest part of Ada has ben removed.
>No support for anonymous types, stiff and annoying syntax, weak
>interface inference (needs explicit component specifications).
>
>Verilog: same as above + lack of generate statements, so how
>does one specify generic pipelines (very useful e.g. in parallel
>CORDIC specifications)?
>
>AHDL: I don't know much about it, because I can't find a good manual.
>
> Best regards
> Piotr Wyderski
If you're doing FPGA development, then you've only got 2 serious
choices; VHDL and Verilog. You can find any amount of VHDL vs. Verilog
debate on Google (mostly uninformed, plain incorrect, prejudiced, or
all 3). The bottom line, if you're already programming-literate (as
you clearly are), is that you'll find Verilog more frustrating than
VHDL. VHDL is at least based on Ada, so is consistent, and relatively
modern (for 1980).
Both languages were designed in the early 80's; VHDL by committee (it
shows), Verilog by one person (it shows). Unfortunately, Verilog's
design was exceptionally poor even then, and still is. The market for
these languages is small, and the major EDA vendors have always had a
vested interest in stability, and not progress; the end result is that
we have to put up with 25-year-old languages.
Verilog-2001 is much more usable than the 1995 version, but it's still
Verilog. SystemVerilog is not an option for you, since it's too new to
be supported. SystemVerilog is largely again a political creation, and
it may or may not catch on in the longer term, depending on how
gullible we all are (very, if history has anything to tell us).
If you want to write a preprocessor, you should generate Verilog-1995
output, not VHDL; it's better supported.
Other minority languages (for FPGA development, anyway):
Handel-C (http://www.celoxica.com/methodology/c2fpga.asp): C+Occam;
interesting, and probably the only realistic choice outside
VHDL/Verilog
SystemC (www.systemc.org): C++ class library; big in system-level
design and architecture exploration, not good for low-level design
SpecC (http://www.ics.uci.edu/~specc/): Extensions to C
Confluence (www.confluent.org): a functional programming language
JHDL (http://www.jhdl.org/): Java-based
RHDL (http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/) Ruby-based
AHDL: vendor-specific; forget it
Article: 81180Hi Mac, thanks for your thoughts. I got the idea for a PHY-less implementation from http://www.fpga4fun.com where they do it without even a transformer but capacitive coupling and a few transistors.... There's also an article at EDN where this is discussed, although they're hinting at using an X485 type of transceiver to buffer the signal. My idea was to save on this too. 10-base has a simpler link pulse scheme (NLP) which (afaik) allows for simple differential signaling, whereas faster Ethernet uses FLPs that might differ here. I'll read up on this. Also thanks much for the ASCII art - it's been working fine without the two 10k, but I'll give it a try. As to the reason why - well, a chip saved is a chip saved.... best, SukandarArticle: 81181
Ben & Paul, Thanks for the feedback. I wonder what X & L could add to their defence. What about DDR or DDR2 support? This is certainly somthing I'm looking for. Multipliers are benificial but not a necessity. Regards, Luc On 18 Mar 2005 13:55:56 -0800, "Paul Leventis" <paul.leventis@utoronto.ca> wrote: >Hi Luc, > >I don't have much to add -- Ben has covered most of the high points. > >> Has someone seen samples yet, knows something more how they compare >> (performance, pricewise). > >On a performance front, you will find that Cyclone and Cyclone II have >a significant performance advantage over Spartan-3. We're talking >50-60% (core performance on 100+ designs, comparing fastest speed grade >to fastest speed grade using best-possible software settings). > >But don't take my word on it. Download our freely available Quartus II >Web Edition and give your design a whirl in Cyclone/Cyclone II. Do the >same for Spartan-3. > >Regards, > >Paul Leventis >Altera Corp.Article: 81182
I guess everyone has different experiences. I find Verilog less
frustrating after writing VHDL for about 3 yrs, but in reality I'm not
adverse to using either. I sure don't miss simulating 9-level SLVs when
less than 1/2 those states occur inside an FPGA design is a nice bonus.
I sure do miss VHDL's records for testbenching (but not the limitations
of driving fields from two directions!). Verilog can be ambiguous. VHDL
can be redundant.
I don't think languages designed by one person is a bad thing; I'm not
sure if I could live without Perl. My opinion on design-by-comittee is
summed up by, Where the heck is VHDL-200x? ("Fast Track", no less). I
used to sit in on SMPTE spec meetings where the group argued over
whether a word should be "shall" or "will" for 2 hrs. The point being
most of the time was spent innovating nothing. Having 'n' engineers in
a room, n>1, means a level of contention proportional to n, and
functionality is diluted in the process to keep everyone happy. I'm
sure the new VHDL will be awesome but I'm not holding my breath.
-- Pete
> If you're doing FPGA development, then you've only got 2 serious
> choices; VHDL and Verilog. You can find any amount of VHDL vs.
Verilog
> debate on Google (mostly uninformed, plain incorrect, prejudiced, or
> all 3). The bottom line, if you're already programming-literate (as
> you clearly are), is that you'll find Verilog more frustrating than
> VHDL. VHDL is at least based on Ada, so is consistent, and relatively
> modern (for 1980).
>
> Both languages were designed in the early 80's; VHDL by committee (it
> shows), Verilog by one person (it shows). Unfortunately, Verilog's
> design was exceptionally poor even then, and still is. The market for
> these languages is small, and the major EDA vendors have always had a
> vested interest in stability, and not progress; the end result is
that
> we have to put up with 25-year-old languages.
>
> Verilog-2001 is much more usable than the 1995 version, but it's
still
> Verilog. SystemVerilog is not an option for you, since it's too new
to
> be supported. SystemVerilog is largely again a political creation,
and
> it may or may not catch on in the longer term, depending on how
> gullible we all are (very, if history has anything to tell us).
>
> If you want to write a preprocessor, you should generate Verilog-1995
> output, not VHDL; it's better supported.
>
> Other minority languages (for FPGA development, anyway):
>
> Handel-C (http://www.celoxica.com/methodology/c2fpga.asp): C+Occam;
> interesting, and probably the only realistic choice outside
> VHDL/Verilog
>
> SystemC (www.systemc.org): C++ class library; big in system-level
> design and architecture exploration, not good for low-level design
>
> SpecC (http://www.ics.uci.edu/~specc/): Extensions to C
> Confluence (www.confluent.org): a functional programming language
> JHDL (http://www.jhdl.org/): Java-based
> RHDL (http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/) Ruby-based
> AHDL: vendor-specific; forget it
Article: 81183Well, Suffice it to say, I don't agree with Paul, but that should come as no surprise. Spartan 3S100E was just announced, so to ask if a 3S1500E is sampling is a bit like asking if we are ready to go visit Mars. Seriously, announcement of the first available part usually means that the rest of the family is three to six months from even being taped out (for us, or Paul). Announcement of the first part into production also means that the time till all parts are in production is out from three to six months (again, for us, or Paul). Sometimes we do better than that. Sometimes they do better than that. Sometimes we both do worse. And suffer for it. Depends on a lot of factors: are they any errata to fix? how many layer changes need to be made? is the process yielding? have we passed the process qualification? have we passed the product qualification? do we have parts ready to ship? so on and so forth. For example: the 2S60 was announced as having received wafers on June 2, 2004. http://www.altera.com/corporate/news_room/releases/releases_archive/2004/products/nr-stratix2_sampling.html Then, they just recently admitted they will ship the final production version of that 2S60 part with the Iccint surge current fixed by the end of this month (3/31/2005). I am likely to believe this, as we just tested the 2S90, and the Iccint surge is all gone. We announced the 4VLX25 on 6/28/2004 (lagging Altera, but we actually shipped five parts on boards on this date and the customer was USING them!). http://www.xilinx.com/prs_rls/silicon_vir/0480v4shipment.htm Then, we just recently announced we are shipping production on this part 1/31/2005: http://www.xilinx.com/prs_rls/silicon_vir/0517v4prodqual.htm So, 9 months for a 2S60 from announcement of first wafer to production (unconfirmed, as it isn't 3/31 yet), and 7 months for the Xilinx 4VLX25 (confirmed). Not much of a difference there. If you go back and track every product announced, to every ES, to every product released to production, you will find a remarkably similar time line. After all, both Xilinx and Altera use world class fabs (UMC and TSMC), and both use a leading edge process, and the differences will be mostly related to factors that are totally random in nature (if we are going to be honest about it). Go talk to your Xilinx FAE, and get the timeline for what you need. Oh, and take the performance boasts (for these low cost parts) from everyone with a grain of salt. Until you see what your needs are, you are unlikely to be able to evaluate if there is even a difference in performance, and if that performance difference even matters for your application. Sure, Spartan 3 (and 3E) have the 18X18 multipliers. And Altera has elements they are proud of in Cyclone 2. But just like Virtex 4 vs Stratix 2, you are going to have to wade through a lot of very technical information if you are trying to compare benchmarks. Best you test your application, regardless. AustinArticle: 81184
Luc, Lattice EC/ECP are not 90nm, but 130nm at the 90nm cost. Excelent FGPA architecture, great DDR performance (400Mbs). Almost all the devices are available today. ispLEVER is free at the latticesemi.com rgds, cristianArticle: 81185
Never, never, gate your clock. Ie, always use
process (HOST_WR)
begin
if HOST_WR'event and HOST_WR='1' then
if HOST_CS = '0' then
rather than
HOST_CS_WR <= HOST_WR or HOST_CS;
process (HOST_CS_WR)
begin
if HOST_CS_WR'event and HOST_CS_WR='1' then
In many FPGAs, you simply aren't allowed to, as local logic cannot be
routed to clock inputs. Even if you can, you add delay twice: once for
the OR gate itself, and again for the wiring from the OR gate to the
FF's clock input, which will have to be local logic wiring, not a
dedicated clock net. This is to invite clock-skew problems (which, be
it said, are independent of the clock frequency: skew can hit you with
a 1kHz clock).
"vax, 9000" <vax9000@gmail.com> wrote:
:Mike Treseler wrote:
:
:> vax, 9000 wrote:
:>
:>> 5. The software gives warnings about latches. I use latches for input
:>> registers ("if HOST_WR='0' then REG <= HOST_DATA"). Do I need to change
:>> them into clocked registers ("if HOST_WR'event and HOST_WR='1' then
:>> REG<=HOST_DATA")?
:>
:> Yes, but consider using the same clock for all of your registers.
:> Use the D and CE inputs for logic.
:
:I did this to most of the circuit including the state machines. But there is
:one place that this rule does not apply, that is when I use a slow host CPU
:bus to write to some configuration registers in the FPGA.
:
:Wait, maybe it applies. like this,
:process (HOST_WR)
:begin
:if HOST_WR'event and HOST_WR='1' then
: if HOST_CS = '0' then
: REG <= HOST_DATA;
: end if;
:end if;
:end process;
:
:I just want to know whether this is better than the following approach,
:HOST_CS_WR <= HOST_WR or HOST_CS;
:process (HOST_CS_WR)
:begin
:if HOST_CS_WR'event and HOST_CS_WR='1' than
: REG<= HOST_DATA;
:end if;
:end process;
:
:Is there a well-known best approach to this problem? It might look trivial
:to some but I am really confused. Now I have 10 such registers, then which
:approach is better? Thanks.
:
:vax, 9000
:
:>
:>> I see no advantage of clocked register here, since my
:>> target FPGA's cell has both async input pin and clock pin.
:>
:> I expect that you will someday.
:>
:> -- Mike Treseler
Article: 81186
Piotr Wyderski wrote:
<...>
> or even constants:
>
> generic const square{N} : type of N where {const N} is N*N;
> const nine : int is square{3};
(Didn't see anybody else mention this -- or I missed it)
In VHDL this would be a function, like
function square (integer N) returns integer;
declared in a package header and defined in a package body. Or is it
that you want to have a single function "square" for a bunch of
different types ? In VHDL presumably your types are different lengths
of SLVs or UNSIGNEDs : VHDL function arguments can be unconstrained
types, ie
function square (std_logic_vector N) returns std_logic_vector;
-- length only determined when function is called.
However be very careful handling increasing and decreasing ranges, I
learnt how to do this by studying some of the standard packages.
As an aside, I also like to use VHDL records, which for the few
unfamiliar readers here are like a C struct.
Regards,
-rajeev-
Article: 81187I would do (have done) it that way : Tcl script driving your PC's RS232 (OTOMH around 30 lines of code with a GUI), then use our free UART (or any other) in your Virtex (you need one wire and an RS232 level translator, but usually the -well designed- boards have this already. On Altera parts, we now often use the In-System Memory Contents Editor which updates Rams in real time through the JTag connector (no design, no utility to write, real handy). I don't remember if Xilinx has the equivalent of ISMCE. B.R. Bert Sea Squid wrote: > I made use of two 1K*10B single port RAMs generated with coregen > which is modified to contain my test vector, and P&R with that. However, > I have one thousand test vector files in plain text to send to the FPGA one > at a time. > > I am wondering about whether I can write a perl script to manipulate the > bitstream and generate an *incremental* bitstream so that I can avoid > running ISE for one thousand times? Where can I find such information? > > Thanks.Article: 81188
lecroy7200@chek.com wrote: > I have left the device in this state is anyone has ideas on further > test. You could measure Icc, to try and guage how much of the Clock tree is operational, and compare that with a device that is held in config-ready state ? Also see if some of the simplest pin-pin paths are still 'alive'. [ but, of course, be careful not to remove the power :) ] Your description thus far sounds like it is flipping back into part-way through a config cycle, but in such a way re-config cannot shake it loose. -jgArticle: 81189
lecroy7200@chek.com wrote: > After waiting an hour for Xilinx to return my phone call, I decided to > attempt further tests. From previous failures it seemed that the > supply had to be turned off for a long time in order to recover from > this failure. Using the dual FET test setup I started pulseing the > power to the FPGAs. Using a scope which was connected to the device, I > started out pulsing the power off for 10uS. I then tried to program > the device 5 times. The device was in the same state, so I increased > the off time and repeat the process. At 1ms (0.001 seconds) the part > would still not recover. Thinking that the device may have actually > been damaged I decided to try a much longer power cycle of about 5 > seconds and sure enough, the part came back to life. > > Of course, none of this helps me. It does confirm that there is an internal RC style Reset block, that has a recovery somewhere between 1ms and 5 sec. It could be usefull to narrow that Trec ( and also Vrec) down more. For example, I have seen devices that state "Vcc must reduce to less than 0.2V for POR to operate correctly" I have started another test where I > do not attempt to reprogram the devices. This will allow me to > determine the state of the control pins prior to attempting the reload. > > > I am starting to suspect that the devices internal oscillator has a > problem. There is very little information about it. There appears to > be no way to detect it's failure. Has anyone seen any detailed > information about how the oscillator was designed? Was the same design > used for all Xilinx devices? I am thinking to try and detect the > internal oscillator with a spectrum analyzer. good idea. -jgArticle: 81190
Hi, I would like some help from roketio users to find what is the maximum realizable freq we can get out of it. I hear that although it supports upto 3.125Ghz, you can only get only upto 2.5Ghz. Also, can I get any eval board which has charaterized the performance. Thanks much ThomasArticle: 81191
sk@glui.de wrote:
> Hi Mac, thanks for your thoughts.
My two bits for transient protection is a 3-element network on the left
hand side of Mac's schematic, ie transformer _in_between_ transient
protection
network and FPGA. All three elements Transient Voltage Suppressors
(basically a Zener diode or back-to-back Zener pair intended for this
application).
(+Wire) == TVS ==== TVS == (-Wire)
|
TVS(bidir)
|
Ground(Circuit Board or Chassis)
The element in the common leg needs to be bidirectional, I think the
other two can be either unidirectional or bidirectional. The top two
would be rated so the transformer secondary doesn't exceed the FPGA max
input, while the common
element is rated so that a common-mode spike doesn't spark across the
transformer.
> I got the idea for a PHY-less implementation from
> http://www.fpga4fun.com where they do it without even a transformer
but
> capacitive coupling and a few transistors....
> There's also an article at EDN where this is discussed, although
> they're hinting at using an X485 type of transceiver to buffer the
> signal. My idea was to save on this too.
X485= RS485? This buys you differential-to-single ended conversion,
tolerance to overvoltage condition, tolerance to wide variation in
differential signal amplitude. Newer devices provide slew-rate limited
drive.
> 10-base has a simpler link pulse scheme (NLP) which (afaik) allows
for
> simple differential signaling, whereas faster Ethernet uses FLPs that
Don't remember enough about Ethernet, is there a minimum rate of
guaranteed transitions ? Capacitive link _is_ simple and cheap, and
I've seen it used in commercial high-speed networks (eg StarFabric).
> might differ here. I'll read up on this.
> Also thanks much for the ASCII art - it's been working fine without
the
> two 10k, but I'll give it a try.
> As to the reason why - well, a chip saved is a chip saved....
Sounds like a good motivation to me. Still, RS485 might be the most
effective from parts cost and count. Remember, for a commercial board
in modest volumes, it costs 10 cents to put a part on a board, even a
resistor that costs 0.1 cent for the part. Nowadays you can get
capacitor arrays just like resistor arrays...
Regards,
-rajeev-
Article: 81192Jens Baumann wrote: > rgebru wrote: > > > Hi, > > > > I'm thinkin go of designing a heating/cooling system with VHDL and > > need to interface my Spartan 3 board to a real temp sensor. Does > > anyone have an idea of how I can do this? > > > > Thanks!! > > There are several temperature sensors with i2c interface. They should easily > be connected to your board. > > http://www.google.de/search?hl=en&q=i2c+temperature+sensor > > Jens My personal preference is SPI device, eg Analog Devices AD7814. Regards, -rajeev-Article: 81193
jjlindula@hotmail.com wrote: > Hello, I've been hearing a lot about DSP Builder and was curious if it > is worth learning? Where have you been hearing about it ? > Can anyone share their experience pros/cons? Are I did one commercial design with DSP Builder about a year ago. I can conceive that for a suitable complex design DSPBuilder would permit realization considerably faster than doing the design directly in VHDL. But I found it to be buggy and limited in _many_ different ways, and the overhead of finding, understanding and working around DSPBuilder's limitations was a HUGE burden that I would not wish on anyone. The second design will go much more smoothly than the first -- if you should live so long. I did finish my project, however it is maintained in VHDL; the Simulink model is not close enough to the final implementation to be worth keeping around, except for the approximate graphical view of the design. Perhaps there have been substantial improvements in recent releases. Perhaps learning Xilinx' SystemGenerator is a better bet. > they any good references I could pick and teach myself? > > Thanks, > joe Regards, -rajeev-Article: 81194
news.verizon.net wrote: > Hi, > I would like some help from roketio users to find what is the maximum > realizable freq we can get out of it. I hear that although it supports upto > 3.125Ghz, you can only get only upto 2.5Ghz. Also, can I get any eval board > which has charaterized the performance. Thanks much > > Thomas > > The RocketIO MGTs in the Virtex-II Pro family have a bandwidth up to 3.125 Gbps (not GHz) using the -6 and -7 speed grades and flipchip (FF) packages. The slower -5 speed grade is rated for 2.000 Gbps and the wirebond (FG) packages are rated for 2.50 Gbps. Our Virtex-II Pro X and Virtex-4 families have higher bandwidth RocketIO MGTs and can operate above 10 Gbps. You can purchase the board (HW-V2P-ML321) that is used for RocketIO characterization through any Xilinx distributor or through our online store at http://www.xilinx.com/ml321/ in addition to the ML321 with a XC2VP7-FF672-6C device we also sell the HW-V2P-ML323 with a XC2VP50-FF1152-6C device and the HW-V2P-ML325 with a XC2VP70-FF1704-6C device, both of which can also be found in our online store. EdArticle: 81195
Paul Leventis wrote:
> On a performance front, you will find that Cyclone and Cyclone II have
> a significant performance advantage over Spartan-3. We're talking
> 50-60% (core performance on 100+ designs, comparing fastest speed grade
> to fastest speed grade using best-possible software settings).
BTW, the Cyclone manual says that the highest speed of
an M4K RAM bank is 200MHz, but Quartus estimates it to
about 250MHz (Cyclone 1C6, speed grade 6). So, which
information is right?
Best regards
Piotr Wyderski
Article: 81196David R Brooks wrote: > Never, never, gate your clock. Ie, always use > > process (HOST_WR) > begin > if HOST_WR'event and HOST_WR='1' then > if HOST_CS = '0' then > Thanks. I have changed the design to follow this rule. vax, 9000 > rather than > > HOST_CS_WR <= HOST_WR or HOST_CS; > process (HOST_CS_WR) > begin > if HOST_CS_WR'event and HOST_CS_WR='1' then > > In many FPGAs, you simply aren't allowed to, as local logic cannot be > routed to clock inputs. Even if you can, you add delay twice: once for > the OR gate itself, and again for the wiring from the OR gate to the > FF's clock input, which will have to be local logic wiring, not a > dedicated clock net. This is to invite clock-skew problems (which, be > it said, are independent of the clock frequency: skew can hit you with > a 1kHz clock).Article: 81197
Group, Well, I need to choose between XC3S50 and EPM1270. Both have pros and cons. I list them below, and I'd like to ask you to point out other important issues, and which would you choose if you were me. My circuit occupies around 50% of XC3S50 or EPM1270. I might need several tens of the chips finally, But at this point I just need 1-3 for the prototype. I am aming at TQ144 package. It needs to interface 5V TTL logic. I plan to use 3.3V LVT244/245 to shift the voltage for inputs. I didn't check 5V/2.5V voltage shifters. My circuit is slow, working with 20MHz clock. XC3S50 pros: * Pin compatible SC3S200 available for possible growth * Cheap ($12+ for XC3S50, $15+ for XC3S200 at XILINX online store) * RAM on chip. Good if I want to add a small FIFO in the future cons: * Don't know where to buy XCF01S configuration flash. cost? * Needs both 2.5V and 3.3V power supply to interface 3.3V logic EPM1270 pros: * On chip configuration flash * On chip user flash, if I want to store some bits in the future * Need only single 3.3V power supply to interface 3.3V logic cons: * expensive (EPM1270C5ES $25+ at digikey). May cost more for none-ES? (for example, EPM1270C3 costs $73) * No TQ144 pin compatible bigger chips cheers, vax, 9000Article: 81198
On 18 Mar 2005 14:35:47 -0800, sk@glui.de wrote: >Hi Mac, thanks for your thoughts. >I got the idea for a PHY-less implementation from >http://www.fpga4fun.com where they do it without even a transformer but >capacitive coupling and a few transistors.... >There's also an article at EDN where this is discussed, although >they're hinting at using an X485 type of transceiver to buffer the >signal. My idea was to save on this too. >10-base has a simpler link pulse scheme (NLP) which (afaik) allows for >simple differential signaling, whereas faster Ethernet uses FLPs that >might differ here. I'll read up on this. >Also thanks much for the ASCII art - it's been working fine without the >two 10k, but I'll give it a try. >As to the reason why - well, a chip saved is a chip saved.... Link pulses have nothing to do with actual data transmission. In both 10bt and 100btx individual link pulses are the same, only for FLPs they are spaced more closely. In 10bt link pulses are used to keep the link alive when there is no actual data packet transmission. For 100btx, FLPs are used in auto-negotation to decide which type of phy would be used as most 100btx phys also have a 10bt portion and can be connected to a 10bt or 100btx phy. Normal data transmission in 10bt is done with a manchester coded signalling scheme which can be recovered with a straight comparator or hacked up with a differential receiver as it's a two level signal with no appreciable ISI. In 100btx, the situation is quite different. It's a 3 level signal and there is considerable ISI so one needs a decent equalizer to recover the bits. Of course clock recovery and base-line wander are other issues to deal with.Article: 81199
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: > Our Virtex-II Pro X and Virtex-4 families have higher bandwidth > RocketIO MGTs and can operate above 10 Gbps. > Virtex 4 can do up to 11.1Gb/s to be exact. -- Wing Wong.
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