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Peter, I was thinking about this scheme: - DSP grabs 25MHz clock from crystal and generates its 600MHz; - FPGA grabs that same 25MHz directly from the crystal too and generates the clock that better suits the code, maybe 50MHz; - then the FPGA, or the DSP (this has not yet been decided), will put the serial clock in between the 2 at 25MHz or 50MHz; - this way they should have a syncronized internal clock (I mean when the signal rises on the FPGA, it also rises on the DSP, the latter having much more rises during an FPGA's period due to the higher frequency it works with). Do you suggest me to: 1) send the serial clock out from the FPGA to the DSP or 2) send the serial clock out from the DSP to the FPGA and use this clock also to let the VHDL program running? The FPGA has to count from some encoders and the, when asked from the DSP, it has to send the quotes, so the FPGA keeps on working even out from the communication (that's why the serial clock would in either the 2 cases be continous). If I've not been that clear, please let me know what I missed. Thanks, MarcoArticle: 98376
i saw it its not of much help..as we are doing it based on subpipelining concepts and composite field arithmetic if you find something of such sort please do help us thanks in advanceArticle: 98377
Page 7-74 of PCI IP 4.1.0 user-guide: "The following events ca cause a PCI interrupt - Avalon asserts the IRQ signal - Avalon writes to one of the mailbox registers - An error condition is detected" "The Avalon IRQ input causes a bit to be set in the PCI interrupt status register. When you need to assert a PCI interrupt, this bit can be enabled." That's why I wonder, that the interrupt does not work. MartinArticle: 98378
The problem is that the 16R4 isn't HDL-friendly; use a 16V8 instead. (Do they even sell 16R4's anymore?) Re-coding it like this might work: Y <= '0' when not (a='1' and b='1' and c='1') else '1'; If that doesn't work, try: Y <= '0' when (a = '0') or (b = '0') or (c = '0') else '1';Article: 98379
Dear all
i write a simple test for led on altera cyclone board by jtag
protocol
such as following: led[0] will shine with some frequence
reg [31:0] temp_count=0;
reg direction=1;
parameter delay=23'h600000;
always @( posedge clock)begin
if(direction==1)begin
temp_count=temp_count+1'b1;
LED[0]=1;
if(temp_count>=delay) begin
direction=0;
end
end
if(direction==0) begin
temp_count=temp_count-1'b1;
LED[0]=0;
if(!(temp_count>0)) begin
direction=1;
end
end
end
it did work after "few minutes"
why it took "few minutes" to perform well, after i bured code into
fpga completely
thanks for reply
Sincerely Chronoer
Article: 98380Hallo, I have a Virtex-4FX, and I have a design made with edk 7.1i. I have opened it into edk 8.1i and the applet asks me to upgrade it. During upgrade process the applet asks if I want upgrade powerpc wrapper from 1.00.a to 1.01.a If I do it the system downloaded into fpga doesn't work. Instead I don't upgrade, the system works well. Has anyone had the same trouble? In which way can be solved? Many Thanks in Advance Marco ToschiArticle: 98381
chronoer wrote: > Dear all > i write a simple test for led on altera cyclone board by jtag > protocol > > such as following: led[0] will shine with some frequence > > reg [31:0] temp_count=0; > reg direction=1; > > parameter delay=23'h600000; > always @( posedge clock)begin > if(direction==1)begin > temp_count=temp_count+1'b1; > LED[0]=1; > if(temp_count>=delay) begin > direction=0; > end > end > if(direction==0) begin > temp_count=temp_count-1'b1; > LED[0]=0; > if(!(temp_count>0)) begin > direction=1; > end > end > end > it did work after "few minutes" > why it took "few minutes" to perform well, after i bured code into > fpga completely > thanks for reply > > Sincerely Chronoer Most likely your synthesis tool ignores the 'reg direction = 1' initialization, and initializes it at zero instead. This results in down count from 0 to delay. which takes ~4 billion clock cycles. Completely unrelated, but you should also use '<=' instead of '='Article: 98382
Austin Lesea wrote: > John, > > Interesting opinions. > snipping > > How much circuit design for FPGAs is done outside the US? Outside > silicon valley? How much software for CAD tool support of FPGAs is done > elsewhere? Where are the patents being filed? > I notice on the job listings for Xilinx that most all of the good stuff is in the US CA,CO etc, but on that other companies website, they seemed to have half their VLSI design reqs in Malaysia last time I looked, perhaps cost cutting or something. John JaksonArticle: 98383
JJ wrote: > > I notice on the job listings for Xilinx that most all of the good stuff > is in the US CA,CO etc, but on that other companies website, they > seemed to have half their VLSI design reqs in Malaysia last time I > looked, perhaps cost cutting or something. > > John Jakson > Xilinx have a circuit design group in Ireland also. AlanArticle: 98384
On Tue, 07 Mar 2006 11:15:33 -0800, Austin Lesea <austin@xilinx.com> wrote: >http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385 > >Well, I guess that about wraps it up for the attempt to disguise ASIC >design as something different... Pity; I'm doing a RapidChip at the moment. I guess they got their business model wrong, but there are still half-a-dozen other people in the market, and I'd be surprised if we don't see more. On the RapidChip, it was (then) a no-brainer: 110nm, (much) bigger than any 'real' FPGA, much better performance, good unit price, and the total NRE+tools cost was equivalent to the cost of about 50 or 60 of the same-size (but slower) FPGA equivalent that I was quoted for. I don't know about the others, but LSI wasn't disguising this as anything other than ASIC design. ASIC design is not actually that different from (good) FPGA design. Evan -- Riverside emlat riverside-machinesdotcodotukArticle: 98385
Hi I would like to design a DDR controller for a Spartan 3. I have tried using MIG 1.5 but without much success. It claims to work with all Spartan 3 devices, yet I have found it to be unreliable and not generate designs with all Spartan 3 devices. Can I ask how others go about with DDR. Do you design your own cores, buy a 3rd part core or use Xilin cores? Thanks JonArticle: 98386
this time i add some codes: initial begin direction<=1'b1; temp_count<=0; end it can't solve this problem either and i found the led[0] has a low level lightness continuously not normal it also took "few minutes" to shine the led could you give some better codes? thanks a lotArticle: 98387
hi everyone we know in the virtex-4 there haven't the bus macro so anyone know if we need the inter-connection between two block how we can do that ???? xunArticle: 98388
hm, at DATE yesterday a university guy who is doing partial reconfig with v2pro claimed that xilinx will come out with v4 partial reconfig solution in one week time, dont know more, but maybe xilinx is really having some new things for v4 reconfigArticle: 98389
chronoer wrote: > initial begin > direction<=1'b1; > temp_count<=0; > end initial blocks are also ignored for synthesis. You can either refer to your synthesis tool manual to see how to initialize registers, or you can add a 'reset' input signal and add some logic to reset registers whenever the reset is asserted. The first option only works once during configuration, the second one will work whenever the reset is asserted. In addition, you could also reduce the counter size to use the same number of bits as your delay. This doesn't fix the problem, but will provide a quicker recovery in case things ever go wrong.Article: 98390
regards: since xilinx ise 8.1i support linux red hat 4.0 (with device Spartan-3 400k) After I install xilinx ise 8.1 under linux red hat 4.0,I cannot find a icon to start the software "xilinx ise 8.1i".Someone say that I might start xilinx ise 8.1i at linux red hat 4.0 command mode.Is this saying right? and how can I achieve that "start xilinx ise 8.1i at linux red hat 4.0" any positive suggestions is welcome. thank you best regards to you allArticle: 98391
Hi John,
"johnp" <johnp3+nospam@probo.com> wrote in message
news:1141838218.969036.272100@i39g2000cwa.googlegroups.com...
> I've been bitten several times by XST producing sub-optimal results by
> trying to use the flip-flop enable when it doesn't need to.
> For example:
>
> always @(posedge Clk10 or posedge reset)
> if (reset)
> timeout_intr_reg <= #1 1'b0;
> else if (lc_intr_reg_wr)
> timeout_intr_reg <= #1 db_wr_data_r2[6];
> else if (intr_db_timeout)
> timeout_intr_reg <= #1 1'b1;
>
> ...
> Can XST be made to recognize cases like this? Just because you have an
> enable pin on the flip-flops doesn't mean you have to use it!
> Anyone else seeing this?
Yes, XST gets this "wrong" sometimes (more often than not, I'd say, when
you're designing for a reasonably high speed). It does the same thing with
synchronous sets and resets, too.
You might find the synthesis constraints "use_clock_enable",
"use_sync_reset" and "use_sync_set" to be useful. In your case, the
invocation would be (I think):
// synthesis attribute use_clock_enable of timeout_instr_reg is no;
That should allow you to keep your nice readable RTL description intact, but
not suffer timing problems. (I'm not saying this is ideal, but anything that
solves your problem, right? :-)).
Cheers,
-Ben-
Article: 98392counter is indeed too large after i reduced the counter it worked as i thought thank you very muchArticle: 98393
"Eric" <dasani8888@hotmail.com> wrote in message
news:1141848324.248239.122130@v46g2000cwv.googlegroups.com...
> Hi,
> I'm trying to debug an application.
> I downloaded the .elf file to the board, and then started XMD.
How is the machine on which you started XMD connected to the target? Is it
via JTAG?
Did you then type "connect ppc hw" to attach to the processor before
starting the debugger?
Cheers,
-Ben-
Article: 98394manjunath.rg@gmail.com wrote: > i saw it > its not of much help..as we are doing it based on subpipelining > concepts and composite field arithmetic if you find something of such > sort please do help us do you have a C based implemention somewhere as an example?Article: 98395
I've made a implementation of the aes core in fpga which work with pipelining - i.e. only 4 sboxes that I use and itterate each 5 times for every round. I cannot give you the code/spec due to IP issues... the design nature depeneds on what is the speed (i.e. clk cycles) you need for each round and how much memories you can spare (dpbram = 2 sboxes). Hope it helps, Mordehay.Article: 98396
Hi, For the editing menus you can install the Smeg menu editor. Cheers mikelinyoho wrote: > regards: > > since xilinx ise 8.1i support linux red hat 4.0 (with device Spartan-3 > 400k) > After I install xilinx ise 8.1 under linux red hat 4.0,I cannot find a > icon > to start the software "xilinx ise 8.1i".Someone say that I might start > xilinx ise 8.1i at linux red hat 4.0 command mode.Is this saying right? > and how can I achieve that "start xilinx ise 8.1i at linux red hat 4.0" > > any positive suggestions is welcome. > > thank you > best regards to you allArticle: 98397
Hi,
I have a design with two identical 16 taps filters runing in parallel on the
same inputs.
A switch allow to disable one of the two filters.
I also have two test bench runing on the same inputs :
- one has the two filters enabled.
- one has only one filter enabled.
I used post-synthesis files (.vho) to simulate the two test bench and record
all signals into .vcd files (values changed dump files)
I use these .vcd files to perform Power consumption estimation for the two
test bench.
In the case where only one filter is running, I only have 45% of the nodes
toggled during simulation.
In the case where the two filters are running, I get 85% of the nodes
toggled during simulation.
In the first case, the powerplay power analyser inidcates a low power
estimation confidence.
In the second case, the powerplay power analyser indicates a medium power
estimation confidence.
Can I consider the power estimation confidence in the first case medium as
in the second case, knowing that if the estimation is low, it's just because
I have intentionally not used half (1 filter out of 2) of the design ?
Article: 98398Hi all, The Sydney-X2 FPGA development system for education and FPGA computer application development has now been released. http://www.burched.biz/sydneyx1.html Are you interested in developing FPGA applications with your own on-chip CPU or multiple on-chip CPUs? The Sydney-X2 "FPGA computer" platform may be the system that you are looking for. Introductory sale with 15% off the normal price. Limited time. Order now using our secure online order form. International orders are very welcome. Best regards, Tony Burch http://www.burched.bizArticle: 98399
On 8 Mar 2006 10:31:12 -0800, laura_pretty05@yahoo.com.hk wrote: >I want to know which VHDL book is better for learning...?? A good starting point is Peter Ashenden's "VHDL Cookbook". You should be able to find it online for free download, using Google. His bigger book "Designer's Guide to VHDL" is very good too. - Brian
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z