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We have been doing a project on high speed aes using subpippelining concepts we would be happy if we find some code which may help us.. if anyone in this group has any access pls help usArticle: 98301
On 6 Mar 2006 21:24:29 -0800, sachink321@gmail.com wrote: >HI >how would i use internal signals in XPS for microblaze on spartan 3 >fpga board. > >let me explain my project >in opb_emc >im using 2 memory banks >so im having two Output enable signals >but i have only one external pin >so i need to AND these two output signals and produce a single output >this output will be given to the external signal. > >but i cant understand how can we produce a logic >for these internal signals? > >any ideaz There are two approaches; the util_reduced_logic core is one; for something slightly more complex you can create your own core for the XPS project and add it just like util_reduced_logic. This allows you to keep the entire project in XPS. But the other approach is to embed the XPS-generated system as a subsystem in an ISE top level project. The XPS tools will generate a "stub" design that simply brings every pin on your subsystem out through I/O buffers to FPGA pins on the top level design. You can then use this "stub" as a starting point for your own top level design. In this instance you would simply "and" the two signals from the subsystem and connect the result to a single output pin (deleting the unused one). For a single "and" gate this would not be simpler, but for a large amount of "traditional" logic (e.g. FFT, filters, etc) it is probably easier than creating XPS cores for everything you want to add... - BrianArticle: 98302
Scott M. Kroll wrote: > > It's very strange, but here's what I meant: I am using Digilent's JTAG > utility (it's called Export) to program the FPGA via JTAG. Using IMPACT > to create the .bit file, and then program the FPGA with the .bit. > Digilent's Export tool only supports .bit and .svf files. If I program > the FPGA via the .bit file, the SRAM never writes, and feeds back random > garbage, never writes correctly. OK, I'll try that tonight and see what I see. BTW, what versions of ISE and Export are you using ? > Some ramtesting vhdl I found for the Spartan-3 Starter doesn't work, > nor does anything I've written. Follow the bouncing links for my S3 kit SRAM test code and notes: http://groups.google.com/group/comp.arch.fpga/msg/ee222450bf8e47c8 If I ever find time to debug the S3 -ES DCM oddities I've been seeing, I'll post a new version of that code that runs the S3 starter kit SRAM (pipelined) at around 60 MHz. BrianArticle: 98303
bjzhangwn wrote: > Hi,I now use the pio mode 0 to wrrite the registers in the device ,but > the device seem not to recceive the data ,becase I read the data from > the register just what I write to .And I think if I set the dmack > =E3=80=81ata address and the cs signals crrectly, the device shall respo= nse > to it when I write to the device Make sure you really set them correctly; I find the spec to be very hard to read with respect to their polarity - I eventually got it to work, but several things were not as I first assumed/tried. Try searching on IDE or ATA and the names of various embedded processors - 8051, pic, etc and you will find code various hobbysists have used, which can help to understand how to get basic communication working.Article: 98304
Does anybody know where I can get hold of a cheap Xilinx development board that has an FPGA with 5v I/O?Article: 98305
fpga_toys@yahoo.com wrote: > In fact, the most obvious thing missed in Austins post, is that he is > openly mocking the very potential clients that Xilinx needs for it's > high end market .... smaller ASIC designers wishing to move down to > FPGAs to balance NRE and production run costs. That is not going to win > Xilinx those customers. I wonder if any of the ASIC designers would design a home grown FPGA with customer specific cores to provide a multiplatform programmable reusable part for high volume to avoid Xilinx? Given they are starting with an ASIC budget and ASIC tallent, do they even need Xilinx for reusable/retargetable FPGA like parts?Article: 98306
Jim, I don't understand what you means. what is Font Rom code? Laura Symon =E5=AF=AB=E9=81=93=EF=BC=9A > "Jim Granville" <no.spam@designtools.co.nz> wrote in message > news:440df96b$1@clear.net.nz... > > > > I think the answer is to re-write the FONT ROM code, so it only displa= ys > > 0..9 - This would even pass a cursory test. ;) > > - and it appears to fully meet the wording of the spec... > > -jg > > > Jim, > Of course! That's an excellent solution. Yet another example of why it's > unnecessary to gate clocks. :-) > cheers mate, Syms.Article: 98307
Scott M. Kroll wrote: > It's very strange, but here's what I meant: I am using Digilent's JTAG > utility (it's called Export) to program the FPGA via JTAG. Using IMPACT > to create the .bit file, and then program the FPGA with the .bit. > Digilent's Export tool only supports .bit and .svf files. If I program > the FPGA via the .bit file, the SRAM never writes, and feeds back random > garbage, never writes correctly. Okay, let me see if I understand this correctly - the digilent programmer does not seem to be able to make a .bit file work, but if you use the xilinx tool to turn .bit into .svf, the digilent programmer can load that. Your only evidence of working/not working to date is the ram test. But it's probably that the programming more generally fails? Anyway, my impression is that a .bit file is just data, while a .svf file is data expanded into explicit instructions for how to wiggle the jtag lines to program it into a xilinx part - all the thinking is already done, only the execution remains. This suggests that your problem is that the digilent programmer is not using (is not configured to use) the right programming algorithm for the part in question. When it's mindlessly executing the .svf instructions things work, when it's taking responsibility for figuring out how to program a .bit, it fails. You could either take that up with digilent, or if you want to streamline your intermediate step, the xilinx tools can be run command-line style from scripts to do your translation.Article: 98308
Take a look at the following cores, they might help you.. http://www.opencores.org/browse.cgi/filter/category_crypto Mordehay.Article: 98309
Peter Alfke wrote: > Please, don't throw any more of your venom at this newsgroup. > You have stopped being entertaining or informative, a long time ago. > Peter Alfke, from home. I couldn't agree more. The soaring ego combined with the chip on the shoulder is really getting tiresome. Reminds me of the level of discourse on sci.electronics. What a shame. -JeffArticle: 98310
Thanks,the specification I have read many times,the fpga I used is stratix 2,and the signals (dmack,ata addr,diow,dior) sampled by the logic analyzer inside the fpga are crrectly.Article: 98311
bjzhangwn schrieb: > the fpga I used is stratix 2 I don't think this FPGA can handle 5V ... I assume you use a level shifter outside the fpga? does the direction switching of the data lines work? are the voltage levels ok? bye, MichaelArticle: 98312
Now, I used the state machine to apply to VHDL. In my case, there are two states, S0 and S1. When I press a button, S0 is transit to S1 such that the LED display some of the segments,like segment a,b,c. And press this button again, S1 is back to S0. How can I present in VHDL so that the LED display in segment a,b,c ? Thanks!!Article: 98313
I tried examining the V4 LVDS input IBIS models last night. Loading them into Edality's free IBIS viewer gave me the following warnings for the LVDS_25 buffer models (v2.2): >IBISCHK3 V3.2.8 > Checking virtex4.ibs for IBIS 3.2 Compatibility... > WARNING - Model LVDS_25: POWER Clamp : Typical value never becomes zero > WARNING - Model LVDS_25: POWER Clamp : Minimum value never becomes zero > WARNING - Model LVDS_25: POWER Clamp : Maximum value never becomes zero Examining the clamp tables, it appears the input buffers will be sourcing rail current, significantly hauling up the signal levels on an LVDS driver connected to them. Anyone else seen this? Is this correct, or are my IBIS reading skills too rusty? Also, the DIFF_TERM input is modeled with a IBIS series element as a simple resistor (+/-20%) across the input. Has anyone seen any documentation of (or measured) the input termination non-linearities away from 1.2V, other than the notes in Answer Record 13910, and the 2.5V VCCO supply requirements noted in Answer Records 17244 and 15633 ? thanks, BrianArticle: 98314
bjzhangwn wrote: > Thanks,the specification I have read many times,the fpga I used is > stratix 2,and the signals (dmack,ata addr,diow,dior) sampled by the > logic analyzer inside the fpga are crrectly. They match what you designed them to do, but that doesn't mean they are correct for the IDE interface.Article: 98315
Gary Pearman wrote: > Does anybody know where I can get hold of a cheap Xilinx development > board that has an FPGA with 5v I/O? To literally do that you'd probably have to find an old one, or one with level translators. One intended for a 5v PCI bus might have the level translators you need, just repurpose the PCI lines. For many purposes though, you may be able to use a spartan 3 kit ($100) with series resistors to protect the FPGA input protection diodes from overcurrent. The FPGA outputs should be valid 5v TTL levels (though not valid 5v CMOS), though perhaps not as high a noise margin as you want.Article: 98316
thomas.b36@gmail.com wrote: > Hello Aurash, > Thanks for you time. Well, by C i mean the complete pakage/knoledge of > C from A to Z at SW engineer, by functional C i mean some knowlege to > be able to programme CPU Knoledge for HW programming. > So, what's knowlegde should i have to be able to wrire device driver? > Thank you. > Thomas > Thomas, To write a device driver it's very OS dependent, but assuming you talking about linux, by reading the right books, and having a basic understanding of ANSI C language (and of course you need to know the behavior of your device) it's a matter of days (if not hours) but this can vary with your mileage. I would learn C from "A to Z" otherwise some else will show up and take your job. a good book for writing linux device drivers (you can read this one on line) http://www.oreilly.com/catalog/linuxdrive2/index.html Have fun, AurashArticle: 98317
On Wed, 08 Mar 2006 07:54:36 -0500, "Scott M. Kroll" <none@nowhere.com> wrote: >Brian Davis wrote: >> Scott M. Kroll wrote: >>> 2. The external SRAM does not work when using a .bit file >>> >> Could you clarify exactly what you mean here; are you >> using the Digilent JTAG utility to program the on-board prom, >> or to directly configure the FPGA via JTAG? >> >> One thing I've seen with IMPACT generated SVF files on both >> V2P's and the S3 starter kit, is the need for one last JTAG >> operation to "wake up" the part. >> >> IIRC, in the Digilent tool, after loading the FPGA with the >> config PROM in BYPASS, just try a device id on the config >> PROM and see if that fixes it. >> >> Also, I think I've had to change the JP1 bitstream readback >> jumper setting to "disable" to get consistent results for JTAG >> download; you may also want to change the configuration mode >> jumpers to "JTAG" >> >> If the DCM doesn't start up after re-configuration, your static >> logic would work but any DCM clocked logic would not: >> Answer Record 11778: >> "Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures >> correctly after PROG is pulsed, but DLL/DCM/DCI does >> not function correctly when reconfigured" >> >> Similar things can happen if the part almost, but not quite, finishes >> configuration and ends up in a configured state with GSR or GTS >> still asserted. >> >> To help sort out what is happening, create a test design with: >> - an LED driven from a switch input (no registers) >> - a blinky LED counter driven from the input clock WITHOUT a DCM >> - a blinky LED counter driven from a DCM sourced clock >> - LED's on DCM LOCKED and "clock stopped" status bit >> >> Brian >> > >It's very strange, but here's what I meant: I am using Digilent's JTAG >utility (it's called Export) to program the FPGA via JTAG. Using IMPACT >to create the .bit file, and then program the FPGA with the .bit. >Digilent's Export tool only supports .bit and .svf files. If I program >the FPGA via the .bit file, the SRAM never writes, and feeds back random >garbage, never writes correctly. Some ramtesting vhdl I found for the >Spartan-3 Starter doesn't work, nor does anything I've written. It >constantly reads back garbage data. When I go into IMPACT, and generate >a SVF of the chip programming (with the same .bit file, no less), and >then load that into Digilent's tool, the SRAM works correctly (reads >back fine, the ram tester comes out ok). > >I know it seems bizarre, but it's what happens. A quick "reality check" on programming problems is to program the file into the flash. If it behaves differently then it's definitely a download problemArticle: 98318
Hello, I would like to implement a can bus protocol on a fpga, in a way to link a pc and a can bus via a pci fpga I/O card. Does anyone has a vhdl core to do that? Thank you AdrienArticle: 98319
$PRINTER environment variable must be non empty. antonio bergnoli ha scritto: > Can you print schematics in ise 8.1 (linux Red Hat)? if i try , ise says > that default printer is not selected and fails. Any ideas? > > Aurelian Lazarut ha scritto: > >> I'm using RedHat Enterprise Linux WS 4 >> so the answer is Yes >> Aurash >> >> mikelinyoho wrote: >> >>> regards: >>> >>> Does xilinx ise 8.1 support linux red hat 4.0 ?????? (with device >>> Spartan-3 400k) >>> thank you >>> best regards to you all >>>Article: 98320
feedcaseg wrote: > I'm looking about methods for controlling these kind of motors, my > motor is with the specifications: > > P = 400W > Poles = 4 > V = 220V > rpm max = 3520 rpm > I = 3.7A > I need help about how to controlling the current and voltaje that not > affect the FPGA, what part of the project i can do with the FPGA, i > have an Xilinx Spartan 3 Board s200, thanks. > Your motor is irrelevant for the FPGA side, the motor will be driven by some "IGBT bricks", what you can do in the FPGA is the PWM (pulse with modulation) to control the frequency of your 3 phase synthesized sinus waves, and many more control loops, over drive protection, speed control, position control, thermal protection, and many other nice things. Most of the microcontrollers these days can perform these things for ~4 USD, but nobody can stop you to design the motor controller using a spartan3. AurashArticle: 98321
Kim, I am just trying to offset the lack of critical thinking regarding ASICs. If my style offends, I apologize. It is extremely difficult to make an IC. We know. How many mask sets does it take to get it perfect? Can anyone afford to make anything perfect? With an ASIC do you just give up, and take what you get (when your budget runs out, or you run out of money or time). At least with a general purpose product like an FPGA we have millions of sockets filled with our parts to help finance the process. And, we have a future guarantee of customers who are just waiting to take advantage of the next generation of technology. As for use of only generic features, if you wish to pay for the FPGA, and not use it, that is your decision. If it were me, I would use everything possible in the part to my advantage, and to the advantage of my company. Austin Kim Enkovaara wrote: > Austin Lesea wrote: > >> Is it really that desparate? No one to talk to when you design an >> ASIC anymore? > > > Design questions about ASIC are usually almost the same as with FPGA. > FPGA is not some magic platform that fixes all the bugs. Some of designs > I do are on both FPGA and ASIC, and both platforms have own problems and > common problems. > >> I don't mind the off topic question. It is instructive as it >> demonstrates just how hard it is to make an ASIC that actually works. > > > Just as hard as with FPGA. Yes you can use some special features in one > FPGA vendor and maybe one family (for example FIFO16s in Virtex4) but that > makes you very dependent to that platform. It is much wiser to use generic > structures that can be targeted to multiple FPGA architectures and vendors. > It much easier to negotiate price when even the vendor can be chosen at > a very late stage. Of course if the real estate is very tight FIFO16 etc. > can be a useful size optimisation. If they fit to the application, usually > in communication equipment the fifos are shared among many ports, and > the divisioning can be configured on the fly, that is not easily done > with FIFO16 for example. > >> And it gives all of the FPGA users a good feeling that they made the >> right decision, and did not even try to make an ASIC. Who needs those >> headaches. > > > There are headaches with FPGA also. FPGA fabric is slower compared to > ASIC and trying to squeeze something to fit and to fullfill timing > in a FPGA can be a very time consuming task. > > As a big user of asics and fpgas, I think your style is little offensive > about asics. In your opinion asics are worst thing ever and fpgas > are the best thing since sliced bread. Fortunately our local FAEs are > not so > aggressive :) > > --KimArticle: 98322
mungam wrote: > Hello, > I would like to implement a can bus protocol on a fpga, in a way to > link a pc and a can bus via a pci fpga I/O card. > Does anyone has a vhdl core to do that? > Thank you > > Adrien > Have you used Google to look for one? There's a CAN block on Opencores (http://www.opencores.org). Also a PCI bridge. AlanArticle: 98323
Kim Enkovaara wrote:
> Just as hard as with FPGA. Yes you can use some special features in one
> FPGA vendor and maybe one family (for example FIFO16s in Virtex4) but that
> makes you very dependent to that platform. It is much wiser to use generic
> structures that can be targeted to multiple FPGA architectures and vendors.
> It much easier to negotiate price when even the vendor can be chosen at
> a very late stage.
This is a fact.
It's ok to be a little boring and "waste" a few gates.
Take off the handcuffs and you will pay less for large FPGAs.
-- Mike Treseler
Article: 98324I have seen that site but the link is broken, only the sources in verilog are available. Could you check for me if you caa get the vhdl cores with your PC, maybe I can't because of my computer. thank you
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