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Ok, so you're working with a DSP too, which one? I'm using a Blackfin with a Spartan3. MarcoArticle: 98276
Hi, for my project I'd like to use the same 25MHz clock signal (coming from an external oscillator) for both the DSP and my Spartan3. A pll inside the DSP creates the 600MHz clock from the 25MHz. I still don't know how fast I'll let the FPGA work, so I was supposed to acquire the 25MHz clock and through a DCM bring it to the level, i.e. 50MHz or 60Mhz, that optimizes my design. In such a way I would have the same clock for both my devices, syncronized and each with its proper frequency. Can I do that or should I avoid this way of working? Is it a common way to work? Suggestions? Thanks, MarcoArticle: 98277
Austin Lesea wrote: > Is it really that desparate? No one to talk to when you design an ASIC > anymore? Design questions about ASIC are usually almost the same as with FPGA. FPGA is not some magic platform that fixes all the bugs. Some of designs I do are on both FPGA and ASIC, and both platforms have own problems and common problems. > I don't mind the off topic question. It is instructive as it > demonstrates just how hard it is to make an ASIC that actually works. Just as hard as with FPGA. Yes you can use some special features in one FPGA vendor and maybe one family (for example FIFO16s in Virtex4) but that makes you very dependent to that platform. It is much wiser to use generic structures that can be targeted to multiple FPGA architectures and vendors. It much easier to negotiate price when even the vendor can be chosen at a very late stage. Of course if the real estate is very tight FIFO16 etc. can be a useful size optimisation. If they fit to the application, usually in communication equipment the fifos are shared among many ports, and the divisioning can be configured on the fly, that is not easily done with FIFO16 for example. > And it gives all of the FPGA users a good feeling that they made the > right decision, and did not even try to make an ASIC. Who needs those > headaches. There are headaches with FPGA also. FPGA fabric is slower compared to ASIC and trying to squeeze something to fit and to fullfill timing in a FPGA can be a very time consuming task. As a big user of asics and fpgas, I think your style is little offensive about asics. In your opinion asics are worst thing ever and fpgas are the best thing since sliced bread. Fortunately our local FAEs are not so aggressive :) --KimArticle: 98278
Peter Alfke wrote: > fpga_toys@yahoo.com wrote: > > Different than the ASIC's that a number of fabless vendors produce that > > we call FPGA's? The business case for in-house fab, or fabless, has > > been a difficult call for the last two decades, and all I see from this > > announcement is that AMD reached the point where investing in 45nm fabs > > wasn't in the cards with their current volumes. When you shed your fab, > > with it goes your ASIC business. > > Mr Anonymous, who hides his name, but doesn't want to be called "toys": > Why do you bring up AMD, which was not at all mentioned in the press > release. > Just to stir the pot and create additional controversy? Because, they were one of the most vocal camps against fabless technology a few years back. That we now have LSI going fabless is a material part of the discussion. > There is understandable glee in the FPGA camp when one of the most > ardent proponents of "Structured ASICs" (the "FPGA-killer technology") > finally, after many unsuccessful money-losing years, throws in the > towel. Basta, finito, kaput. > So it is now clear again, as it has always been: > There are ASICs (with their well-known technical advantages and > economically-based disadvantages) and there are FPGAs (not as big, not > as fast, and not as frugal, but increasingly popular for reasonable > designs in reasonble volume, and far less risky). > Both camps will survive, but the trend is in favor of FPGAs. I agree both will survive to some extent for a very long time. Till at least until the next technology comes along and replaces FPGA's as the small ASIC step child, as FPGA's did PLDs in the last decade. The the title the Austin puts forth, and the one liner in the body is laced with sarcastic riddicule of the ASIC camp with the assumed thought that somehow Xilinx has killed ASIC's. The fairy land here, is that Xilinx has grown to be a pretty large step child to the ASIC industry, and still growing - but that is hardly making Xilinx a giant slayer. In fact, the most obvious thing missed in Austins post, is that he is openly mocking the very potential clients that Xilinx needs for it's high end market .... smaller ASIC designers wishing to move down to FPGAs to balance NRE and production run costs. That is not going to win Xilinx those customers. > Please, don't throw any more of your venom at this newsgroup. > You have stopped being entertaining or informative, a long time ago. > Peter Alfke, from home. The venom is on your and Austin's part. Like where in the hell do you get off on asking someone to leave CAF because they disagree with you? I say take a flying hike yourself .... and as another reader commented to this thread via email earlier .... that is "Mr. Toys to you". Controversy, disagreement, debate, even when very passionate, NEVER EVER justify your and Austins directly personal attacks in this forum. Since you continue to press Tin-Aus's slur in your own way, let's adopt "Peter Principle" for you, if you want to continue making discussions in this forum personal. Otherwise, stop being childish, get over the handle I use, and stick to the facts with informed debate (however lively that gets) as address your position responsibly and professionally. I'm hardly the only person using a handle in this forum ... and you have no right in hell to riddicule anyone that does.Article: 98279
fpga_toys@yahoo.com wrote: > Peter Alfke wrote: > > Mr Anonymous, who hides his name, but doesn't want to be called "toys": > I say take a flying hike yourself .... and as another reader commented > to this thread via email earlier .... that is "Mr. Toys to you". hmm ... I got that slightly wrong ... the other readers humor was: <fpga_toys@yahoo.com> wrote: >austin wrote: > > toys, I was expecting your reply to be "That's _Mister_ Toys to you."Article: 98280
regards: Does xilinx ise 8.1 support linux red hat 4.0 ?????? (with device Spartan-3 400k) thank you best regards to you allArticle: 98281
> I need help about controlling the speed of an ac trifasic motor, thanks the speed goes linear with the frequency of your 3-phase inputs to the mortor - just change the frequency? or maybe have a look at http://www.catb.org/~esr/faqs/smart-questions.html bye, MichaelArticle: 98282
On 8 Mar 2006 00:32:52 -0800, "Marco" <marco@marylon.com> wrote: >for my project I'd like to use the same 25MHz clock signal (coming from >an external oscillator) for both the DSP and my Spartan3. A pll inside >the DSP creates the 600MHz clock from the 25MHz. I still don't know how >fast I'll let the FPGA work, so I was supposed to acquire the 25MHz >clock and through a DCM bring it to the level, i.e. 50MHz or 60Mhz, >that optimizes my design. In such a way I would have the same clock for >both my devices, syncronized and each with its proper frequency. >Can I do that or should I avoid this way of working? >Is it a common way to work? >Suggestions? I donīt know the exact way the DSP creates the 600 MHz, but my best suggestion would be to use the DCM to go up from 25MHz to 50 or 60 MHz (whichever fits you best), and then output this signal to the DSP, so that it derives its internal clock from the one generated by the FPGA. You may even need to feedback the clock to the FPGA. Thus way, you may have a better control of the phase between both devices, and the inter-clock jitter will be limited to that coming from the DSP, the other way you might get more jitter as both the devices would put their own contribution. Maybe there are better solutions, but you must first analyse the synthesiser and DCM parameters, and how they will fit together. Regards, ZaraArticle: 98283
On Wed, 08 Mar 2006 10:26:20 +0100, Zara <yozara@terra.es> wrote: >On 8 Mar 2006 00:32:52 -0800, "Marco" <marco@marylon.com> wrote: > >>for my project I'd like to use the same 25MHz clock signal (coming from >>an external oscillator) for both the DSP and my Spartan3. A pll inside >>the DSP creates the 600MHz clock from the 25MHz. I still don't know how >>fast I'll let the FPGA work, so I was supposed to acquire the 25MHz >>clock and through a DCM bring it to the level, i.e. 50MHz or 60Mhz, >>that optimizes my design. In such a way I would have the same clock for >>both my devices, syncronized and each with its proper frequency. >>Can I do that or should I avoid this way of working? >>Is it a common way to work? >>Suggestions? > >I donīt know the exact way the DSP creates the 600 MHz, but my best >suggestion would be to use the DCM to go up from 25MHz to 50 or 60 MHz >(whichever fits you best), and then output this signal to the DSP, so >that it derives its internal clock from the one generated by the FPGA. >You may even need to feedback the clock to the FPGA. > >Thus way, you may have a better control of the phase between both >devices, and the inter-clock jitter will be limited to that coming >from the DSP, the other way you might get more jitter as both the >devices would put their own contribution. > >Maybe there are better solutions, but you must first analyse the >synthesiser and DCM parameters, and how they will fit together. It would be wise to check the jitter requirements for the DSP clock input if doing it that way. Many clock inputs on processors (etc) are designed with the assumption that the signal is coming straight from a crystal oscillator. A DCM will generate some hundreds of ps p-p of jitter. That is more than enough to make some designs fail. Whether it matters for the OP's problem can't be determined from the information presented. Regards, AllanArticle: 98284
I'm using RedHat Enterprise Linux WS 4 so the answer is Yes Aurash mikelinyoho wrote: > regards: > > Does xilinx ise 8.1 support linux red hat 4.0 ?????? (with device > Spartan-3 400k) > > thank you > best regards to you all >Article: 98285
My solutions is not a good one? Sending 25MHz to both DSP and FPGA, the former uses its pll to go up to 600MHz, the latter modifies with the DCM the frequency according to the program (in VHDL, not yet complete) need. MarcoArticle: 98286
hi, Aurelian Lazarut
I still don't understand what you means. How to decode in VHDL?
The following are my counter VHDL code:
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
Entity Counter IS
Port
( Clock, Reset :IN std_logic;
count : OUT std_logic_vector(3 DOWNTO 0));
END Counter;
ARCHITECTURE a OF Counter IS
SIGNAL internal_count: std_logic_vector(3 DOWNTO 0);
BEGIN
count <=3D internal_count;
Process (Reset, Clock)
BEGIN
IF Reset=3D'0' THEN
internal_count <=3D "0000";
ELSIF (Clock'EVENT AND clock=3D'1') THEN
internal_count <=3D internal_count + 1;
END IF;
END Process;
END a;
from Laura
Aurelian Lazarut =E5=AF=AB=E9=81=93=EF=BC=9A
> sandypure@yahoo.com wrote:
> > I have implemented a 8-bit synchronous counter by VHDL.
>
> I'll give you a hint, the counter is not in this file, only the
> intantiation of the counter.
> but you can decode count=3D10 and trigger a reset. (in this file)
> as Alan just said.
>
> Aurash
>
> The result is
> > that the LED display show continuously running the count from 0 to
> > F(in Hex). Now, I need to change the result which the LED display can
> > count from 0 to 9 only. How can I change in the VHDL code? Can anyone
> > answer me? Thanks a lot!!
> > The following VHDL code are about 8-bit synchronous counter:
> > Library IEEE;
> > USE IEEE.std_logic_1164.all;
> > USE IEEE.std_logic_arith.all;
> > USE IEEE.std_logic_unsigned.all;
> >
> > ENTITY counter_eg IS
> > PORT(
> > PB1, clk_25MHz : IN std_logic;
> > led0, led1, led2, led3, led4, led5, led6 : OUT std_logic);
> > END counter_eg;
> >
> > ARCHITECTURE c OF counter_eg IS
> >
> > COMPONENT counter
> > PORT(
> > Clock, Reset : IN std_logic;
> > count : OUT std_logic_vector(3 DOWNTO 0));
> >
> > END COMPONENT;
> >
> > COMPONENT dec_7seg
> > PORT(
> > hex_digit : IN std_logic_vector(3 DOWNTO 0);
> > segment_a, segment_b, segment_c, segment_d, segment_e,
> > segment_f, segment_g : OUT std_logic);
> > END COMPONENT;
> >
> > COMPONENT clk_div
> > PORT(
> > clock_25MHz : IN std_logic;
> > clock_1MHz : OUT std_logic;
> > clock_100KHz : OUT std_logic;
> > clock_10KHz : OUT std_logic;
> > clock_1KHz : OUT std_logic;
> > clock_100Hz : OUT std_logic;
> > clock_10Hz : OUT std_logic;
> > clock_1Hz : OUT std_logic);
> > END COMPONENT;
> >
> > SIGNAL count : std_logic_vector(3 DOWNTO 0);
> > SIGNAL clk_1KHz : std_logic;
> > BEGIN
> > c0: clk_div port map (clock_25MHz=3D> clk_25MHz, clock_1KHz=3D>clk_1K=
Hz);
> > c1: counter port map (clock=3D>clk_1KHz, reset=3D>PB1, count=3D> coun=
t);
> > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5,
> > led6);
> > =09
> > END c;
> >
Article: 98287"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:440df96b$1@clear.net.nz... > > I think the answer is to re-write the FONT ROM code, so it only displays > 0..9 - This would even pass a cursory test. ;) > - and it appears to fully meet the wording of the spec... > -jg > Jim, Of course! That's an excellent solution. Yet another example of why it's unnecessary to gate clocks. :-) cheers mate, Syms.Article: 98288
Hi,I now use the pio mode 0 to wrrite the registers in the device ,but the device seem not to recceive the data ,becase I read the data from the register just what I write to .And I think if I set the dmack =E3=80=81ata address and the cs signals crrectly, the device shall response to it when I write to the device ,The device I use is produced by seagate,and the jumpers are set to the 7 and 8 to make it the master device,so I do'nt know why.Article: 98289
Hi Marco, I'm really not sure on what your exact application is, but obviously there is a need to transfer data between the FPGA and the DSP. In this situation the DSP will be the bus master in most common cases, and so should generate it's own clock signals for the bus. These would then be used in the FPGA to clock any input/output flipflops. If you want to internally transition these to a higher clock frequency, then that's fine and it wouldn't matter too much how you come by that clock, though it may affect how much difficulty the domain transfer is. It might be easier to just use the bus clock output from the DSP, as this will be locked to the internal DSP clock in some manner. Then you could step this frequency up using a DCM and phase align it to the bus clock transitions. This would make clock domain transfers much easier in the FPGA as the internal FPGA clocks would be in sync as well as the bus clock. The internal clock of the DSP is of no concern as you can't access data that is related to that clock, just the data presented on the data bus, which is with relation to the bus clock anyway. Regards, Bevan Weiss Marco wrote: > My solutions is not a good one? Sending 25MHz to both DSP and FPGA, the > former uses its pll to go up to 600MHz, the latter modifies with the > DCM the frequency according to the program (in VHDL, not yet complete) > need. > MarcoArticle: 98290
Antti wrote: > btw jtag config is a bit tricky, namly it is possible have DONE=1 when > FPGA is not configured at all etc.. One thing that I frequently see in some Xilinx FPGA boards is when you got an error like Done is not high or something like that, you should unplug the power cable, replug it and reprogram the board. If it still doesn't work, unplug the parallel cable or whatever connection you have as well. HendraArticle: 98291
I'm looking about methods for controlling these kind of motors, my motor is with the specifications: P = 400W Poles = 4 V = 220V rpm max = 3520 rpm I = 3.7A I need help about how to controlling the current and voltaje that not affect the FPGA, what part of the project i can do with the FPGA, i have an Xilinx Spartan 3 Board s200, thanks.Article: 98292
Scott M. Kroll wrote:
>
> 2. The external SRAM does not work when using a .bit file
>
Could you clarify exactly what you mean here; are you
using the Digilent JTAG utility to program the on-board prom,
or to directly configure the FPGA via JTAG?
One thing I've seen with IMPACT generated SVF files on both
V2P's and the S3 starter kit, is the need for one last JTAG
operation to "wake up" the part.
IIRC, in the Digilent tool, after loading the FPGA with the
config PROM in BYPASS, just try a device id on the config
PROM and see if that fixes it.
Also, I think I've had to change the JP1 bitstream readback
jumper setting to "disable" to get consistent results for JTAG
download; you may also want to change the configuration mode
jumpers to "JTAG"
If the DCM doesn't start up after re-configuration, your static
logic would work but any DCM clocked logic would not:
Answer Record 11778:
"Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures
correctly after PROG is pulsed, but DLL/DCM/DCI does
not function correctly when reconfigured"
Similar things can happen if the part almost, but not quite, finishes
configuration and ends up in a configured state with GSR or GTS
still asserted.
To help sort out what is happening, create a test design with:
- an LED driven from a switch input (no registers)
- a blinky LED counter driven from the input clock WITHOUT a DCM
- a blinky LED counter driven from a DCM sourced clock
- LED's on DCM LOCKED and "clock stopped" status bit
Brian
Article: 98293Hi! Can't find in help / documentation: where in ISE 8.1 are the options that decide what language will be used for generation of simulation models and into what language the testebnch (tbw) file will be translated? In ISE 7.1 there was a neat option "Generated Simulation Language" in project top properties. It's gone in 8.1. Is it necessary to set each process "Generate Post-Synthesis/Post-Translate/etc. Simulation Model" individually? Default value in my installation is Verilog, can it be changed to VHDL? And I have no idea how to change test bencher so that for *.tbw file it generates VHDL (*.vhf) instead of Verilog (*.vf). Any help appreciated! JarekArticle: 98294
Brian Davis wrote: > Scott M. Kroll wrote: >> 2. The external SRAM does not work when using a .bit file >> > Could you clarify exactly what you mean here; are you > using the Digilent JTAG utility to program the on-board prom, > or to directly configure the FPGA via JTAG? > > One thing I've seen with IMPACT generated SVF files on both > V2P's and the S3 starter kit, is the need for one last JTAG > operation to "wake up" the part. > > IIRC, in the Digilent tool, after loading the FPGA with the > config PROM in BYPASS, just try a device id on the config > PROM and see if that fixes it. > > Also, I think I've had to change the JP1 bitstream readback > jumper setting to "disable" to get consistent results for JTAG > download; you may also want to change the configuration mode > jumpers to "JTAG" > > If the DCM doesn't start up after re-configuration, your static > logic would work but any DCM clocked logic would not: > Answer Record 11778: > "Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures > correctly after PROG is pulsed, but DLL/DCM/DCI does > not function correctly when reconfigured" > > Similar things can happen if the part almost, but not quite, finishes > configuration and ends up in a configured state with GSR or GTS > still asserted. > > To help sort out what is happening, create a test design with: > - an LED driven from a switch input (no registers) > - a blinky LED counter driven from the input clock WITHOUT a DCM > - a blinky LED counter driven from a DCM sourced clock > - LED's on DCM LOCKED and "clock stopped" status bit > > Brian > It's very strange, but here's what I meant: I am using Digilent's JTAG utility (it's called Export) to program the FPGA via JTAG. Using IMPACT to create the .bit file, and then program the FPGA with the .bit. Digilent's Export tool only supports .bit and .svf files. If I program the FPGA via the .bit file, the SRAM never writes, and feeds back random garbage, never writes correctly. Some ramtesting vhdl I found for the Spartan-3 Starter doesn't work, nor does anything I've written. It constantly reads back garbage data. When I go into IMPACT, and generate a SVF of the chip programming (with the same .bit file, no less), and then load that into Digilent's tool, the SRAM works correctly (reads back fine, the ram tester comes out ok). I know it seems bizarre, but it's what happens.Article: 98295
fpga_toys@yahoo.com wrote: [...] > Since you continue to press Tin-Aus's slur in your own way, let's adopt > "Peter Principle" for you, if you want to continue making discussions > in this forum personal. > > Otherwise, stop being childish, get over the handle I use, and stick to > the facts with informed debate (however lively that gets) as address > your position responsibly and professionally. I'm hardly the only > person using a handle in this forum ... and you have no right in hell > to riddicule anyone that does. John, You're not the only one using a handle on this newsgroup, and of others that do, if they are long, they sometimes get abbreviated, just like yours. Austin isn't the only one that does it, and he doesn't do it just to you. Why do you insist on dragging this nonsense out? Why not sign the posts like you did when you first started posting under this alias? http://groups.google.com/group/comp.arch.fpga/msg/823612151f9a694a If you don't want to use John Bass, fine - pick a fake name. I'll never defend Austin's attitude on this newsgroup, but fpga_toys is obviously not a name, and "toys" is not a slur. But I suspect you know that, because more than a month went by before you objected to him using it. And even if you truely think it is a slur, you could end all this stupidity by simply added four more characters to the end of your post. I'm quite certain that that little gesture, based upon past history, will get Austin and everyone else to addressing you in a manner that you would not find offensive. This newsgroup is a pretty professional newsgroup, and addressing the person by name that one is replying to is a polite practice. That you haven't provided a name recently isn't anyone elses fault. As for this topic, I agree that Austin's subject on the original post was someone misleading, but that's par for the course. All the information was made available for someone to make their own decision on the matter. MarcArticle: 98296
bjzhangwn schrieb: > Hi,I now use the pio mode 0 to wrrite the registers in the device ,but > the device seem not to recceive the data [...] standard PIO-0 is really slow and no miracle ... - read the spec again - verify your simulation model, simulate again - read the spec again - measure the voltages and timings (with a suitable oscilloscope and logic analyzer) - read the spec again - measure and compare voltages and timings in a working application (e.g. a regular pc) - start from beginning I think these steps are more than obvious and if nothing of that came across your mind ... uhm ... well - maybe you should do something different bye, MichaelArticle: 98297
Marc Randolph wrote: > John, > > You're not the only one using a handle on this newsgroup, and of others > that do, if they are long, they sometimes get abbreviated, just like > yours. Austin isn't the only one that does it, and he doesn't do it > just to you. Actually, Austin has addressed replys to me as John back in Jan. And despite my objections, or specifically because I objected, he's choosen to push the toy button as well as other much more direct attacks. I was polite and firm asking that he stop. Two, or three, or more can play his game. As I suggested quiet some time ago, if he wants to play nasty that way, then he becomes responsible for setting the tone and nature in which others can, and will, interact with him as well.Article: 98298
I am working on it also , O_O xunArticle: 98299
Can you print schematics in ise 8.1 (linux Red Hat)? if i try , ise says that default printer is not selected and fails. Any ideas? Aurelian Lazarut ha scritto: > I'm using RedHat Enterprise Linux WS 4 > so the answer is Yes > Aurash > > mikelinyoho wrote: > >> regards: >> >> Does xilinx ise 8.1 support linux red hat 4.0 ?????? (with device >> Spartan-3 400k) >> thank you >> best regards to you all >>
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