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Hello guys, I have a system FPGA in vhdl for the virtex board and would like to generate DDR controller . When i tried to generate a DDR SDRAM controller using the MIg1.5 it give verilog files.and i wasnt able to see any settings for the language selection in the mig too. thanks in advance subinArticle: 103576
Hello guys, I have a system FPGA in vhdl for the virtex board and would like to generate DDR controller . When i tried to generate a DDR SDRAM controller using the MIg1.5 it give verilog files.and i wasnt able to see any settings for the language selection in the mig tool. thanks in advance subinArticle: 103577
I deffinatelly recommend Platform Cable USB if you willing to give 150$. Otherwise build or buy Parallel cable III (very low cost). Cheers, GuruArticle: 103578
subint wrote: > Hello guys, > I have a system FPGA in vhdl for the virtex board and would like to > generate DDR controller . When i tried to generate a DDR SDRAM > controller using the MIg1.5 it give verilog files.and i wasnt able to > see any settings for the language selection in the mig tool. > thanks in advance > subin > Whne you're running the Core Generator, choose 'Project Options...' from the Projects menu. This will bring up a dialog box. Choose the 'Generation' tab and in the 'Flow' box choose VHDL. Most of the cores will give you an option to create or regenetate cores using the new settings or using the previous setting. --- Joe Samson Pixel VelocityArticle: 103579
subint wrote: > Hi guys, > Thanks for the reply. > I am still confused. > Is it possible to use the code without removing the > testbench?. Where is the actual interface for the data and address bus. > is it in the topmodule or it is the one driven by the testbench. In the DDR2 design, the testbench is integrated into the design several levels of hierarchy down from the top. All that is exposed at the top are the signals to the SDRAM and an error signal. If you go to the main_0 hdl code, you will see that test_bench_0 and top_0 are instantiated there. You will have to find the user interface signals that pass between test_bench_0 and top_0 and route them up the hierarchy. It would have been a lot nicer if the testbench connected to the memory controller at the top of the hierarchy like a user's interface would. You will have to remove the test bench because it will drive signals that your design also has to drive. --- Joe Samson Pixel VelocityArticle: 103580
Hi, Can anyone tell me how I can count the number of instructions or cycles needed for a particular piece of code? Other than stepping over in the debugger :) Thanks, e.Article: 103581
hi, it's true, but i was not able to run the mig from the core generator.don't know why. Actually i am opening the mig from the installed directory(there is a batch file named mig.) . subin Joseph Samson wrote: > subint wrote: > > Hello guys, > > I have a system FPGA in vhdl for the virtex board and would like to > > generate DDR controller . When i tried to generate a DDR SDRAM > > controller using the MIg1.5 it give verilog files.and i wasnt able to > > see any settings for the language selection in the mig tool. > > thanks in advance > > subin > > > Whne you're running the Core Generator, choose 'Project Options...' from > the Projects menu. This will bring up a dialog box. Choose the > 'Generation' tab and in the 'Flow' box choose VHDL. Most of the cores > will give you an option to create or regenetate cores using the new > settings or using the previous setting. > > --- > Joe Samson > Pixel VelocityArticle: 103582
Kolja Sulimma <news@sulimma.de> wrote: >Peter Alfke schrieb: >> rickman wrote: >>>with IT, the secretary being out of the office (no credit card >>>purchases) and the general BS of working in a defense company. >> I will poke around in Xilinx, if there is a meaningful way to overcome >> real and also bureaucratic/security obstacles. >While I am sure that a defense company can afford a DVD burner to obtain >software, as a CAD software developer I always wondered, why a single >FPGA device needs more than 40MB of characterisation data. >Rethinking the file format for the NPH and GRF files would probably >reduce the foundation install size by 1GB. What do those files really contain? ;) >I guess the format was invented in XC2K times and noone really thought >that exploiting the regularity in the device would be worth the hassle. I did a quick check for the space that the filetypes use up: Percent: Size: Suffix: 18.87% 356.1MB nph \ 11.86% 223.9MB so -- 41% .. 10.21% 192.7MB pdf / 6.31% 119.2MB (no suffix) 5.79% 109.4MB bsd 4.38% 82.7MB bin 4.34% 82.0MB ngc 3.48% 65.8MB vhd 3.23% 61.1MB vho 3.22% 60.9MB jar 3.18% 60.1MB grf 2.65% 50.2MB htm 2.31% 43.7MB sch 2.15% 40.7MB class 1.40% 26.4MB spd 1.29% 24.4MB lzp 1.24% 23.5MB edn 1.06% 20.1MB v As for directories in kBytes: 306890 coregen 236992 bin 204278 doc 201538 virtex4 122558 vhdl 106958 virtex2p 106094 verilog 86608 java 85752 gnu 75094 virtexe 71092 virtex2 55478 spartan3 49816 virtex 46662 smartmodel 36302 spartan3e 27648 data 24398 spartan2e 16340 chipviewer 12988 spartan2 12590 xpla3 12030 xbr 11886 ISEexamplesArticle: 103583
Yes chips are fitted. The RS1-1500 has a XC3S1500. I will see if we can get the text a little less ambiguous. There are a few areas like this that we need to tidy up on the website. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Dave Farrance" <DaveFarrance@OMiTTHiSyahooANDTHiS.co.uk> wrote in message news:fsla82paqfo8htedeorljamtjn2f0090hn@4ax.com... > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> > wrote: > >>Have a look at this module >>http://www.enterpoint.co.uk/moelbryn/modules/usb_ps2.html in conjunction >>with our Raggedstone1 product. Basically the module is a voltage >>limiter(bus >>switch) on the USB lines leaving the logic to be implemented in the FPGA. > > Thanks. I'm a bit confused by the "shop" section. The RS1-400 and the > RS1-1500 both have the same description including: > > "FPGA: XilinxTM SpartanTM-3 FPGA, in FG456 package, fitted to the > board. Available with XC3S400 fitted." > > I presume that it should be the XC3S1500 in the latter case. > > Also the wording is ambiguous. I presume that "Available with XC3S400 > fitted" does mean that the FPGA *is* fitted for the that price, rather > than being an option? > > -- > Dave FarranceArticle: 103584
Where can one find a schematic of a parellel port jtag programmer? "Guru" <ales.gorkic@email.si> skrev i meddelandet news:1149591274.181317.159500@j55g2000cwa.googlegroups.com... > > > I deffinatelly recommend Platform Cable USB if you willing to give > 150$. > Otherwise build or buy Parallel cable III (very low cost). > > Cheers, Guru >Article: 103585
Ben,
Here's the timing analyzer report for one of the failing paths. I don't
see where it's coming up with a period of 20.255ns. If you are curious
I could paste the constraints file, but it seems fairly vanilla to
me...
<SNIP>
================================================================================
Timing constraint: TS_sys_clk_in = PERIOD TIMEGRP "sys_clk_in" 112 MHz
HIGH 50%;
1270 items analyzed, 11 timing errors detected. (11 setup errors, 0
hold errors)
Minimum period is 20.255ns.
--------------------------------------------------------------------------------
Slack: -2.644ns (requirement - (data path - clock path
skew + uncertainty))
Source: inst_ddr/U3/BU510 (FF)
Destination: inst_ddr/U3/BU212 (FF)
Requirement: 2.084ns
Data Path Delay: 3.140ns (Levels of Logic = 6)
Clock Path Skew: -1.588ns
Source Clock: sys_clk rising at 59471.130ns
Destination Clock: out_clk rising at 59473.214ns
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: inst_ddr/U3/BU510 to inst_ddr/U3/BU212
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.419 inst_ddr/U3/BU510
net (fanout=4) 0.782 inst_ddr/U3/N6047
Topcyg 0.722 inst_ddr/U3/BU183
inst_ddr/U3/BU184
net (fanout=1) 0.000 inst_ddr/U3/N7188
Tbyp 0.088 inst_ddr/U3/BU187
inst_ddr/U3/BU190
net (fanout=1) 0.000 inst_ddr/U3/N7186
Tbyp 0.088 inst_ddr/U3/BU193
inst_ddr/U3/BU196
net (fanout=1) 0.000 inst_ddr/U3/N7184
Tbyp 0.088 inst_ddr/U3/BU199
inst_ddr/U3/BU202
net (fanout=1) 0.000 inst_ddr/U3/N7182
Tbyp 0.088 inst_ddr/U3/BU205
inst_ddr/U3/BU208
net (fanout=1) 0.000 inst_ddr/U3/BU208/O
Tcinx 0.865 inst_ddr/U3/BU211
net (fanout=1) 0.000 inst_ddr/U3/N7192
Tdxck 0.000 inst_ddr/U3/BU212
---------------------------- ---------------------------
Total 3.140ns (2.358ns logic, 0.782ns route)
(75.1% logic, 24.9% route)
--------------------------------------------------------------------------------
Slack: -2.580ns (requirement - (data path - clock path
skew + uncertainty))
Source: inst_ddr/U3/BU503 (FF)
Destination: inst_ddr/U3/BU212 (FF)
Requirement: 2.084ns
Data Path Delay: 3.076ns (Levels of Logic = 6)
Clock Path Skew: -1.588ns
Source Clock: sys_clk rising at 59471.130ns
Destination Clock: out_clk rising at 59473.214ns
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: inst_ddr/U3/BU503 to inst_ddr/U3/BU212
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.419 inst_ddr/U3/BU503
net (fanout=4) 0.608 inst_ddr/U3/N6048
Topcyf 0.832 inst_ddr/U3/BU180
inst_ddr/U3/BU181
inst_ddr/U3/BU184
net (fanout=1) 0.000 inst_ddr/U3/N7188
Tbyp 0.088 inst_ddr/U3/BU187
inst_ddr/U3/BU190
net (fanout=1) 0.000 inst_ddr/U3/N7186
Tbyp 0.088 inst_ddr/U3/BU193
inst_ddr/U3/BU196
net (fanout=1) 0.000 inst_ddr/U3/N7184
Tbyp 0.088 inst_ddr/U3/BU199
inst_ddr/U3/BU202
net (fanout=1) 0.000 inst_ddr/U3/N7182
Tbyp 0.088 inst_ddr/U3/BU205
inst_ddr/U3/BU208
net (fanout=1) 0.000 inst_ddr/U3/BU208/O
Tcinx 0.865 inst_ddr/U3/BU211
net (fanout=1) 0.000 inst_ddr/U3/N7192
Tdxck 0.000 inst_ddr/U3/BU212
---------------------------- ---------------------------
Total 3.076ns (2.468ns logic, 0.608ns route)
(80.2% logic, 19.8% route)
--------------------------------------------------------------------------------
Slack: -2.550ns (requirement - (data path - clock path
skew + uncertainty))
Source: inst_ddr/U3/BU188 (FF)
Destination: inst_ddr/U3/BU212 (FF)
Requirement: 2.084ns
Data Path Delay: 3.046ns (Levels of Logic = 5)
Clock Path Skew: -1.588ns
Source Clock: sys_clk rising at 59471.130ns
Destination Clock: out_clk rising at 59473.214ns
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: inst_ddr/U3/BU188 to inst_ddr/U3/BU212
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.419 inst_ddr/U3/BU188
net (fanout=1) 0.776 inst_ddr/U3/N6065
Topcyg 0.722 inst_ddr/U3/BU189
inst_ddr/U3/BU190
net (fanout=1) 0.000 inst_ddr/U3/N7186
Tbyp 0.088 inst_ddr/U3/BU193
inst_ddr/U3/BU196
net (fanout=1) 0.000 inst_ddr/U3/N7184
Tbyp 0.088 inst_ddr/U3/BU199
inst_ddr/U3/BU202
net (fanout=1) 0.000 inst_ddr/U3/N7182
Tbyp 0.088 inst_ddr/U3/BU205
inst_ddr/U3/BU208
net (fanout=1) 0.000 inst_ddr/U3/BU208/O
Tcinx 0.865 inst_ddr/U3/BU211
net (fanout=1) 0.000 inst_ddr/U3/N7192
Tdxck 0.000 inst_ddr/U3/BU212
---------------------------- ---------------------------
Total 3.046ns (2.270ns logic, 0.776ns route)
(74.5% logic, 25.5% route)
--------------------------------------------------------------------------------
</SNIP>
When I use the Timing Improvement Wizard hyperlink for each it says:
"75.10 percent is consumed by logic levels in this path.
This path crosses clock domains from "sys_clk" to "out_clk"."
I suppose the clock domain dependence have something to do with this...
I found that this "out_clk" is the input to one of their fifo
controllers and is connected to the 100 MHz board clock... Fortunately
I was able to convince one of their engineers that this needs to be
fixed, especially since they advertise user customization of the FPGA!
O_o
Thanks,
-Brandon
Ben Jones wrote:
> "Brandon Jasionowski" <killerhertz@gmail.com> wrote in message
> news:1149546962.801753.53900@h76g2000cwa.googlegroups.com...
> > Ok, so I'm working with a COTs DSP board vendor's ISE project and
> > customizing the logic (essentially tossing code in a user wrapper).
> > Unfortunately, I'm having some 'user-friendly' issues with the project
> > file and customizability.
>
> > 1) 'sys_clk_in' is a board clock at 100 MHz (constrained to 112 MHz)
> > 2) 'sys_clk' is derived from 'sys_clk_in' via DCM's fx output at 4/3.
> > 'sys_clk' needs to operate at 125 MHz (constrained to ~150 MHz).
>
> > -His response:
> > <SNIP>"You're right. The Xilinx tool has a bug. Something about
> > spinning up a clock using a DCM & subsequent timing analysis. The
> > hardware does work."</SNIP>
> >
> > -My questions to those experienced:
> > I've seen clock's overconstrained before with another vendor.
> > 1) Is this a common practice? If so, I could envision timing results
> > being highly overconstrained when dealing with DCMs.
>
> It is reasonably common to see designs overconstrained in the synthesis
> phase, to compensate for the fact that many synthesis tools underestimate
> the routing delays in a design. It's not an ideal situation, but often it's
> the only way to ensure the design meets timing later on.
>
> The only reason I can think of to overconstrain a design at the PAR stage is
> if there is a requirement that the FPGA clock be variable without altering
> the FPGA bitstream. That is, in your case, if the sys_clk_in could
> theoretically one day be run at up to 112MHz.
>
> Otherwise, overconstraining the clock at PAR is pointless (you just increase
> the runtime of the tools without buying yourself any extra performance).
>
> > 2) Is this really a bug or is the project misconstrained?
>
> Hard to say, without seeing the constraints file.
>
> The "hold error" is a little worrying (maybe this is an IO placement
> issue?), and the 20us cycle time figure for the 150MHz "TS_clk_fx" domain is
> very strange indeed - is there really a path that long in the design? That
> sounds like a good candidate for a bug. It's not one I've heard of though
> (anyone?).
>
> BTW, what version of the Xilinx tools are you using?
>
> > 3) Am I crazy to think it's unreasonable to be given a
> > 'user-defineable' project with timing that is seemingly failing by
> > default? (i.e. how am I to modify the project and know it will work if
> > the baseline does not meet timing?)
>
> No, you're not crazy.
>
> I've seen some FPGA projects where the engineer just eyeballs the log file
> full of timing errors and says, "that's not a problem, that's not a
> problem...". Not a good way to work. If you don't have any documentation of
> exactly why these timing errors are there and a good engineering
> justification of why they don't matter - preferably including timing
> diagrams - I would run away. If you have that option, of course. :-)
>
> -Ben-
Article: 103586
<eascheiber@yahoo.com> wrote in message
news:1149595856.563215.72500@h76g2000cwa.googlegroups.com...
> Hi,
>
> Can anyone tell me how I can count the number of instructions or cycles
> needed for a particular piece of code? Other than stepping over in the
> debugger :)
You can get an assembly listing with something like objdump -d <yourfile>,
and count by hand (or automatically). This will tell you how many
instructions are needed to implement a particular function, but not how many
instructions will actually be executed when running that function (because
you need to know how all the branches behave).
Thinking fast - if your debugger has a "run for N instructions" facility,
you can use that to manually perform a binary search - go to the start of
the function, set a breakpoint at the end, run for 100,000 instructions,
then 50,000, then 25,000, then 37,500... braketting until you've got an
accurate-enough answer.
With a following wind, that might even be scriptable.
-Ben-
Article: 103587
Hi Brandon,
"Brandon Jasionowski" <killerhertz@gmail.com> wrote in message
news:1149600989.491728.162420@f6g2000cwb.googlegroups.com...
> Ben,
>
> Here's the timing analyzer report for one of the failing paths. I don't
> see where it's coming up with a period of 20.255ns. If you are curious
> I could paste the constraints file, but it seems fairly vanilla to
> me...
> <SNIP>
> Source Clock: sys_clk rising at 59471.130ns
> Destination Clock: out_clk rising at 59473.214ns
> <MORE SNIP>
>
> I suppose the clock domain dependence have something to do with this...
> I found that this "out_clk" is the input to one of their fifo
> controllers and is connected to the 100 MHz board clock...
Yes, those paths you posted are all crossing clock domains. If the clocks
are related, then this should be specified somewhere; if they are unrelated,
and there is proper clock-domain-crossing synchronization logic in place,
then they should be marked as "ignore" to the timing analyser by means of a
"TIG" constraint. If they are the same, they shouldn't be different. If you
see what I mean.
FWIW, the timing analyser comes up with the 20.255ns number by working
backwards from the e.g. 3.140ns path it achieved for the offending logic,
and asking itself "how slow do I have to run sys_clk_in in order for this
timing error to go away?".
Cheers,
-Ben-
Article: 103588bh, We are actively working with many military contractors on packaging. And, they have been tested, and they don't fare well. All our packages breath. If they get conformal coated, then any moisture inside is trapped. If they could bake before coat, potentially this works ... but the tests continue. Then when the heat is on, they POP if they adsorbed any moisture (even through the coating). This is not unique to Xilinx, but an industry wide problem with all flip chip packages today. In the FPGA business we have the distinction of making the largest die in the industry. In the lobby of the IDA building http://www.ida.org/ there area series of posters of pcbs. Center in many of them is a Xilinx FPGA. These posters caught many by surprise, as in most recent systems, there is a Xilinx FPGA. (Even the military had no idea how pervasive FPGAs have become) Coatings are typically used where there is no protection from the environment at all. Many systems provide environmental protection at the box level. There are some packages which are qualified for coating (hermetic), but they are either too small for our die, or they have not been qualified for our use, yet. Austin bh wrote: > Xilinx app note XAPP426 v1.3 (March 2006) indictes that: > "Xilinx has no experience or reliability data on flip-chip BGA packages > on board after exposure to conformal coating." > > WTFO ? > > How is it possible with Xilinx being so tight with Military > developers that they haven't tested their parts under the > conditions which nearly all military boards are produced? > > What am I missing? Have they been sworn to secrecy? :-)) > > -BH > > >Article: 103589
Dear All,
I'm trying to use a GIPO module in my application, but I can't figure
out how to use it
and the GPIO specification (DS466) and software API definition document
are not helping
much.
I need 32 lines for input and 32 different lines for output. I decided
to use a GPIO
core, 32 bits wide, configured as single channel. The idea is to read
data from the
GPIO_in pins and write data to GPIO_d_out pins. I have parameterized
the core as follows:
C_GPIO_WIDTH 31
C_ALL_IMPUTS 0
C_IS_BIDIR 0
C_IS_DUAL 0
So, my first question is: Is there something wrong with this
configuration? Can I us it?
Next, I try to write to the core. I used the following instructions:
XGpio gpio_io;
XGpio_Initialize(&gpio_io, XPAR_GPIO_IOPORT_DEVICE_ID);
XGpio_DiscreteWrite(&gpio_io,1,255);
Noting happens. Do I have to set the direction with
XGpio_SetDataDirection? Do I have
to use other functions?
Tanks to all
Jos=E9 Mariano
Article: 103590Hello all, First of all I have to say that I'm completely new with the FPGAs. I have just received Xlinx ML403 and I have some problems/questions: 1. When I tried to use demos which requires NIC on the PC side I could use e.g. Intel(R) PRO/1000 MT NIC and everything is OK but when I connect to NVIDIA nForce built-in (ASUS A8N-E motherboard) NIC connection is established, no packets are received (TX diode shows that board is transmitting). On the other hand the NIC itself is OK when working with other NICs/switches. What do you think the problems is rather connected with the NIC or with the board? 2. I have download Ethernet Cores Hardware Demonstration Platform (xapp443) and when I use it with hard MAC I could not send frames bigger than 4000 bytes, the other issue is that the maximum speed I got using 1500 bytes frames and the speed is 840 Mbps (payload). I think should be better (close to 1 Gbps) and for the bigger frames faster not slower. How to send 9k (or if not possible 4k) frames with 1 Gbps speed. 3. Where I can find description how to prepare my own boot menu for bitstreams on CF card for the System ACE. Best regards, BartekArticle: 103591
Ryan Laity wrote: > Rickman, > > You don't have to install them using the web installer - that's why I > suggested that you check the "Install Later" box once the installer > downloads and you run it. That makes the Web Installer just act like a > download tool. You get installers that can easily be installed from a > CD at a later time (even by IT). > > I've also forwarded this request on the right person within Xilinx, > perhaps he will comment. I certainly don't think that the web installer > is the most intuitive way to download individual installers so I am > motivated to get this suggestion in the hands of someone who can do > something about it. Nonetheless, I've used this method for my customers > (I'm an FAE) to get a lab-only install of iMPACT standalone, so I've > been through it myself. I can't even get that to work. For whatever reason, Xilinx requires that you provide a password to download webpack. I can't get my password to work and I can't seem to get a new one. I have gone to the page for getting a new password several times and I never get the email. At this point I am not going to order the software. I'll just wait for IT to get around to doing the job. I am getting tired of trying to push this rope.Article: 103592
If you actually check the example program in the installed EDK folder, you find an example that uses the GPIO components. You have to set the data direction using the XGpio_mSetDataDirection function and use XGpio_mSetDataReg function to set the GPIO component. jmariano wrote: > Dear All, > > I'm trying to use a GIPO module in my application, but I can't figure > out how to use it > and the GPIO specification (DS466) and software API definition document > are not helping > much. > > I need 32 lines for input and 32 different lines for output. I decided > to use a GPIO > core, 32 bits wide, configured as single channel. The idea is to read > data from the > GPIO_in pins and write data to GPIO_d_out pins. I have parameterized > the core as follows: > C_GPIO_WIDTH 31 > C_ALL_IMPUTS 0 > C_IS_BIDIR 0 > C_IS_DUAL 0 > > So, my first question is: Is there something wrong with this > configuration? Can I us it? > > Next, I try to write to the core. I used the following instructions: > XGpio gpio_io; > XGpio_Initialize(&gpio_io, XPAR_GPIO_IOPORT_DEVICE_ID); > XGpio_DiscreteWrite(&gpio_io,1,255); > > Noting happens. Do I have to set the direction with > XGpio_SetDataDirection? Do I have > to use other functions? >=20 > Tanks to all >=20 > Jos=E9 MarianoArticle: 103593
On the Xilinx web site. A google search will turn up many more.Article: 103594
> 1. When I tried to use demos which requires NIC on the PC side I could > use e.g. Intel(R) PRO/1000 MT NIC and everything is OK but when I > connect to NVIDIA nForce built-in (ASUS A8N-E motherboard) NIC > connection is established, no packets are received (TX diode shows that > board is transmitting). you are using a crosslink cable? some NICs have some auto-swap-input-pins feature ... maybe your intel has - try to run the connection over a switch where you can see the link status of both sides bye, MichaelArticle: 103595
eascheiber@yahoo.com wrote: > Hi, > > Can anyone tell me how I can count the number of instructions or cycles > needed for a particular piece of code? Other than stepping over in the > debugger :) > > Thanks, > e. > To count the number of cycles, use the time stamp counter present in the PPC. If you are using Xilinx EDK, you can use XTime_GetTime() routines to access the TSC..or you can always write assembly code. /SivaArticle: 103596
First, your code (both versions) will create latches, not registers. You need a clock edge specification: if rising_edge(clk) then -- decode/assignment statements go here end if; Second, whenever I see a long case or if-then-else tree, I look for ways to use an array, or array of arrays, to do the decoding for me, possibly within a loop. Think about transforming slices of the address into indices for the array, then assign the desired element(s) of the array from the data bus. For documentation, you can assign meaningfully-named constants to the appropriate index values, and use them where you want to individually access the contents by name. Lastly, VHDL case statement targets are required to be mutually exclusive, therefore no priority is assigned. If-then-else statements do imply priority, but if the synthesis tool is smart enough to figure out that the conditions are all mutually exclusive, then it will remove the priority logic anyway. if address = 1 then a <= data; elsif address = 2 then b <= data; elsif address = 3 then c <= data; end if; Address clearly cannot be 1 and 2 and 3 at the same time; the synthesizer should recognize that and remove the priority logic, creating something that looks more like: if address = 1 then a <= data; end if; if address = 2 then b <= data; end if; if address = 3 then c <= data; end if; or: case address is when 1 => a <= data; when 2 => b <= data; when 3 => c <= data; end case; Andy JonesArticle: 103597
We currently have a Spartan 3 FPGA in our design. In our design, we are using two DCM's specifically. One is driving an off-chip ADC and the other is driving an FPGA register (which registers the data coming back from the off-chip ADC). One clock is manually phase-shifted at synthesis relative to the other clock to resolve clock skew issues between the ADC processing of the data and the output of the ADC being latched into the register. The clock signal to the ADC can be phase-shifted to bring the overall timing within constraint. This setup works so far, but the question is whether it will continue to work as the FPGA temperature changes, and over variations between different chips or slight variations in the voltage supplies. The DCM driving the ADC is physically placed far from the pin which it drives. The routing from DCM to pin is accomplished via hex lines and combinational logic. Are there any general rules which are capable of predicting the sensitivity of propagation delay to temperature, voltage, and chip variations?Article: 103598
FWIW, my ISE8.1 installation has libPlXil_Legal.so in $XILINX/xilinx/bin/lin64 on my RedHat EL3 64-bit machine. Jim http://home.comcast.net/~jimwu88/tools/ Sean Durkin wrote: > Hi *, > > just installed ISE8.1 with SP3 on a 64bit Linux-machine running OpenSUSE > 10. Just thought I'd give it a try, even if it's not officially > supported by Xilinx and I haven't read any reports here on people > getting it to run successfully (BTW, ISE8.1 works fine on other machines > running OpenSUSE, but this is the first 64bit-machine I've tried). > > Anyhow, most of it seems to work fine. The system is detected correctly > as lin64, the GUI works, and the utilities for flow work all right > (meaning XST, ngdbuild, map and so on don't crash and seem to do what > they should). The only thing that does not work is par. Starts up all > right, it reads in the constraints and displays device utilization, but > then exits with a fatal error before it starts placing: > > "Starting Placer > FATAL_ERROR:PersonalityModule:baspmdlm.c:164:1.25 - dll library > <PlXil_Legal> does not exist. Process will terminate. > To resolve this error, please consult the Answers Database and other > online resources at http://support.xilinx.com. > If you need further assistance, please open a Webcase by clicking on the > "WebCase" link at http://support.xilinx.com" > > There's nothing on this on the support website. I've opened a web case, > but since OpenSUSE is not a supported platform, they probably won't be > able to help there. > > Has anyone else seen this? "Xil_Legal" strikes me as kind of an odd name > for a library. It doesn't exist anywhere in the installation > directories, but it's not there on other machines running OpenSUSE > either, and on those machines the tools work fine. > > Has anyone gotten this to work? > > cu, > SeanArticle: 103599
Andy wrote:
> If-then-else statements
> do imply priority,
... if (and only if) two or more cases overlap.
Otherwise, excellent posting.
-- Mike Treseler
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