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Hi, Now I have several options: (I don't care if it is free or paid, because it is a company project, not personal one). The drawback of WinMerge is its search function incompleteness during two file comparison: During two file comparison, what I want most is a function that uses two user-defined fast keys to search forth and back for keyword different appearances and to find their differences between 2 versions. With WinMerge, there is no fast key definition for search. When entering Ctrl+F, it pops a window to search for. If one is found, you must enter Ctrl+F again to search next, ... For example, if I define F3 key is to search forward, F4 key is to search backward. After first highlighting a keyword, then pressing F3, it would go to next key word appearance, or pressing F4, it would go to next keyword appearance backward. Their implementation is not difficult, but greatly reduce the timing to do search. To relieve my pressure, can you please tell me whether or not the tools you suggested and preferred have the functions? Thank you. Weng AxisCompare, Compare,Article: 103726
eascheiber@yahoo.com wrote: > just one question, in xtime_l.c XTime_GetTime function shouldn't use > mftb instead of mfspr. It does not seem to work ok /w mfspr. That's odd. It does look like XTime_GetTime *should* be using mftb. But the mfspr code works fine for me (EDK6.1, EDK7.1, EDK8.1). Alan NishiokaArticle: 103727
Hi all, I use KDiff (http://kdiff3.sourceforge.net/). It's free and very useful (you can ignore case, space for instance). You can compare/merge file and directory. Regards Marcus Harnisch a =E9crit : > Weng, > > I guess nobody has mentioned (X)Emacs+Ediff yet. It makes only sense > with text-based files of course. > > One highlight worth mentioning is the ability to take full advantage > of the editing capabilities and syntax highlighting (as well as email, > news-reading, doctor...) of (X)Emacs. >=20 > -- MarcusArticle: 103728
I want to use a Spartan II chip to drive two ADCs. The ADC spec says that the input current on the SCLK pin is +/-0.5uA max and 10nA typically. Similary the input current on the CS pin is 10nA typically. The absolute maximum ratings for the same ADC state that the maximum input current to any pins (except supplies) is +/-10mA. I'm using the LVTTL standard and can only specify the drive current to a minimum of 2mA. Will I be doing the ADCs potential damage if I specify 2mA to drive the SCLK and CS pins? Thanks, MeesArticle: 103729
Mees, don't worry about the currents, just make sure that the voltage ramges for FPGA and ADC are compatible. Peter Alfke, Xilinx ======= m_oylulan@hotmail.com wrote: > I want to use a Spartan II chip to drive two ADCs. The ADC spec says > that the input current on the SCLK pin is +/-0.5uA max and 10nA > typically. Similary the input current on the CS pin is 10nA typically. > The absolute maximum ratings for the same ADC state that the maximum > input current to any pins (except supplies) is +/-10mA. I'm using the > LVTTL standard and can only specify the drive current to a minimum of > 2mA. Will I be doing the ADCs potential damage if I specify 2mA to > drive the SCLK and CS pins? > > Thanks, > MeesArticle: 103730
Mees, Current only makes sense when there is a path for it. In your case the current will go through the input impedance of your ADC. The extremely small current value given in its datasheet (10nA typically) is essentially leakage current typical for high-impedance CMOS inputs. Thus, since the input impedance is high you will never see anything close to absolute limits of the chip pretty much regardless of the drive strength you choose. The drive strength only tells you how much current a driver CAN drive while keeping the output voltage range in spec. If there is no load, there is current. /Mikhail <m_oylulan@hotmail.com> wrote in message news:1149870335.699238.81850@f6g2000cwb.googlegroups.com... > I want to use a Spartan II chip to drive two ADCs. The ADC spec says > that the input current on the SCLK pin is +/-0.5uA max and 10nA > typically. Similary the input current on the CS pin is 10nA typically. > The absolute maximum ratings for the same ADC state that the maximum > input current to any pins (except supplies) is +/-10mA. I'm using the > LVTTL standard and can only specify the drive current to a minimum of > 2mA. Will I be doing the ADCs potential damage if I specify 2mA to > drive the SCLK and CS pins? > > Thanks, > Mees >Article: 103731
Subroto Datta napisał/a: > AHDL support will be there in Quartus for a long long time.The AHDL > language, is fully maintained and supported for reasons of backwards > compatibility. There are lots of legacy Max+Plus II designs which > customers are migrating to Quartus for use in both existing and new > projects. We are sensitive to our customers needs and will not do > anything to jeopardize their productivity. Is backward compatibility the only reason why Altera keeps AHDL in Quartus? Which languages Altera suggests to use in new projects? czerstwyArticle: 103732
hello i built on myself a cable 3 interface,following the xilinx drawing,i checked in all the possible ways,ohmically,injecting square waves,and then once connected tho the parallel port i used the option in the Jtag programmer utility that allows to force level on tdi,sending n clock pulses and so on,these signals are present on the pins of the fpga and the cable is connected to the supply(5V),but the pc doesn't see the cable at all please,anyone can help me?thanks!Article: 103733
> > Is backward compatibility the only reason why Altera keeps AHDL in > Quartus? Which languages Altera suggests to use in new projects? > > czerstwy You would never want to start a new project in an obsolete language like AHDL or ABEL. Verilog and VHDL are the only reasonable choices for new designs, personally I use Verilog but I don't want to start a religious war so lets just say both of those languages are industry standards and that code written in either can be easily ported to anybody's FPGA or ASIC.Article: 103734
Hi, I am a student,I am new in VHDL and want to implement a project. I am working on VHDL with Actel Libero. In my previous implementation, I have used the "RAMB4_S1_S1"(4K-Bit Data Dual Port Block RAM) and "RAMB4_S1"(4K-Bit Data Single Port Block RAM) which are implemented in the "UNISIM" in Xilinx. Could you please provide me with the information of an equivalent library that implement these RAMs in Actel Libero ? Thanks in advance Best regardsArticle: 103735
Alan Nishioka wrote: > eascheiber@yahoo.com wrote: > >>just one question, in xtime_l.c XTime_GetTime function shouldn't use >>mftb instead of mfspr. It does not seem to work ok /w mfspr. > > > That's odd. It does look like XTime_GetTime *should* be using mftb. > But the mfspr code works fine for me (EDK6.1, EDK7.1, EDK8.1). > > Alan Nishioka > Time Base Register is just another special purpose register. From the documentation it looks like mftb provides read access to non privileged code. mfspr should work as long as you are running privileged code..which is the case with most simple apps. I haven't verified this though. -SivaArticle: 103736
I would suggest VHDL as a replacement for AHDL as the two are similar. Simon "Josh Rosen" <bjrosen@polybusPleaseDontSPAMme.com> wrote in message news:pan.2006.06.09.19.35.20.613577@polybusPleaseDontSPAMme.com... > > > > Is backward compatibility the only reason why Altera keeps AHDL in > > Quartus? Which languages Altera suggests to use in new projects? > > > > czerstwy > > You would never want to start a new project in an obsolete language like > AHDL or ABEL. Verilog and VHDL are the only reasonable choices for new > designs, personally I use Verilog but I don't want to start a religious > war so lets just say both of those languages are industry standards and > that code written in either can be easily ported to anybody's FPGA or ASIC. > > >Article: 103737
"radarman" <jshamlet@gmail.com> wrote in message news:1149698107.233187.12590@u72g2000cwu.googlegroups.com... > John Smith wrote: > > Seemed like a good deal, but the board was only around for purchase a few > Have you tried searching on the Xilinx website. I was able to find: > > http://www.xilinx.com/products/boards/sp305/reference_designs.htm > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SP305-US&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS > > Between the two, there are reference designs (with working UCF files), > schematics, and a user guide. > > -Seth Thanks for the tips, I will check it out. It seems kind'a strange to me though that Xilinx is discontinuing this board after a few months on the market ? Why is that ?Article: 103738
> > Have you tried searching on the Xilinx website. I was able to find: > > http://www.xilinx.com/products/boards/sp305/reference_designs.htm > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SP305-US&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS > > Between the two, there are reference designs (with working UCF files), > schematics, and a user guide. > Well, I've checked it out now, and I have downloaded all this stuff before, so nothing new. In fact, I had to make my own "master" UCF-file for this board. Maybe there are some hidden treasures in the EDK files, but I'm only using ISE. And Xilinx does not offer any customer support either. Not a good way to treat future customers.Article: 103739
John, It is listed as out of stock. How does that equate to discontinued? I think I missed something. AustinArticle: 103740
"blisca" <blisca@tiscali.it> wrote in message news:4489bd31$0$18288$4fafbaef@reader1.news.tin.it... > hello > i built on myself a cable 3 interface,following the xilinx drawing,i checked > in all the possible ways,ohmically,injecting square waves,and then once > connected tho the parallel port i used the option in the Jtag programmer > utility that allows to force level on tdi,sending n clock pulses and so > on,these signals are present on the pins of the fpga and the cable is > connected to the supply(5V),but the pc doesn't see the cable at all > please,anyone can help me?thanks! > Try the different BIOS setup options on your computer for the port in question. It worked wonders for me, but that was a Parallel IV cable. When it was set to ECP-mode, everything worked so much better.Article: 103741
Commercial advertising are still banned on news, right ? "John Adair" <g1@enterpoint.co.uk> wrote in message news:1149708569.253658.305870@c74g2000cwc.googlegroups.com... > John > > What are your requirements for a board? We can match the XC3S1500 on a > number of our products just a question of what else you want on board. > Have a look at our University Access program for discounts etc. Click > the big green square on top right of our root page for details or > directly at http://www.enterpoint.co.uk/uap/uap.html. > > John Adair > Enterpoint Ltd. > > > John Smith wrote: > > Seemed like a good deal, but the board was only around for purchase a few > > months, so I guess there aren't to many around ? Thats a shame, really ! It > > is as far as I can tell a good board, It has a good an powerfull FPGA; > > Spartan 3-1500 and enough power to fullfill the requirements of my masters > > degree. But the board are no longer available ? I was kind'a hoping > > draining knowledge from other users of this board... >Article: 103742
"Austin Lesea" <austin@xilinx.com> wrote in message news:e6cs9c$7bn18@xco-news.xilinx.com... > John, > > It is listed as out of stock. > > How does that equate to discontinued? > > I think I missed something. > The board is listed as "no longer available". So you missed something, yes ! A fundamental knowledge of the english language....Article: 103743
What about the ML401. It's about the same price. You get a Virtex 4 instead of the Spartan 3. The peripherals look about the same. The LX25 is a little smaller than the S3-1500, but not tons smaller and it's still supported by webpack. -Arlen John Smith wrote: > "Austin Lesea" <austin@xilinx.com> wrote in message > news:e6cs9c$7bn18@xco-news.xilinx.com... > > John, > > > > It is listed as out of stock. > > > > How does that equate to discontinued? > > > > I think I missed something. > > > The board is listed as "no longer available". > > So you missed something, yes ! A fundamental knowledge of the english > language....Article: 103744
"Austin Lesea" <austin@xilinx.com> wrote in message news:e6cs9c$7bn18@xco-news.xilinx.com... > John, > > It is listed as out of stock. > > How does that equate to discontinued? > > I think I missed something. > > Austin Well, Austin deare, I did not meen to be rude, but when I buy hardware for about $400, it would be very nice to have an e-mail address to post simple questions, an get some answers to. Thats not to much to ask for. It's kind'a like the ultimatium the US ambassador in Norway has given us: Either you are with us, or you are against us ! (He IS a fool !) I would not put it quite like that, I would say; I you dont offer propper support, you will loose me as a customer. Maybe you'll regret that some time. Remenber the first days of The Beatles ? I'll always manage. I'll just switch to one of Xilinxs competitors.Article: 103745
There is a tool called SmartGen that you can use to generate memories for Actel devices. It is part of your Libero installation. irfan.mohammed@gmail.com wrote: > Hi, > > I am a student,I am new in VHDL and want to implement a project. I am > working on VHDL with Actel Libero. In my previous implementation, I > have used the "RAMB4_S1_S1"(4K-Bit Data Dual Port Block RAM) and > "RAMB4_S1"(4K-Bit Data Single Port Block RAM) which are implemented in > the "UNISIM" in Xilinx. > Could you please provide me with the information of an equivalent > library that implement these RAMs in Actel Libero ? > > Thanks in advance > > Best regardsArticle: 103746
Hello,
I have two questions that hopefully someone will be able to provide some
info on>
1. Has anyone developed a custom embedded PowerPC system for a card
other than the demo boards available from vendors like Avnet, Xilinx, etc.
I have a pmc module with 128 MB of DDR SDRAM and 6 MB of QDRAM.
It has a VirtexPro XC2PV70 on it also. I'd like to use EDK to
test a ppc implementation on that card. I have vendor specific
VHDL that allows me to read and write the memories but the code does not
instantiate the Power PC. I want to replace their library with cores from
the EDK to read and write the memory from the PPC and do some basic I/O
under control of the PPC.
2. In EDK version 8.102i, when I try to select the Generic DDR
controller in the base system builder the "Add devices" button of the GUI
disappears and I can not add any more devices. If I add a UART or other
device it seems to work ok. I have 7.1 installed on another pc and when I
selected the Generic DDR controller it all seemed to work ok. I haven't
contacted Xilinx about this yet. Has anyone else noticed this bug?
Any input is appreciated,
Thanks,
CTW
Article: 103747John Smith <someone@microsoft.com> wrote in message e6cskr$ofc$2@readme.uio.no... > > "blisca" <blisca@tiscali.it> wrote in message > news:4489bd31$0$18288$4fafbaef@reader1.news.tin.it... > > hello > > i built on myself a cable 3 interface,following the xilinx drawing,i > checked > > in all the possible ways,ohmically,injecting square waves,and then once > > connected tho the parallel port i used the option in the Jtag programmer > > utility that allows to force level on tdi,sending n clock pulses and so > > on,these signals are present on the pins of the fpga and the cable is > > connected to the supply(5V),but the pc doesn't see the cable at all > > please,anyone can help me?thanks! > > > > Try the different BIOS setup options on your computer for the port in > question. It worked wonders for me, but that was a Parallel IV cable. When > it was set to ECP-mode, everything worked so much better. > > despite here in italy are 1:45 a.m. i want to follow your hint,stay tuned and thank youArticle: 103748
"gallen" <arlencox@gmail.com> wrote in message news:1149896992.818022.324140@y43g2000cwc.googlegroups.com... > What about the ML401. It's about the same price. You get a Virtex 4 > instead of the Spartan 3. The peripherals look about the same. The > LX25 is a little smaller than the S3-1500, but not tons smaller and > it's still supported by webpack. Ok, but my point is that 1: Xilinx does not offer any customer support. 2: Xilinx does not offer any customer support. 3: Xilinx does not offer any customer support. I'ts impossiblle to get hold of the guys ! Even simple guestion ! NO saupport e-mail. NO support phone ? What am I supposed to do ? Write a letter to Georg Dobbeltv Busk ? Maybe thats a good idea ! That way I can tell him what a crappy ambassador he has sent us ! I want the old one back. He understood the close relatisonship between our to nations. The new one, with his speaches about chosing sides, will only feed the left wing and communists. USA should never need to question our loyalti, but when the US ambassador does that in a public speech, I feel hurt, and I know most Norwegians does. Thats why I call him a fool.Article: 103749
John Smith wrote: > "gallen" <arlencox@gmail.com> wrote in message > news:1149896992.818022.324140@y43g2000cwc.googlegroups.com... >> What about the ML401. It's about the same price. You get a Virtex 4 >> instead of the Spartan 3. The peripherals look about the same. The >> LX25 is a little smaller than the S3-1500, but not tons smaller and >> it's still supported by webpack. > > Ok, but my point is that > 1: Xilinx does not offer any customer support. > 2: Xilinx does not offer any customer support. > 3: Xilinx does not offer any customer support. > > I'ts impossiblle to get hold of the guys ! Even simple guestion ! > NO saupport e-mail. NO support phone ? What am I supposed to do ? I would suggest that you try http://support.xilinx.com Right at the top you will see a tab labeled "Contact Support" where you can follow the links to file a WebCase on your issue or to get the phone number for technical support as well. In additional to our official support channels we also monitored this newsgroup for issues. To claim that Xilinx does not offer any customer support is a bit of hyperbole. Ed McGettigan -- Xilinx Inc.
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