Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 88425

Article: 88425
Subject: Re: Fastest way to compute floating point log and exp
From: Eric Smith <eric@brouhaha.com>
Date: 17 Aug 2005 18:46:33 -0700
Links: << >>  << T >>  << A >>
Marc Battyani wrote:
> at cordic at a glance, but it looks slower or bigger if totally unrolled.

Kolja Sulimma wrote:
> Why would you want to unroll it?

Higher data throughput.  It's more efficient to unroll it than to
instantiate multiple copies because the stages of the unrolled version
use fixed shifts (just wiring) rather than barrel shifters.


Article: 88426
Subject: Re: super fast divide-by-N
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 18 Aug 2005 13:47:49 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> I have been told that Virtex ( II to 4) the DCMs can divide down from a
> GHz, if you use the divide-by-two prescle option in the DCM. That means
> the DCM really runs on 500 MHz, which it is specified to do.

Interesting - is that DIV 2 in the IO area, or in the DCM itself - in
which case, are there pin restrictions to drive at 1GHz ?

> Division ( even combined multiply/divide) with numbers up to 32 is no
> problem. You can multiply 500 MHz by 7 and divide by 27 (if those are
> your numbers). The virtual 3.5 GHz are not really being generated, it's
> all mathematical trickery. :-)

What jitter spec, would the DCM give ?
assume sub 100MHz out, and 1GHz sub ps jitter IP .

> For finer granularity, you can use DDS phase accumulators which,
> however, generate som jitter (+ or - half a clock period).
> Peter Alfke, Xilinx Applications

-jg



Article: 88427
Subject: Re: Digilent's JTAG-USB cable with chipscope
From: Eric Smith <eric@brouhaha.com>
Date: 17 Aug 2005 18:58:20 -0700
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@openchip.org> writes:
> Yes, it looks like Xilinx is trying to make money on the over priced USB
> Cable, that doesnt work very good.

Did you mean that the cable doesn't work very well, or that trying to
make money on it doesn't work very well?  I hope you meant the latter,
since I'm considering buying one.

> UUPS! I made a mistake - the USB cable is $149 not 495, so its not so bad
> deal at all.

Seems not completely unreasonable.

Eric

Article: 88428
Subject: Re: Xilinx ISE on remtoe Display
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: Thu, 18 Aug 2005 00:11:19 -0400
Links: << >>  << T >>  << A >>
> I've got X11 forwarding over SSH working fine. but for some reason the
> project navigator just will not display.

I have a FC3 desktop and am able to run ise from a RHEL3.0 server and
forward it to my desktop. I use "ssh -Y". If ssh doesn't work for you, you
can always use vncserver/vncviewer combination.

HTH,
Jim




Article: 88429
Subject: [Q] Synthesis : HowTo Preserve FSM encodings
From: Markus Meng <meng.engineering@bluewin.ch>
Date: Thu, 18 Aug 2005 09:36:52 +0200
Links: << >>  << T >>  << A >>
Hi all,

I just wonder if there is a possibility to add a constraint
on the RTL level (VHDL/Verilog) to make shure that a
specific state machine encoding for a particular module/entity
is not changed/optimized?

Is this possible, if for the overall design the synthesis tool
is given the freedom to do at is best, and therefore maybe
re-arrange state vector encoding.

I'am interested for the tools XST from Xilinx, but also others
from Synplicity, Mentor etc.

Best Regards
Markus

----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==----
http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups
----= East and West-Coast Server Farms - Total Privacy via Encryption =----

Article: 88430
Subject: Re: Problem with quartus 5.0 sp1
From: czerstwy <czebaka@o2.pl>
Date: Thu, 18 Aug 2005 09:37:26 +0200
Links: << >>  << T >>  << A >>
Subroto Datta wrote:
> Is there a Mysupport service request number on this? Also please send

I don't see anything like this.

> me a project archive of your design so that we can reproduce the
> problem in house.

I did some more test and now I know whats the problem. I created 
lpm_ram_dp as synchronous, but i overlook connecting few clocks. 
Compiler for Acex family don't recognize this situation as ahdl error in 
Analysis and Synthesis stage and successfully goes through this and 
fitting stage. When I change device family to Flex10k and started 
compilation, error was reported at the first stage in 
Messages->Processing window and  report said that I've got some clocks 
input not connected.

Thanks and Best Regards
czerstwy

Article: 88431
Subject: Re: Modelsim on a remote display
From: "Marco" <marcotoschi@nospam.it>
Date: Thu, 18 Aug 2005 09:55:10 +0200
Links: << >>  << T >>  << A >>

"unfrostedpoptart" <david@therogoffs.com> wrote in message 
news:1124308524.499740.121800@f14g2000cwb.googlegroups.com...
> vnc (lots of versions - I use UltraVNC -
> http://ultravnc.sourceforge.net/)
>

It works, but in this way none can open a session into pc with vnc server. 
The pc with vnc server should not be locked for the only vnc client.
Local sessions should be possible.

Another way?

Many Thanks
Marco 



Article: 88432
Subject: Re: Evolutionary VHDL code example
From: apsolar@rediffmail.com
Date: 18 Aug 2005 01:11:36 -0700
Links: << >>  << T >>  << A >>
Hi Andrew
I have read a lot of conference papers on Evolvable Hardware. They
always mention about the implementation but i couldn't find any
examples. So its like I have a vague idea about this but I need to see
it in reality to try something myself.

Ankit


Article: 88433
Subject: Re: Chipscope pro : timing constraint?
From: "Pasacco" <pasacco@gmail.com>
Date: 18 Aug 2005 01:18:40 -0700
Links: << >>  << T >>  << A >>
Yes, it is correct.

In ILA, we can see the transition of the signal in a cycle accurate
manner.

BTW, What I want to see in ILA , in the example above, is

'counter' signal change (0 -> 1 -> 2 -> 3 -> 4 ) part.

Those transitions occur during the first 4 clock cycles, after (rst='0'
and en='1').

In my exercise, I do not see them. I only see the value '4', whih is
the last value.

Is it possible to see, in ILA, those signal transition behaviors in the
example above?


Article: 88434
Subject: Re: Synthesis : HowTo Preserve FSM encodings
From: "Neo" <zingafriend@yahoo.com>
Date: 18 Aug 2005 02:04:51 -0700
Links: << >>  << T >>  << A >>
sure thats should be possible. there is something called as a
dont_touch attribute which you should look for.


Article: 88435
Subject: Re: Spartan-3 configuration -- peculiar problem
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 18 Aug 2005 02:31:03 -0700
Links: << >>  << T >>  << A >>
<ScreamingFPGA@yahoo.com> wrote in message 
news:1124328260.084464.275430@g44g2000cwa.googlegroups.com...
>
> The old Volvo 240's had a 'Bulb Failure Warning Light' on the
> dashboard. But what about the case where that bulb failed? Oh no!
> Infinite recursion...
>
Luckily, in all the cars I've had, the warning bulbs all come on briefly as 
you turn on the ignition. This way you know if they're working or not!
Cheers, Syms. 



Article: 88436
Subject: Re: Modelsim on a remote display
From: Sylvain Munaut <com.246tNt@tnt>
Date: Thu, 18 Aug 2005 11:38:06 +0200
Links: << >>  << T >>  << A >>
Marco wrote:
> "unfrostedpoptart" <david@therogoffs.com> wrote in message 
> news:1124308524.499740.121800@f14g2000cwb.googlegroups.com...
> 
>>vnc (lots of versions - I use UltraVNC -
>>http://ultravnc.sourceforge.net/)
>>
> 
> 
> It works, but in this way none can open a session into pc with vnc server. 
> The pc with vnc server should not be locked for the only vnc client.
> Local sessions should be possible.
> 
> Another way?
> 
> Many Thanks
> Marco 
> 
> 

Windows remote desktop ? I think that's included in WXP Pro no ?

Article: 88437
Subject: Re: Xilinx ISE on remtoe Display
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Thu, 18 Aug 2005 11:15:28 +0100
Links: << >>  << T >>  << A >>
Jim Wu wrote:
> I use "ssh -Y". If ssh doesn't work for you, you
> can always use vncserver/vncviewer combination.

I had both 'X11 forwarding' and 'trusted X11 forwarding' enabled on a 
perhost basis in my ~/.ssh/config file, so that avoids the need for -X 
or -Y.

The thing that really confused/frustrated me though was that other 
applications happily displayed remotely. xclock, even coregen and 
floorplanner would pop-up, but the Project manager does nothing. Very odd.

Although VNC is a great tool, it is a little slow, and I've got 
everything working by opening up the X server and using xauth. Thanks 
for the suggestion though.

Andy

-- 
Dr. Andrew Greensted      Department of Electronics
Bio-Inspired Engineering  University of York, YO10 5DD, UK

Tel: +44(0)1904 432379    Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224    Web: www.bioinspired.com/users/ajg112

Article: 88438
Subject: Re: Synthesis : HowTo Preserve FSM encodings
From: Alex <al.lopich@gmail.com>
Date: Thu, 18 Aug 2005 11:40:23 +0100
Links: << >>  << T >>  << A >>
It is possible.
Check the constrain documentation. In XILINX the constrain called (if i am  
not mistaken)
something like  FSM_coding or similar.

-- 
Alex

Article: 88439
Subject: Re: Problem with quartus 5.0 sp1
From: Sylvain Munaut <com.246tNt@tnt>
Date: Thu, 18 Aug 2005 13:17:05 +0200
Links: << >>  << T >>  << A >>
czerstwy wrote:
> Hello
> 
> I've got problem with Quartus 5.0 with Service Pack 1. Problem occurs in
> compilation process after fitting. When assembling is at 47% I get
> 'Quartus II Internal Error' which says:
> 
> 'Internal Error: Sub-system: ASM, File: asm_ram_model_base.cpp, Line: 3430
> clock_is_used == clock_found
> Quartus II Version 5.0 Build 168 06/22/2005 SJ Web Edition
> Service Pack Installed:  1'
> 
> I used to get this kind of errors earlier in this and previous versions
> of Quartus, but restarting Quartus or computer was always a solution.
> 
> Project is for Acex EP1K30 device and contains 2 lpm_ram_dp megafunctions.
> 
> Can anyone give me directions what can cause this kind of problems?

Last time I got an "Internal Error" with quartus, it just didn't like
the name of one of my signal ... I just changed the name to another name
and it worked. Changing it back made it crash again so that was _really_
the name of the signal.

To 'isolate' the problem, I synthetized my project piece by piece,
sub-module by sub-module to isolate the source file that made him crash.


	Sylvain

Article: 88440
Subject: Re: Easy USB2.0 hi-speed device solutions ?
From: "Gregory C. Read" <readgc.invalid@hotmail.com.invalid>
Date: Thu, 18 Aug 2005 07:34:44 -0400
Links: << >>  << T >>  << A >>
You can definitely find a cheaper solution, but for a "1-off project", you
won't find an easier one.  I just finished a project using it and the time
saved in software will more than pay for the module.

BTW, if you went into a higher volume project, you can buy only the firmware
chip from them and put the components on your board at a fraction the cost.

-- 
Greg
readgc.invalid@hotmail.com.invalid
(Remove the '.invalid' twice to send Email)


"Mike Harrison" <mike@whitewing.co.uk> wrote in message
news:i326g15o5vohtc4102td43lmdcsi5ejceg@4ax.com...
> I'm looking for an easy-to-use USB2.0 hi-speed device solution with the
minimum of software work
> required to get a lot of data from a device into a PC.
>
> I've found https://www.quickusb.com/ which looks to be exactly what I
want, providing DLL calls to
> use at the PC end to get chunks of data, but it seems somewhat expensive
($150), especially with
> their connector break-out board ($79 for a PCB with 5 connectors on it!)
>
> If that's the only thing around, I'll use it, but was wondering if anyone
knows of anything similar
> that would be worth a look (lower priced would be nice..)
>
> Also, does anyone have any feedback on this product & the company ( can't
say I'm impressed so far
> after emailing an ordering enquiry 2 days ago with no reply yet...).
> This is initially for a 1-off project, but as I may well need USB2 for
future production projects,
> it would be useful to get familiar with something that had a price more
viable for production use.



Article: 88441
Subject: Re: Modelsim on a remote display
From: "Marco" <marcotoschi@nospam.it>
Date: Thu, 18 Aug 2005 13:44:46 +0200
Links: << >>  << T >>  << A >>

"Sylvain Munaut" <com.246tNt@tnt> wrote in message 
news:430456bb$0$345$ba620e4c@news.skynet.be...
> Marco wrote:
>> "unfrostedpoptart" <david@therogoffs.com> wrote in message
>> news:1124308524.499740.121800@f14g2000cwb.googlegroups.com...
>>
>>>vnc (lots of versions - I use UltraVNC -
>>>http://ultravnc.sourceforge.net/)
>>>
>>
>>
>> It works, but in this way none can open a session into pc with vnc 
>> server.
>> The pc with vnc server should not be locked for the only vnc client.
>> Local sessions should be possible.
>>
>> Another way?
>>
>> Many Thanks
>> Marco
>>
>>
>
> Windows remote desktop ? I think that's included in WXP Pro no ?

I have tried it, but there some troubles with license.

When I try to open modelsim into the remote desktop, I receive an error 
message about license.




Article: 88442
Subject: Re: Modelsim on a remote display
From: "Jon Beniston" <jon@beniston.com>
Date: 18 Aug 2005 05:56:02 -0700
Links: << >>  << T >>  << A >>
You can have local sessions with RealVNC. In fact you can have the
local user and remote user battle for control of the mouse if you
really want.

http://www.realvnc.com/

Cheers,
Jon


Article: 88443
Subject: State Machine and BUFG
From: "Marco" <marcotoschi@nospam.it>
Date: Thu, 18 Aug 2005 15:07:00 +0200
Links: << >>  << T >>  << A >>
Hallo,
I have made a state machine. When I synthetize it, XST adds lots of BUFG to 
states.

My code:

type state_type is ( seq_daq_state_1, seq_daq_state_2, seq_daq_state_3, 
seq_daq_state_4, seq_daq_state_5, seq_daq_state_6, seq_daq_state_7, 
seq_daq_state_8, seq_daq_state_9, seq_daq_state_10, seq_daq_state_11, 
seq_daq_state_12, seq_daq_state_13, seq_daq_state_14, seq_daq_state_15, 
seq_daq_state_16, seq_daq_state_17 );

signal seq_daq_state, seq_daq_next_state : state_type;



Here the log:

---------------------------------------------+---------------------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

---------------------------------------------+---------------------------------------+-------+

USER_LOGIC_I__n0065(USER_LOGIC_I__n00651:O) | 
NONE(*)(USER_LOGIC_I_rx_data_received)| 1 |

USER_LOGIC_I__n0064(USER_LOGIC_I__n00641:O) | 
NONE(*)(USER_LOGIC_I_interrupt_0) | 1 |

OPB_Clk | BUFGP | 237 |

USER_LOGIC_I_Clk_Spi_I_prescaler_out:Q | BUFG | 7 |

USER_LOGIC_I_tx_state_FFd2:Q | NONE | 1 |

USER_LOGIC_I__n0062(USER_LOGIC_I__n00621:O) | 
NONE(*)(USER_LOGIC_I_interrupt_1) | 1 |

USER_LOGIC_I__n0221(USER_LOGIC_I__n0221183:O)| 
NONE(*)(USER_LOGIC_I_Adc_Mux_0) | 3 |

USER_LOGIC_I__n0060(USER_LOGIC_I__n00601:O) | NONE(*)(USER_LOGIC_I_Spi_Ss_0) 
| 1 |

USER_LOGIC_I__n0059(USER_LOGIC_I__n00591:O) | 
NONE(*)(USER_LOGIC_I_interrupt_2) | 1 |

USER_LOGIC_I__n0058(USER_LOGIC_I__n00581:O) | NONE(*)(USER_LOGIC_I_Spi_Ss_1) 
| 2 |

USER_LOGIC_I__n0057(USER_LOGIC_I__n00571:O) | 
NONE(*)(USER_LOGIC_I_interrupt_3) | 1 |

USER_LOGIC_I__n0056(USER_LOGIC_I__n00561:O) | 
NONE(*)(USER_LOGIC_I_interrupt_4) | 1 |

USER_LOGIC_I__n0055(USER_LOGIC_I__n00551:O) | 
NONE(*)(USER_LOGIC_I_interrupt_5) | 1 |

USER_LOGIC_I__n0054(USER_LOGIC_I__n00541:O) | 
NONE(*)(USER_LOGIC_I_interrupt_6) | 1 |

USER_LOGIC_I__n0053(USER_LOGIC_I__n00531:O) | 
NONE(*)(USER_LOGIC_I_interrupt_7) | 1 |

USER_LOGIC_I__n0052(USER_LOGIC_I__n00521:O) | 
NONE(*)(USER_LOGIC_I_tx_shift_enable) | 1 |

USER_LOGIC_I__n0051(USER_LOGIC_I__n00511:O) | 
NONE(*)(USER_LOGIC_I_rx_shift_enable) | 1 |

USER_LOGIC_I_seq_daq_state_FFd17:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd15:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd13:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd11:Q | NONE | 16 |

USER_LOGIC_I_seq_daq_state_FFd9:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd7:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd5:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd3:Q | NONE | 16 |

---------------------------------------------+---------------------------------------+-------+

(*) These 14 clock signal(s) are generated by combinatorial logic,

and XST is not able to identify which are the primary clock signals.

Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) 
generated by combinatorial logic.

INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically 
buffered by XST with BUFG/BUFR resources. Please use the buffer_type 
constraint in order to insert these buffers to the clock signals to help 
prevent skew problems.



In this way my project is overmapped, because it uses 10 GCLK.

In what way could I resolve this trouble?

There is a way to substitute BUFG with IBUF, in example?



Article: 88444
Subject: Re: State Machine and BUFG
From: Sean Durkin <smd@despammed.com>
Date: Thu, 18 Aug 2005 15:17:44 +0200
Links: << >>  << T >>  << A >>
Marco wrote:
> Hallo, I have made a state machine. When I synthetize it, XST adds
> lots of BUFG to states.
> 
> My code:
> 
> type state_type is ( seq_daq_state_1, seq_daq_state_2,
> seq_daq_state_3, seq_daq_state_4, seq_daq_state_5, seq_daq_state_6,
> seq_daq_state_7, seq_daq_state_8, seq_daq_state_9, seq_daq_state_10,
> seq_daq_state_11, seq_daq_state_12, seq_daq_state_13,
> seq_daq_state_14, seq_daq_state_15, seq_daq_state_16,
> seq_daq_state_17 );
> 
> signal seq_daq_state, seq_daq_next_state : state_type;
Relevant is the code where you USE these signals. Obviously there's
something wrong there.

BUFGs are inserted because XST has detected that some state signals are
connected to clock inputs of Flipflops or other clocked components,
hence it derives that these signals must be clocks.

I suggest you post a code snippet from your state machine, something's
odd there.

cu,
Sean

Article: 88445
Subject: Re: State Machine and BUFG
From: "Marco" <marcotoschi@nospam.it>
Date: Thu, 18 Aug 2005 15:23:38 +0200
Links: << >>  << T >>  << A >>
  SEQ_DAQ_SYNC_PROC: process ( BUS2IP_Clk, BUS2IP_Reset ) is
  begin

    if ( BUS2IP_Reset = '1' ) then
      seq_daq_state <= seq_daq_state_1;
    elsif ( BUS2IP_Clk'event and BUS2IP_Clk = '1' ) then
         seq_daq_state <= seq_daq_next_state;
    end if;

  end process;


  SEQ_DAQ_OUTPUT_DECODE: process ( seq_daq_state, mux_channel, 
seq_data_received ) is
  begin

    case ( seq_daq_state ) is

      when seq_daq_state_1 =>
          -- STATO DI IDLE
          interrupt <= (others => '0');

      when seq_daq_state_2 =>
      if ( mux_channel(0) = '1' ) then
            Adc_Mux <= "000";
    end if;

      when seq_daq_state_3 =>
          Adc_Mux <= "000";
    if ( seq_data_received = '1' ) then
      slv_reg1 <= rx_register_out;
    interrupt(0) <= '1';
    else
    interrupt(0) <= '0';
    end if;

      when seq_daq_state_4 =>
      if ( mux_channel(1) = '1' ) then
            Adc_Mux <= "001";
    end if;

      when seq_daq_state_5 =>
          Adc_Mux <= "001";
    if ( seq_data_received = '1' ) then
      slv_reg2 <= rx_register_out;
    interrupt(1) <= '1';
    else
    interrupt(1) <= '0';
    end if;

      when seq_daq_state_6 =>
      if ( mux_channel(2) = '1' ) then
            Adc_Mux <= "010";
    end if;

      when seq_daq_state_7 =>
          Adc_Mux <= "010";
    if ( seq_data_received = '1' ) then
      slv_reg3 <= rx_register_out;
    interrupt(2) <= '1';
    else
    interrupt(2) <= '0';
    end if;

      when seq_daq_state_8 =>
      if ( mux_channel(3) = '1' ) then
            Adc_Mux <= "011";
    end if;

      when seq_daq_state_9 =>
          Adc_Mux <= "011";
    if ( seq_data_received = '1' ) then
      slv_reg4 <= rx_register_out;
    interrupt(3) <= '1';
    else
    interrupt(3) <= '0';
    end if;

      when seq_daq_state_10 =>
      if ( mux_channel(4) = '1' ) then
            Adc_Mux <= "100";
    end if;

      when seq_daq_state_11 =>
          Adc_Mux <= "100";
    if ( seq_data_received = '1' ) then
      slv_reg5 <= rx_register_out;
    interrupt(4) <= '1';
    else
    interrupt(4) <= '0';
    end if;

      when seq_daq_state_12 =>
      if ( mux_channel(5) = '1' ) then
            Adc_Mux <= "101";
    end if;

      when seq_daq_state_13 =>
          Adc_Mux <= "101";
    if ( seq_data_received = '1' ) then
      slv_reg6 <= rx_register_out;
    interrupt(5) <= '1';
    else
    interrupt(5) <= '0';
    end if;

      when seq_daq_state_14 =>
      if ( mux_channel(6) = '1' ) then
            Adc_Mux <= "110";
    end if;

      when seq_daq_state_15 =>
          Adc_Mux <= "110";
    if ( seq_data_received = '1' ) then
      slv_reg7 <= rx_register_out;
    interrupt(6) <= '1';
    else
    interrupt(6) <= '0';
    end if;

      when seq_daq_state_16 =>
      if ( mux_channel(7) = '1' ) then
            Adc_Mux <= "111";
    end if;

      when seq_daq_state_17 =>
          Adc_Mux <= "111";
    if ( seq_data_received = '1' ) then
      slv_reg8 <= rx_register_out;
    interrupt(7) <= '1';
    else
    interrupt(7) <= '0';
    end if;

  when others =>
      null;

  end case;

  end process;


  SEQ_DAQ_NEXT_STATE_DECODE: process ( seq_daq_state, spi_rx_active, 
mux_channel, seq_data_received ) is
  begin

    seq_daq_next_state <= seq_daq_state;  --default is to stay in current 
state
    case ( seq_daq_state ) is
      when seq_daq_state_1 =>
    if ( spi_rx_active = '1' ) then
            seq_daq_next_state <= seq_daq_state_2;
    else
            seq_daq_next_state <= seq_daq_state_1;
    end if;

      when seq_daq_state_2 =>
      if ( mux_channel(0) = '1' ) then
            seq_daq_next_state <= seq_daq_state_3;
    else
            seq_daq_next_state <= seq_daq_state_4;
    end if;

      when seq_daq_state_3 =>
    if (  seq_data_received = '1' ) then
    seq_daq_next_state <= seq_daq_state_4;
    else
    seq_daq_next_state <= seq_daq_state_3;
    end if;

      when seq_daq_state_4 =>
      if ( mux_channel(1) = '1' ) then
            seq_daq_next_state <= seq_daq_state_5;
    else
            seq_daq_next_state <= seq_daq_state_6;
    end if;

      when seq_daq_state_5 =>
    if ( seq_data_received = '1' ) then
    seq_daq_next_state <= seq_daq_state_6;
    else
    seq_daq_next_state <= seq_daq_state_5;
    end if;

      when seq_daq_state_6 =>
      if ( mux_channel(2) = '1' ) then
            seq_daq_next_state <= seq_daq_state_7;
    else
            seq_daq_next_state <= seq_daq_state_8;
    end if;

      when seq_daq_state_7 =>
    if (  seq_data_received = '1' ) then
    seq_daq_next_state <= seq_daq_state_8;
    else
    seq_daq_next_state <= seq_daq_state_7;
    end if;

      when seq_daq_state_8 =>
      if ( mux_channel(3) = '1' ) then
            seq_daq_next_state <= seq_daq_state_9;
    else
            seq_daq_next_state <= seq_daq_state_10;
    end if;

      when seq_daq_state_9 =>
    if (  seq_data_received = '1' ) then
    seq_daq_next_state <= seq_daq_state_10;
    else
    seq_daq_next_state <= seq_daq_state_9;
    end if;

      when seq_daq_state_10 =>
      if ( mux_channel(4) = '1' ) then
            seq_daq_next_state <= seq_daq_state_11;
    else
            seq_daq_next_state <= seq_daq_state_12;
    end if;

      when seq_daq_state_11 =>
    if (  seq_data_received = '1' ) then
    seq_daq_next_state <= seq_daq_state_12;
    else
    seq_daq_next_state <= seq_daq_state_11;
    end if;

      when seq_daq_state_12 =>
      if ( mux_channel(5) = '1' ) then
            seq_daq_next_state <= seq_daq_state_13;
    else
            seq_daq_next_state <= seq_daq_state_14;
    end if;

      when seq_daq_state_13 =>
    if (  seq_data_received = '1' ) then
    seq_daq_next_state <= seq_daq_state_14;
    else
    seq_daq_next_state <= seq_daq_state_13;
    end if;

      when seq_daq_state_14 =>
      if ( mux_channel(6) = '1' ) then
            seq_daq_next_state <= seq_daq_state_15;
    else
            seq_daq_next_state <= seq_daq_state_16;
    end if;

      when seq_daq_state_15 =>
    if (  seq_data_received = '1' ) then
    seq_daq_next_state <= seq_daq_state_16;
    else
    seq_daq_next_state <= seq_daq_state_15;
    end if;

      when seq_daq_state_16 =>
      if ( mux_channel(7) = '1' ) then
            seq_daq_next_state <= seq_daq_state_17;
    else
            seq_daq_next_state <= seq_daq_state_1;
    end if;

      when seq_daq_state_17 =>
    if (  seq_data_received = '1' ) then
    seq_daq_next_state <= seq_daq_state_1;
    else
    seq_daq_next_state <= seq_daq_state_17;
    end if;

  when others =>
    seq_daq_next_state <= seq_daq_state_1;

  end case;

  end process;



Article: 88446
Subject: Re: Problem with quartus 5.0 sp1
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Thu, 18 Aug 2005 09:28:05 -0400
Links: << >>  << T >>  << A >>
Hi Sylvain,

> Last time I got an "Internal Error" with quartus, it just didn't like
> the name of one of my signal ... I just changed the name to another name
> and it worked. Changing it back made it crash again so that was _really_
> the name of the signal.

I have no idea what caused this problem, but if you find something like 
this, we really would like to hear about it.  Especially when you've already 
done our work for us and figured out how and when the problem occurs!

In the future, please file a report on a bug like this with 
mysupport.altera.com!

Thanks,

Paul 



Article: 88447
Subject: Two microblaze in EDK
From: "mvetromille" <mvetromille@gmail.com>
Date: Thu, 18 Aug 2005 09:39:42 -0400
Links: << >>  << T >>  << A >>
Hello!
I'm trying on connecting two microblaze processors in EDK but I'm having
problems. I used microblaze_bread_datafsl and microblaze_bwrite_datafsl
macros to communicate them. The processors are working, they show a
message on the terminal, but when they call the macros, they stop working.
Does anyone know how to solve this problem? Does anyone have an example of
two microblazes communicating?

Thank you!

Melissa


Article: 88448
Subject: Re: Modelsim on a remote display
From: "Marco" <marcotoschi@nospam.it>
Date: Thu, 18 Aug 2005 15:47:14 +0200
Links: << >>  << T >>  << A >>

"Jon Beniston" <jon@beniston.com> wrote in message 
news:1124369762.118278.306890@g43g2000cwa.googlegroups.com...
> You can have local sessions with RealVNC. In fact you can have the
> local user and remote user battle for control of the mouse if you
> really want.
>
> http://www.realvnc.com/
>
> Cheers,
> Jon
>

I have tried but in this way local and remote users have the same session.
I need they have different sessions, not the same.


I need to use modelsim with a remote desktop, when someone is using the 
remote computer.

With XP SP2 is possible applying a patch found on the web.
But in this way Modelsim doesn't accept license and closes itself. 



Article: 88449
Subject: Re: State Machine and BUFG
From: Kolja Sulimma <news@sulimma.de>
Date: Thu, 18 Aug 2005 15:52:36 +0200
Links: << >>  << T >>  << A >>
ADC_MUX is a transparent latch controlled by seq_daq_state. Therefore
synthesis treats seq_daq_state as a clock signal.

You need to either assign a value to ADC_MUX in all branches (including
the case that seq_daq_state=seq_daq_state_4 and mux_channel(1)='1') or
you to add an edge triggered DFF for ADC_MUX.

Kolja Sulimma

Marco schrieb:

>       when seq_daq_state_4 =>
>       if ( mux_channel(1) = '1' ) then
>             Adc_Mux <= "001";
>     end if;
> 
>       when seq_daq_state_5 =>
>



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search