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Nitesh wrote:
> You can have a look at the CORDIC algorithm. Its got a good way of
> calculating log of a number .
> Nitesh
Would something like this be what you are looking for? This function
can be placed in the declaration section before the begin line, and
will generate values that are used to define constants, or specify slv
widths, etc.
<function>
-- The ceil_log2 function returns the minimum register
-- width required to hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while 2**retval < x loop
retval := retval + 1;
end loop;
return retval;
end ceil_log2;
<example usage>
constant COUNTER_BITS : integer := ceil_log2(Counter_Threshold - 1);
Article: 90051Distributed Arithmetic implementations of filters don't need to use the silicon multipliers provided by the FPGA. With your sample rate being much lower than the FPGA clock rate a DA filter may be what you want. The DA filter processes samples 1(or more) bits per clock cycle. For minimum FPGA logic use you would process 1 bit of the sample word per clock cycle. So in your case, 16 clock cycles per sample would be required so you would need a clock rate of 8.8x16 = 140 MHz. (you can use the spartan 3 DCM frequency synthesizer to get a clock rate around this). In the DA filter there are LUTs that calculate the partial products for the multiplies. I have seen newsgroup posts describing how one can use SRL16's(xilinx) instead of the LUT. This allows the LUT to be reloaded in a serial fashion if you want to change the coefficients. Disclaimer: I have implemented a DA filter before but I admit I have not done a decimation filter so I don't know for sure that DA technqiues are appropriate for decimation filters. Most probably there are further logic savings you can achieve because the post decimation sample rate is lower than the incoming sample rate. Search the newsgroup for distributed arithmetic and you will get heaps of good hits. Regards Andrew seb_tech_fr wrote: > I don't know spartan devices. I only work with Virtex-II and virtex-II > Pro. > I have a look on spartan datasheet and according to your requirements > I don't see how you can do except if decimation ratio is greater than > 4 (or if you increase clock rate upto (decimation filter input data > rate)*32). > I've seen you can use up to 4 multipliers. Why do you want to use only > one? > > --------------------------------------------- > -- TechwaY > -- TechwaY > Partners > -------------------------------------------Article: 90052
Hello! I want to debug my system generated in EDK, so I'm using ModelSim. I generated the simulation files and created the testbench file to stimulate my system. However, this testbench just generates the clock and reset, and I need debug my system using my software. Is it possible? What do I have to do in order to incorporate my software in simulation? Does anyone can help me? Does anyone have a project with an example of this? Thank you!Article: 90053
Ben, Yes, it is nice to see Antti posting again. By the way, if Altera doesn't use "faulty bits" why do you have: 1 6,759,871 Line segmentation in programmable logic devices having redundancy circuitry 2 6,600,337 Line segmentation in programmable logic devices having redundancy circuitry 3 6,337,578 Redundancy circuitry for programmable logic devices with interleaved input circuits 4 6,222,382 Redundancy circuitry for programmable logic devices with interleaved input circuits 5 6,166,559 Redundancy circuitry for logic circuits 6 6,107,820 Redundancy circuitry for programmable logic devices with interleaved input circuits 7 6,091,258 Redundancy circuitry for logic circuits 8 6,034,536 Redundancy circuitry for logic circuits 9 5,498,975 Implementation of redundancy on a programmable logic device 9 Patents (plus) for them? Your use of laser frapped fuses to replace bad columns is identical to EasyPath (we just avoid the defects, the same as you). 'HardcopyTo' really does live up to its name: not pin compatible, and a custom ASIC in every (bad) sense of the word. Meanwhile, 'EasyPath' remains easy, and now includes the standard option of being able to change the logic (LUTs may be reprogrammed) or change the IO (strength). Every try to ECO an ASIC? With EasyPath, it is still just bits. AustinArticle: 90054
Ed McGettigan wrote: > We have improved the VGA quality on the upcoming ML405 and ML410 boards > that will be released early next year. I have done the "tie all grounds together" mistake myself, so I know how you feel. But I am wondering why the ML401 uses a 50MHz DAC instead of a 140MHz one like the other two boards. I can't imagine the difference in cost is significant in a $500 product and being limited to 800x600 isn't much fun. I am looking into adding a second video output using the expansion connectors to get around this but the result will be a bit awkward. -- JecelArticle: 90055
thank you Mike Treseler. y dont u try a porn group Symon. dont show off ur stupidity a..hole. CMOSArticle: 90056
"Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag news:dhrn1m$d4n3@xco-news.xilinx.com... > Thomas Entner wrote: > >>The video out has asynchronous resonant spikes running > >>through it. The spikes are about 100 mV p-p, and have a > >>resonant frequency of about 250 MHz, with about 6 half-cycles > >>present. > >> > >>There is also about 15 mV p-p of pixel clock and harmonics. > >> [] > We have improved the VGA quality on the upcoming ML405 and ML410 boards > that will be released early next year. > > Ed Hi Ed, your comment about 405 "to be released early next year" (2006) sounds like firm indication that Xilinx has serious problems with 4FX? The ML405 was announced no later than jan 2005 (maybe earlier), now you are saying that it is coming sometime in 2006 ? Why announce products that are 'maybe' coming more than a year later? I would have expect ML405 to be available by now. Well if there is really an issue with 4FX that would explain why no FX boards are available from Xilinx online shop. Just wondering. AnttiArticle: 90057
"Pete Fraser" <pfraser@covad.net> schrieb im Newsbeitrag news:11jtggpgu5i958f@news.supernews.com... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dhm897$gms$05$1@news.t-online.com... > > > > http://www.hydraxc.com > > > > its not on the website yet, but there is base board for it that can be > > used > > standalone with following specs > > > > Chrontel CH7301 for DVI or RGB out > > V4 (SF363) can be fitted with LX15, LX25 or FX12 > > 2 DDR2 memories > > header for micron camera > > header for char LCD > > rs232 uart > > > > Do you know when it will be available, and how > much it will cost? > The board is 'functional test' phase, eg I still need to verify the DDR2 memories to be operational. As of manufacturing the boards we have everything ready, but there will be no general shipping until the board testing is completed. And sorry i have no pricing info. AnttiArticle: 90058
Of course there is an identical way to implement VHDL in verilog... unfortunately I don't know verilog either :-) A XC2V8000 wow.. you must have a seriously huge budgie.. $8,300 each.. :-) 4 XC3S1000's would only cost you about $220. only 4,000 LUT's.. but I bet it would fit too .. that's why I suggested using 4 FPGA's in the first place. Simon "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1128344153.831983.257240@g44g2000cwa.googlegroups.com... > Every thing is correct. But i cant simply change my design. What i am > thinking now is to proceed with the 120 register version. > If required i can switch over to Virtex "XC2V8000". Will that help > (with 8M gates). > But i am still wondering why Xilinx is not doing any synthesizing work. > And about your code is there any way to implement the same in verilog. > I dont know VHDL. >Article: 90059
there is an industry accepted method for creating abbreviated names....
First drop the vowels
clock => clck
then use industry standard TLA's if applicable...
clock => clk
the exception is a reduction that becomes ambiguous
clear as mud I hope
Simon
"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:3qdb1rFegn59U1@individual.net...
> CMOS wrote:
> > please someone let me know the effects of having "ibuf_lvcmos33" for
> > each input , "obuf_lvcmos33" for each output and "bufg" in some entity
> > declarations.
>
> These connect the device pins
> to the design. If you are using synthesis,
> these will be inferred where needed.
>
> > In addition please let me know the effect of mappimg clk to clock in
> > the following entity declaration.
>
> No effect for syntheses, other than possible confusion.
> An extra delta delay for simulation.
> I would just change the port name to clk.
>
> -- Mike Treseler
Article: 90060Name the clock signal the way you want. These are only symbolic names and only the way you use them will determine whether they are clocks signals or not (or sometimes a combination of both). clk <= clock has no other effect than changing the signal name and introducing some delta delays in simulation. The synthesizer will simplify this code to keep only one signal and will decide whether it inserts a clock buffer based on other considerations (synthesis constraints, use of the signal, and so on). Effects of having ibuf_/obuf_ in VHDL are : 1) specifying @ code-time which electrical interface your FPGA will have w/ other components on the board (important to properly identify logic values 0/1 wrt to electrical voltages) 2) explicitely specifying propagation delays through the I/O pads of the FPGA in order to take their effect into account during the VHDL simulation (note however that w/ high-density FPGA you miss an important contributor to the propagation delay eg the interconnect capacitance that you'll have to add after a place&route via a .sdc file). EricArticle: 90061
Is the following a good way to avoid meta stability problems? The signal 'd'
is synchronous to a1.8 MHz clock?
At least one of the signals a,b or c could end up in a meta stabel
condition.
It then takes the median of the 3 samples.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity median3 is
Port ( clk_24M : in std_logic;
d : in std_logic;
q : out std_logic := '0');
end median3;
architecture beh of median3 is
type state_type is (load_a, load_b, load_c);
signal state : state_type := load_a;
begin
process(clk_24M)
variable a,b,c : std_logic := '0';
begin
if rising_edge(clk_24M) then
case state is
when load_a => a := d; state <= load_b;
when load_b => b := d; state <= load_c;
when load_c => c := d; state <= load_a;
when others => state <= load_a;
end case;
q <= (a and b) or (a and c) or (b and c);
end if;
end process;
end beh;
Article: 90062The problem is i want that in a single chip. How can i link those huge control signals out of FPGA. But i am still wondering why the ISE is not working with my design. Ok any way i am proceeding with 120 registers and will let all of you know the results. Thanks for all the advice and suggestions.Article: 90063
Hi, All. Nowdays I'm focusing on building some design for multiplication of matrices that each element is floating point number. What I want to do is - M(0,0), M(0,1), M(0,2) M(1,0), M(1,1), M(1,2) M(2,0), M(2,1), M(2,2) multiply by vector V(0,0) V(1,0) V(2,0) and when I got the result below, R(0,0) R(1,0) R(2,0) I want to divide R(0,0), R(1,0) by R(2,0) for normalization. Is this multiplication and division are possible using Spartan3 device with VHDL? Or should I convert each floating point numbers to integers and calculate all after that? I'm sure any advice helps me a lot. Thanks.Article: 90064
Kevin Brace wrote: > Hi, > > If you are considering purchasing a Xilinx FPGA-based PCI development > board, and is planning to use it for personal use, I recommend > purchasing a personal version of BDS XPCI PCI IP core. Is this an ngc netlist with verilog wrappers as was described by Antti? Also, the most important issue to me is whether this is something that I can use with the free version of Web ISE or whether I have to purchase a full ISE to use it? > BDS XPCI PCI IP core comes with a PCI testbench for Verilog HDL which > allows the user to simulate the design extensively on an HDL simulator > like ModelSim before firing up the FPGA. That's excellent. Will it run within the evaluation version of ModelSim bundled with Web ISE or even better, will it run in Xilinx's free simulator? Thanks, GHHArticle: 90065
codejk, How fast and precise does it have to be? You could put a MicroBlaze on there with the single-precision floating-point instructions enabled and do it in software. StephenArticle: 90066
Hallo, I have made a clock divider using a counter connected to master clock and a comparator. The comparator has a clock enable to avoid "gating-clock". Now my trouble. I have connected some logic blocks to the new clock, but in this way it has high load and delay. The warning message: WARNING:Route - CLK Net:opb_spi_adc_dac_0/opb_spi_adc_dac_0/USER_LOGIC_I/clk_spi may have excessive skew because 3 NON-CLK pins failed to route using a CLK template. This peripheral is a part of a small micrcontroller based on microblaze. What could I do to solve this trouble? Many Thanks in advance MarcoArticle: 90067
"Marco" <marcotoschi@nospam.it> schrieb im Newsbeitrag news:dhu289$tce$1@news.ngi.it... > Hallo, > I have made a clock divider using a counter connected to master clock and a > comparator. > > The comparator has a clock enable to avoid "gating-clock". > > Now my trouble. I have connected some logic blocks to the new clock, but in > this way it has high load and delay. 1) you should connect ALL clk inputs to master clock (not the new clock) and use clock enables 2) why do you reinvent the wheel? the opb_spi core is provided by xilinx for free! 3) SPI is easier to implement as FSL peripheral :) 4) in most cases the GPIO bitbanged SPI is fastest to implement, and takes no resources (except gpio pins) sure takes some sw overhead anttiArticle: 90068
The clk is sort of a standard style. I do think it is a good idea on your top level to map the IO pin to the clk signal in case you want to change that pin or switch to another clock source. This will save you from having to replace all the clk signals if you want to move your clock source. If you have testbeds, too, these will probably all be written with clk drivers, and so it is sometime a good idea to write your subordinate modules with clk and map it on the upper hierarchial modules with such an assignmnet that you suggest below. Brad Smallridge > In addition please let me know the effect of mappimg clk to clock in > the following entity declaration. > > entity test is port (clock : in std_logic ) > > end clock ; > > architecture arch_test of test is > > signal clk : std_logic ; > clk <= clock; > > end architecture arch_test ; > > in the remainder of the definition, only "clk" is used. "clock" is > never used. Why cant we just use "clock".Article: 90069
Hello all, I am monica from germany.I am using NIOS in cyclone FPGA.I have problem with PIO interrupts. Environment details Quartus Software : version 4.2 build 178 01/19/2005 SJ full version Nios software : version 1.1.0 build 137 FPGA : Altera cyclone I have a input signal which should generate interrupt on every rising edge.So I have used a PIO to capture the signal and generate the IRQ for every rising edge. PIO settings : width : 1bit direction : input only Edge capture reg synchronously capture : yes rising edge :yes generate irq : yes edge : yes The software hangs at "alt_irq_register(TEST_CONTINUE_PIO_IRQ,(void *)&global_flag,&intr_timer);" However software works fine,If I change the PIO settings to width : 1bit direction : input only Edge capture reg synchronously capture : yes rising edge :yes generate irq : yes level : yes I am trying to find out what might be causing my software hang if I use "edge" instead of "level". Did anybody face this sort of wierd behaviour? or is this a bug in Quartus software? I have already wasted lot of time to find out a solution for this problem. I will be obliged if anybody can throw some light on this issue. Thanking you, Monica DsouzaArticle: 90070
"Antti Lukats" <antti@openchip.org> wrote in message news:dhu2oi$a4c$05$1@news.t-online.com... > "Marco" <marcotoschi@nospam.it> schrieb im Newsbeitrag > news:dhu289$tce$1@news.ngi.it... >> Hallo, >> I have made a clock divider using a counter connected to master clock and > a >> comparator. >> >> The comparator has a clock enable to avoid "gating-clock". >> >> Now my trouble. I have connected some logic blocks to the new clock, but > in >> this way it has high load and delay. > > 1) you should connect ALL clk inputs to master clock (not the new clock) > and > use clock enables Where possible I have made as you told. But there are some blocks, where I can't. In example, I must send a 1 MHz clock to a FPGA pin, 2 slave select for and ADC and a DAC... etc... > 2) why do you reinvent the wheel? the opb_spi core is provided by xilinx > for > free! Yes, but it supports only 8 bit peripheral. I contacted Xilinx support and they told me that 16 bit peripheral are not still supported. In my project there are 2 16-bit peripheral, an ADC and a DAC. > 3) SPI is easier to implement as FSL peripheral :) I could try. > 4) in most cases the GPIO bitbanged SPI is fastest to implement, and takes > no resources (except gpio pins) sure takes some sw overhead > > antti >Article: 90071
Jecel wrote: > Ed McGettigan wrote: > >>We have improved the VGA quality on the upcoming ML405 and ML410 boards >>that will be released early next year. > > > I have done the "tie all grounds together" mistake myself, so I know > how you feel. > > But I am wondering why the ML401 uses a 50MHz DAC instead of a 140MHz > one like the other two boards. I can't imagine the difference in cost > is significant in a $500 product and being limited to 800x600 isn't > much fun. I am looking into adding a second video output using the > expansion connectors to get around this but the result will be a bit > awkward. > With every board that is designed you have to make some trade offs between peripherals, performance, power and cost. The ML401/2/3 boards are loaded with features at a very reasonable price point and in order to do that we had to make some compromises in certain areas. When we designed the VGA output on these boards the thought was that it would make it easier for our FAEs to demo the Virtex-4 technology by being able to plug it into a projector for a whole room instead of having everyone crowd around a tiny LCD display. With this in mind we opted for a lower performance solution as it would keep the cost down and not add yet another clock source to the board. This was also carried through to the ML403 (FX12) version that has a lower total IO count (320 vs 448) and the bottom 3 bits of the RGB values are tied to GND providing only 15-bit color instead of 24-bit color on the ML401/2. As it turns out we have had more customer interest interest than we expected in this feature and we have improved the VGA quality on upcoming boards. In order to verify and optimize the new VGA layout we built a protoboard for the XGI headers, so it is possible to do this cleanly. We are not intending on releasing this board for sale, but if there was interest in it we might (if you want to see this send me an email). EdArticle: 90072
"Antti Lukats" <antti@openchip.org> wrote in message news:dhu2oi$a4c$05$1@news.t-online.com... > "Marco" <marcotoschi@nospam.it> schrieb im Newsbeitrag > news:dhu289$tce$1@news.ngi.it... >> Hallo, >> I have made a clock divider using a counter connected to master clock and > a >> comparator. >> >> The comparator has a clock enable to avoid "gating-clock". >> >> Now my trouble. I have connected some logic blocks to the new clock, but > in >> this way it has high load and delay. > > 1) you should connect ALL clk inputs to master clock (not the new clock) > and > use clock enables > 2) why do you reinvent the wheel? the opb_spi core is provided by xilinx > for > free! > 3) SPI is easier to implement as FSL peripheral :) > 4) in most cases the GPIO bitbanged SPI is fastest to implement, and takes > no resources (except gpio pins) sure takes some sw overhead > > antti > > I have tried using a BUFG, and I think it could be a work around. I would know if there are other solution when load is high. MarcoArticle: 90073
Antti Lukats wrote: > "Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag > >>We have improved the VGA quality on the upcoming ML405 and ML410 boards >>that will be released early next year. >> >>Ed > > > Hi Ed, > > your comment about 405 "to be released early next year" (2006) sounds like > firm indication that Xilinx has serious problems with 4FX? The ML405 was > announced no later than jan 2005 (maybe earlier), now you are saying that it > is coming sometime in 2006 ? Why announce products that are 'maybe' coming > more than a year later? I would have expect ML405 to be available by now. > Well if there is really an issue with 4FX that would explain why no FX > boards are available from Xilinx online shop. Just wondering. > Right now almost all of the FX20 silicon is being shipped to customers on a priority basis. We do have fully functional ML405 and ML410 boards in house that we are now making available to our processor specialist FAEs and available on a limited loaner basis to customers and this will increase over coming months. It takes 3-4 months from this point before we can complete all of the rest of the material in order to turn it from early access board that requires a knowledgeable and trained person to use it into a general availability product with full manufacturing tests, documentation, reference designs and packaging. Also, our internal processes has certain requirements that must be met before we place boards in the Xilinx Online Store, this should happen 1-2 months after the boards are available from our distributors. We haven't formally announced the ML405 and ML410, but we have shown them at trade shows and forums such as this as an upcoming development vehicle for Virtex-4. We do this so that our customers and partners can understand what our plans our for support collateral so that they can develop their own product development and test roadmaps. EdArticle: 90074
Hi all, I have a custom designed hardware.... when i ran the xilinx iMPACT to configure the device, it ended up detecting the FPGA and a 101 unknown devices and then just stopped dead? has anyone ever had a similar problem? Please do help. Thanks
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z