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Peter Alfke wrote: > Al, Philip gave you good advice: > For each input pin, you can specify a delay from the pad to the O. The > granularity (given a 200 MHz calibration frequency) is 78.125 ps,but > each tap has its own non-cumulative error of about 15 ps. > I would improve your accuracy by using 16 inputs, each having a > different IDELAY value, so that you divide the 5 ns into 16 steps of > 312 ps each (give or take a 15 ps non-accumulative error). Are the pin-captures within this 15ps window, or is that just the error of the delay elements themselves ? The tap > delays are unaffected by any jitter of the 200 MHz clock. > You interconnect all 16 inputs. When an edge comes in, it will be > delayed differently in each IDELAY, and you use your 200 MHz clock to > register a 16-bit input word which has ones on one end, and zeros on > the other. > It's then your job to find the transition point (look-up-tables are > good for that),and that 4-bit binary value identifies the time as a > fraction of your 5 ns timing (200 MHz) > This means you have an absolute time for the rising as well as for the > falling edge, and the difference is your pulse width. Worst-case error > is thus ± one tap. > Peter Alfke, from home This sounds like a good app-note...., Peter ? Such an app note could also cover : a) If you use just one FPGA pin (eg existing PCB design), what are the alternatives ? b) Trickiest portion of this, I can see, will be crossing the 'phase boundary' between the delay line capture, and the counter-capture. Edge detect flag could be as simple as Sample.0 <> Sample.15. For the Calibrate Philip mentions, and this ease of edge detect, the delay block should be toleranced to be always greater than the clock - ie maybe 6ns for 200MHz. The Clock can be scaled, to match the FPGAs ability to count/capture the edges - which will be related a little to the max time between edges - longer counters are slower c) Pattern detect might need to be single sample error tolerant. ie a pattern of 111110100000000 might occur ? -jgArticle: 92326
> > I started to define and implement a 'new' SoC inertconnect > (Yes, just another interconnect 'standard'). However, will > see how far this gets. A draft of the specification is available at: http://www.jopdesign.com/docu.jsp MartinArticle: 92327
> I have done some, although I haven't covered all the various options - > unfortunately within work time, so I can't post them :-( That's fine, not everything can be open-source ;-) And this work should be done by Xilinx (as you wrote in the other post). > > I based it on the ideas in David Kessner's Free-IP RAM library if that > helps... I can't seem to find it out there on the web anymore. > > The wayback machine has it though... > http://web.archive.org/web/20040519060445/http://www.free-ip.com/ > http://web.archive.org/web/20040605072636/www.free-ip.com/ramlib/index.html But the .zip files are not archieved :-( MartinArticle: 92328
plz give your suggetion soon. thanksArticle: 92329
The 15 ps are what I remember as the difference between the ideal delay from pin to O vs the measured delay, because the taps are not perfectly equal. As a difference between further non-adjacent taps, this statistical error actually gets smaller. The total delay over the 64 bits is exactly 5 ns = one period of the 200 MHz clock. It is servo-controlled. The 200 MHz are allowed to vary by +/-10%, (causing of course an inversely proportional change in tap delay) although that is not described in the data sheet.. I could imagine calibrating this with a variable frequency input of <<200 MHz, effectively measuring the half-period of the incoming signal. Any discontinuities could be attributed to wrong tap-settings and/or different pc-board-to-chip (package) delays. This can of course be remedied by changing individual tap settings (The design in question uses only 25% of the available tap settings). Sampling errors as Jim showed should be impossible, once the design is properly adjusted. I think IDELAY is one of the most exciting innovations in Virtex-4 (together with the FIFO controller). Peter Alfke, from home.Article: 92330
Ravindra, you have to do some thinking yourself, you cannot just dump an incompletely-described problem in our lap. If you do not have enough input pins, you either go to a different chip or package, or you find a way to time-share some inputs. Be creative ! Peter AlfkeArticle: 92331
Hi all, I am doing some experiments with virtex-ii pro50 fpga baord. I want to put my programme in the flash, and make the programme run as long as the power of the fpga board is on. According to the EDK document "chapter 12 Programming flash memory": the program flash memory dialog box allows me to program external Compact Flash Interface(CFI) compliant parallel flash devices on my board. But my flash is "AT49BV162A made by ATMEL" which is Common Flash Interface(CFI), so I want to ask is it OK to run the programme? Or do I have to use a Compact Flash to run my programe? How can I boot from the flash or Prom? Thank you very much! Athena Thank youArticle: 92332
I have some digital waveforms, during the idle interval, it's zero, while in active mode, some patterns are output. This waveform is send through DAC (TI DAC290x-EVM) and ADC (Analog AD9218). I am expecting a clean zeros during the idle interval, however the ADC output are not. How can I correct this problem? Thanks in advance.Article: 92333
When my DAC output is from 0-1V, and is fed into 10-bit AD9218 which is set to binary mode, what binary value will I get when the input is -10mV?Article: 92334
Hi, Have a look to xapp642, it gives some more infomation to undestand what bootloading is all about ! "googlie" <suncream777@hotmail.com> a écrit dans le message de news: 1132916312.649404.67410@g47g2000cwa.googlegroups.com... > I will contact you if i have further information. But how can you > simple write and read to ddr? >Article: 92335
Hi,
Thank you for your time.
But I know all this methods, the thing is that I'd like to understand what
is behind all these button clics series !
I have good skills on handling hardware platfoms with EDK, I'm fine with
writing low level C routines, I have some knowledges about software basics
notions like compiling, linking, linker scripts, so I want to learn about it
!
The fact is I don't know from where to start and I can"t get to find a
complete, simple, example I could analyze !
I've some more information in XAPP642, so I'm studying this.
Thanks.
<beeraka@gmail.com> a écrit dans le message de news:
1132940296.595930.249780@g44g2000cwa.googlegroups.com...
Hi,
EDK does all this stuff that you want on the background and u
can just keep clicking buttons...Here are the answers to your questions
...
1 ) How to compile soft projects --
I guess you know this..in the EDK GUI, just hit
the applications tab and add a software project (add all the source and
the header files )
The other way is when you create is a simple EDK
7.1 project, it creates two sample Software Projects (TestApp_Memory
and TestApp_Peripheral) ..So you can just replace the the source files
in either of the projects
2) How to analyze linking, obj files, linkerscripts, elf content
..
I dont' know the complete answer to this
question but..I mean you have the source for the Linker Script, and
your own sources.. I dunno if there is any other specific reason that
you need the content of the elf file for.
3) Transferring code to external memory
This is not a big deal at all.. When hit the
applications tab and highlight your software project, there will be an
option which says Generate Linker Script. So just click on that and a
Window will pop up... In that window change all the contents to
DDR_SDRAM ( or whatever your external memory ) ..Before you do this
make sure that you have DDR ( or external memory in your system )
4) Jump to external memory execution
Thats what u do in the Linker Script....
Feel free to e-mail me in case you have any other
questions...
--
Parag
sjulhes wrote:
> I guess we have the same questions !
>
> How to compile soft projects
> How to analyze linking, obj files, linkerscripts, elf content ..
> Transfering code to external memory
> Jump to external memory execution
>
> I'm looking for answers, I have no answers yet !
>
>
> "googlie" <suncream777@hotmail.com> a écrit dans le message de news:
> 1132914552.225700.11800@g14g2000cwa.googlegroups.com...
> > Maybe you can you use xmd. Look at the documentation pdf for more
> > information. I'm a student and I'm also trying to set data on ddr but
> > i'm using powerpc. Can you help with it?
> >
Article: 92336
Olaf Petzold schrieb:
> Hi,
>
> if I synthese the followng code (substract using two's-complement and
> adder) using xst and then have a look to the RTL schematic, the co
> output is on ground and a 16bit adder is infered. The carry out (co) is
> the interesting signal for me. Did I wrote wrong code (TB not yet)? How
> to correct it? BTW, is there a way to 'tune' this entities especially to
> avoid such castings and conversations?
>
> Thanks
> Olaf
>
Hi Olaf,
think about the results numeric range. Can it be larger than the biggest
number when you do a subtraction in a signed range (remember, you are
doing two's complement!) because the result will be two's complement too.
In fact there is no other result for co than '0'.
Also you are not using a ci. (which is not really important for a
subtractor)
a more compact code would look like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity simple_sub is
Port ( a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
diff : out std_logic_vector(15 downto 0);
co : out std_logic);
end simple_sub;
architecture Behavioral of simple_sub is
signal total_sum : std_logic_vector(16 downto 0);
begin
total_sum <= a-b;
diff <= total_sum (15 downto 0);
co <= total_sum(16);
end Behavioral;
Your synthesis result: Number of Slices: 17
My synthesis result : Number of Slices: 8
Because I get a single subtractor while you are infering two adders.
Write a testbench and compare both.
I'm using the std_logic libs because it's in the xilinx template, try
for yourself how it can be done with std_numeric. (Please no discussion
about which lib to prefer here. There are enough postings about this topic.)
The important point: Don't re-invent the wheel, when you have a
wheelfactory in the neighbourhood.
The synthesis tools today know how to subtract, just let them do their
job :-)
have a nice synthesis
Eilert
Article: 92337I assume you mean -10mV AC coupled into the AD9218 (it is internally biased at 1/3Vdd) You would have 1/200 of the negative dynamic range, or 1/100 of the span range which gives -10/1024. As the output is set for 2s complement, the output will run from +511 to -512 (Hex = 0x1FF at +511 to 0x200 at -512) for an input of 1Vp-p, so in this case, you should get 3F6, rounded to the nearest integer. (-10 decimal) Cheers PeteSArticle: 92338
"MM" <mbmsv@yahoo.com> schrieb im Newsbeitrag news:3upganF12m2i7U1@individual.net... > Hi folks, > > We have laid out a board for XC4VFX20-10FF672, but can't get a single > sample. The local distributors have been promising us parts for ages, but > now are saying that they can't get any... The design uses MGTs, but at this > point we will accept samples even with the non-functioning MGTs as soon as > everything else is working... Can anyone help please? It is a very important > project for us. > Thanks, > Mikhail Matusov > Hardware Design Engineer > Square Peg Communications > Tel.: +1 (613) 271-0044 ext.231 > Fax: +1 (613) 271-3007 > http://www.squarepeg.ca > we did receive FX20- FF672 CES1 in May or June, the package has an label 'sealed on 28 march 2005' - so if your disti has not been able to get you the very same part by today then they are doing a very bad job. CES1 and also CES2 have been available for a while, just make more push on the distributor ! AnttiArticle: 92339
further to my other reply, if you are using offset binary, then you will get N[off] - 10 (decimal). The output of the DAC at Vin(centre) should be 0x200, so you would get 1F6. Cheers PeteSArticle: 92340
Thanks for all your help. One quick last question, is it possible to internally connect the pins, or do I need to physically wire them up external to the fpga? Thanks again, AlastairArticle: 92341
On Sun, 27 Nov 2005 11:15:45 -0600, alastairlynch@blueyonder.co-dot-uk.no-spam.invalid (al99999) wrote: > >Ok, looking at the datasheet for IDELAY in fixed delay mode, the only >output is 'O' which is the data output. Do I not need to be able to >access the output of the tap multiplexer? You need to look a bit further (which I admit is not easy, as the data sheet has to cover a massive amount of information, and if you don't know what you are looking for, it can be hard to find) In the user's guide (ug070.pdf) http://www.xilinx.com/bvdocs/userguides/ug070.pdf (Just documenting the I/O is from page 215 through 384) on page 309 is figure 7-1 and it shows some of what is in the input part of the I/O tile. (doesn't show ISERDES or I/O standards selection for example), but it does show the IDELAY and the DDR structure. Note that all the little muxes are config bits. The figure shows that the output from IDELAY can be used either directly (O), but it also can feed the inpout Flip Flops. >> So you are on the right track. I think with IDELAY and your example >> numbers, you would bring the input signal in on 8 input pins, and >set >> the delay from 0 to 3.5 nS , all the input flipflops are clocked by >> your 250 MHz clock, and then you decode the resulting 8 bit result >> to get your fine timing, and count the 250 MHz clock for coarse >> timing. > >What do you mean bring the input signal on to 8 input pins? >Physically wire up the input pulse to 8 of the virtex 4 IO pins? Right. Be careful of signal skew on your PCB. Or 4 inputs if you use my IDELAY + DDR suggestion. >Sorry, just a little bit confused!! I'd be grateful for any more >detail you could provide on how to go about doing this. This is tricky stuff. Unfortunately, to be able to get the most out of what these chips have to offer, it requires a lot of study. 169 pages of user guide is a lot to read when looking for one specific detail, but the investment in learning this stuff, is it is easier to find next time :-) >Thanks! > >Al Cheers, PhilipArticle: 92342
Hello all, Environment FPGA : Altera Cyclone FPGA(EP1c20F324I7) Synthesis Tool : Quartus Integrated Synthesis(Quartus Version 4.2 build 178) We are using Altera cyclone FPGA with a nios processor.On our custom new board,few pins are connected to FPGA,but we did not use those pins in our design,However we are observing some signals on these pins. We are confused how FPGA drives logic on the pins that we donot use in design.Are we missing something? Can anybody please give us a hint how to solve this problem? Thank you very much, Monica DSouza, GermanyArticle: 92343
On 28 Nov 2005, Frank put down his happy meal and blurted: > When my DAC output is from 0-1V, and is fed into 10-bit AD9218 which > is set to binary mode, what binary value will I get when the input is > -10mV? > > > > I'm lovin' it.Article: 92344
Hi,
1) A gray-to-binary code that I picked up on the web years ago is
------------------------------------------------------------
function f_gray_to_bin(vval : std_logic_vector) return
std_logic_vector is
variable i : integer;
variable v_accumulate : std_logic_vector(vval'left downto
vval'right);
variable v_par1 : std_logic_vector(vval'length - 1
downto 0);
begin
v_par1 := vval;
v_accumulate(v_par1'left) := v_par1(v_par1'left);
for i in v_par1'left -1 downto 0 loop
v_accumulate(i) := v_par1(i) xor v_accumulate(i + 1);
end loop;
return v_accumulate;
end f_gray_to_bin;
------------------------------------------------------------
I can't find the document I derived it from on my laptop, I still should
have it on a CD somewhere. If I get a chance to look I'll send it to you.
2) Seems a difficult one at first glance.
Would it be feasable
a) just to store the base addresses on the FIFO (since the packet or
whatever always seems to be 18 bytes)
b) use semaphores to indicate whether memory blocks are empty/valid/read
Article: 92345Thank you Peter. My digital output is from 0-1024 (1MHz sine wave 0 -> -1, 1024 -> +1) and fed into the 10 MSBs of DAC (TI DAC290x-EVM). Due to noise, the DAC has some below zero values on oscilloscope (-20mV ~ 0.8V). When I connected this signal to ADC, how do I ensure that the digital output is the same (or nearly the same) value of my original digital input? (The requirement is such that after I captured the ADC O/P with logic analyzer, plotted in graph of 0~1024, it shows a sine wave without bad codes). "PeteS" <ps@fleetwoodmobile.com> wrote in message news:1133167821.286103.231790@f14g2000cwb.googlegroups.com... > further to my other reply, if you are using offset binary, then you > will get N[off] - 10 (decimal). The output of the DAC at Vin(centre) > should be 0x200, so you would get 1F6. > > Cheers > > PeteS >Article: 92346
"Von Heler" <eck@forlivingstone.com> wrote in message news:Xns971C6270A1224eckforlivingstonecom@194.117.143.53... > On 28 Nov 2005, Frank put down his happy meal and blurted: > >> When my DAC output is from 0-1V, and is fed into 10-bit AD9218 which >> is set to binary mode, what binary value will I get when the input is >> -10mV? >> >> >> >> > > > > > I'm lovin' it. I am so hard doing this assignment for the year end bonus's sake. After the money enters my purse, I can BURP about all the nice food in the entire city. I'm lovin' it. Kekekeke...................Article: 92347
CFI is not 'Compact Flash Interface' It is the 'Common Flash Interface'. Compact flash and parallel flash devices are not the same (interface wise) at all. The data sheet should state whether the device is CFI compliant. You can find the datasheet at: http://www.atmel.com/dyn/resources/prod_documents/doc3349.pdf I looked through the datasheet and it is CFI compliant. Cheers PeteSArticle: 92348
HI group, I am searching for some technique which can give me instruction count and cache hits/misses for a configuration created using Xilinx FPGA. I have bitstream corresponding to that configuration. My objective is to get the following statistics such as instruction count and cache hits/misses for any application executing on the system configuration downloaded on FPGA. waiting for reply PankajArticle: 92349
> # ** Note: Verify Test #4: 10 - 20 = 246; co = '1' vs. got = '0'
> # ** Note: got wrong carry = '0'
8 bit only (for convenience)
10 = 8 + 2 = 00001010
20 = 16 + 4= 00010100
inverted: 11101011
add one : 11101100
Do the addition : 00001010
+ 11101100
= 11110110
No carry needed!
-1*2^7+1*2^6+1*2^5+1*2^4+1*2^2+1*2^1 = -128+64+32+16+4+2 = -10
calculation correct!
So what's your TB expecting???
Probably you are searching for the (here) ninth bit of the result which
should be '1' if the result is negative. But don't confuse this with a
carry signal! That's two totally different things!
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