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Thanks for the info Looking more and more like going to have to use a custom pcb anyway. The code were using is small so a spartan 3 is ideal but it just needs so many I/O's (just the way it has to work with the other components) Hopefully I'll be able to get something worked out Keith WakehamArticle: 91551
"Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message news:436f32f9$0$11868$3b214f66@tunews.univie.ac.at... >I want to use an Altera CPLD to do the interface between an ISA-Bus and a >Cyclone II-FPGA. > The CPLD should satisfy the criteria of the ISA-Bus timing to > enable/disable the FPGA and do the level-conversion between the 5V > ISA-Bus-levels and the logic levels of the FPGA (3,3V or 2,5V or 1,8V). > > I found this Altera CPLDs: > MAX II doesn't support 5V I/Os > MAX 3000A > MAX 7000B doesn't support 5V I/Os > MAX 7000AE > MAX 7000S > What is the main difference between this 3 remaining CPLDs? > Is one of them a mature device? > Which Altera CPLD should I use, I'm unfortunately not so familiar with > CPLDs. > I would recommend the MAX 3000A as it is 3.3V with 5V tolerant I/O and will interface to the Cyclone II using 3.3V I/O levels. The MAX 7000AE will also work (3.3V with 5V tolerance) but is more expensive. The MAX7000S is an older 5V family (cannot interface directly to the Cyclone II). Daniel LangArticle: 91552
Zara wrote: > On Mon, 7 Nov 2005 23:42:57 -0500, "Dave Roberts" <anon@anon.com> > wrote: > > >You are exactly right. I'm a researcher doing error control experiments and > >I need to find a way of making an arbitrary delay between registers. Any > >ideas how I can do this? Ideally I want to build a 32-bit wide bus between > >registers where each bit line has approximately the same (long) delay. I > >want to make a fake critical path. > > > >Regards, > > > >Dave. > > > ><robertncsu@gmail.com> wrote in message > >news:1131423585.021801.150580@g49g2000cwa.googlegroups.com... > >> When you say logic delay, do you mean you want to increase delay in the > >> same clock or do you just want to add delays? > >> > >> For just delays, you can add as many flip-flops as the number of > >> clock-delays you need. But I am guessing you need delay between two > >> registers, right? > >> > >> I am wondering why do you need such a delay? > >> > >> Robert. > >> > > > > You should use primitives, and check out "Optimize instantiated > primitives". I think you should alos LOC or RLOC the primitives, to > have more control over the delay > > -- Zara Use LUT primitives (not gates) to ensure that the tools don't remove them. Also it is possible to get finer-grained delays using carry-chain primitives, but you'll need to do a lot more work to achieve this. Xilinx has an appnote XAPP250 with a reference design in verilog and VHDL. Look at the Verilog module muxdelchain32.v for an example of using carry chain primitives.Article: 91553
Phil Tomson wrote:
> The main advantage that C has over the HDLs is that many software
> engineers know C, not many know VHDL/verilog. Perhaps the goal of
> targetting FPGAs with C is to allow lots of software engineers to be able
> to develop algorithms that can be accelerated in a FPGA.
When we look at FPGAs for reconfigurable computing, that is certainly
the draw. When you look at C like offering for FPGAs from firms like
Mitrionics and their product Mitrion-C which directly targets moving
High Performance Computing (HPC) applications to FPGAs:
http://news.taborcommunications.com/msgget.jsp?mid=461789&xsl=story.xsl
http://www.mitrionics.com/index.shtml
with the claim of 20 times faster execution on FPGAs, it's pretty clear
that FPGA have a new volume market. If you google search reconfigurable
computing, there are links to hundreds of firms and projects with this
goal.
> Of course a lot of software engineers do not prefer C these days....
There are more different types of software engineers than there are
hardware engineers. Most software engineers have never liked plain
vanilla C, just as most hardware engineers don't like RF and power
supply engineering.
That has always been true. C has always been the systems programming
language of choice for low level implementation as a direct substitute
for
assembly language. This has been true since the early days in the 1970s
when C was designed from the "B programming Language" which was a
threaded interpreter to a fully compiled language usable to replace
almost
all the assembly in the UNIX operating system and utilities during the
V5,
to V6, to V7 migrations.
Higher level languages, with better database and GUI interfaces, and
other
applications development libraries have always been the language of
choice for higher level applications. These days that is a large number
of
higher level object oriented or application specific languages,
including
C++ and Java. While C++ and Java resemble C syntax, that is about
where the simularity ends. Much like Apples, Oranges, and Bananas
all grow on plants known as trees, and that is where the simularity
ends.
C as a low level assembly language replacement, is primarily used by a
subset of programmers doing systems level programming and a small
group of applications programmers doing hardware interfacing and
performance sensitive optimizations. These programmers frequently have
the skill sets to understand interfacing to hardware at a high level,
and
are the target of many current C based reconfigurable computing
development tools projects. While some high level applications
programmers
used to coding in C++, Java, and other production languages may be
trainable to do low level C work on FPGAs, in general they will find C
about as primative as a VHDL/Verilog designer will find Schematics.
So, like it or not, there are two vary different markets for FPGA
hardware
and tools. Those building hardware, and those building applications for
HPC platforms. And a lot of grey area in between.
Article: 91554"Dhivya" <dhivya.nshankar@gmail.com> schrieb im Newsbeitrag news:1131473946.389474.175990@g14g2000cwa.googlegroups.com... > hi.. > i am tryin to interface the pico blaze from SPRATAN III to a computer > and hvin some trouble..can ny 1 guide me/?? > There are lots of different ways to do that. Which interface of the PC do you want to use ? You can choose between USB, Firewire, Ethernet, parallel port, RS232, PCMCIA, PCI, ISA and some millions more. But there is a simple and cost effective solution with the Xilinx Parallel cable III. Use the JTAG interface with an user JTAG register. see: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=krs_blockRAM MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !Article: 91555
"Henry" <apl2research@comcast.net> schrieb im Newsbeitrag news:-YOdnUhO1K2JlO3eRVn-qw@comcast.com... > I'm looking for some suggestions/recommendations with CPLD's and development > software. > > > > I'm new to CPLD's and a couple projects of mine will involve redesigning > existing "though hole" hardware using a CPLD. I've researching some Xilinx > products, and believe the 9500 series will do everything I need, as my needs > really aren't that great. My only issue with the ISE software is I need to > recreate all the TTL IC logic from scratch, which will prove to be very time > consuming. I was hoping to find a design package that would already have > existing "groups" of TTL logic designed so I won't have to take as much time > with the schematic design and layout. For example in ISE it took me about > 15 minutes just to draw the logic to a 74LS245. Only took me 3 minutes to > "wire" it up. > > > > Any recommendations on other companies, other software and your experiences > with them would be appreciated. > > > > Thanks for your time. > > > > > > Henry > > GSE-Reactive.com > > My email is listed on the site if you wish to contact me directly. > > From a TTL designer's view, a library of TTL components is fine. However painting schematics is boring, and modifications are very time consuming. Designing logic with 74'245 and other tristate logic doesn't map 1:1 in modern programmable logic. So you have to modify the original schematics anyway. That's why you should learn VHDL. It's easy. And there are lots of excellent introductory courses online. -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !Article: 91556
Ray Andraka wrote: > Tobias Weingartner wrote: > > >In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote: > > > > > >>as example VQ100 is really nice package very thin, so largest LUTs you get > >>in VQ100 is S3e. etc.. > >> > >> > > > >I realize that there are people out there that need the 1000+ pin packages > >that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs > >would come in VQ100/144 packages. Personally, I'd love to have the capacity, > >but I really dont need (or want) the complexity and raw bandwidth of having > >to deal with several hundred (or a thousand) pins... > > > > > > > Unfortunately, the size of the cavity in those small packages is far too > small to fit the die for the high density parts, and even if it did fit, > you may have power dissipation issues as well. > > -- > --Ray Andraka, P.E. any idea how big the dies are?, what will fit in a vq100, the only thing I could find on the web was something like 3x3mm sounds small for a 10x10 package? -LasseArticle: 91557
Hello, just tried to get the ml403_emb_ref-project working. During MAP I get 8 errors of the following type: ERROR:Pack:1564 - The dual data rate register plb_ddr_0/plb_ddr_0/DDR_CTRL_I/IO_REG_I/DDR_DQS_REG_V4_I3 failed to join the OLOGIC component as required The OLOGIC SR signal does not match the ILOGIC SR signal, or the ILOGIC SR signal is absent. The OLOGIC REV signal does not match the ILOGIC REV signal, or the ILOGIC REV signal is absent. Any hints? Thanks and greetings UdoArticle: 91558
langwadt@ieee.org wrote: > Ray Andraka wrote: >> Tobias Weingartner wrote: >> >>> In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote: >>> >>> >>>> as example VQ100 is really nice package very thin, so largest LUTs you get >>>> in VQ100 is S3e. etc.. >>>> >>>> >>> I realize that there are people out there that need the 1000+ pin packages >>> that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs >>> would come in VQ100/144 packages. Personally, I'd love to have the capacity, >>> but I really dont need (or want) the complexity and raw bandwidth of having >>> to deal with several hundred (or a thousand) pins... >>> >>> >>> >> Unfortunately, the size of the cavity in those small packages is far too >> small to fit the die for the high density parts, and even if it did fit, >> you may have power dissipation issues as well. >> >> -- >> --Ray Andraka, P.E. > > any idea how big the dies are?, what will fit in a vq100, the only > thing I could find on the web was something like 3x3mm sounds small > for a 10x10 package? > > -Lasse That sounds about right to me. You've got to remember there's a tolerance on the die placement, so the interior die 'room' needs to be larger, then you've got the anchor space for the pins themselves and then the added space for the wirebonds. BGAs can accommodate much larger dies given equivalent sizing to QFP etc etc. They don't require any room for wirebonds in almost all cases.Article: 91559
What does this "Intellectual Property" actually mean. is it like copyright? Is it the oposite of opencores ? <allanherriman@hotmail.com> wrote in message news:1131431142.314073.177710@o13g2000cwo.googlegroups.com... > mughat wrote: >> > > Intellectual Property. > > http://www.acronymfinder.com/af-query.asp?String=exact&Acronym=ip&Find=Find > > Regards, > Allan >Article: 91560
Hello, I am using xilinx ml310 board. Now I want to use networking feature on the board and hence I have to enable the "ENABLE PCI" option in the configuration of kernel which I am trying to load onto the ppc. Now once I enable the enable pci option what happens is that the kernel during the make zImage command execution asks for the following parameters which are not present in the xparameters_ml300.h file `XPAR_PCI_0_IO_BASEADDR' `XPAR_PCI_0_CONFIG_ADDR' `XPAR_PCI_0_LCONFIG_ADDR' All these parameters I believe get added in xparamters_ml300.h file. If I am using ml300 board and I add the pci module in the bsp then they get added. However the ml310 board has a different architecture and hence the pci bridge parameters get added instead of the above. How do I get around this problem.If I disable the pci then I can compile the kernel succesfully. But to use the networking feature I believe I have to use pci. Has anyone come across this problem? Has anyone successfully compiled linux kernel with pci support on ml310? Thanks, NiteshArticle: 91561
Please visit the ML310 web pages at http://www.xilinx.com/ml310. Under Documentation and reference designs you will find a section of information on how to build a Linux system including PCI. One of these documents is a "Tutorial on how to configure and re-create the Linux kernel for the PCI design using XPS and MVL 3.1 Pro." (http://www.xilinx.com/products/boards/ml310/current/reference_designs/pci/linux/ml310_pci_linux_bsp_proj_creation.pdf) Cheers, - Peter Nitesh wrote: > Hello, > I am using xilinx ml310 board. Now I want to use networking feature on > the > board > and hence I have to enable the "ENABLE PCI" option in the > configuration of > kernel which I am trying to load onto the ppc. > Now once I enable the enable pci option what happens is that the kernel > during > the make zImage command execution asks for the following parameters > which are > not present in the xparameters_ml300.h file > > `XPAR_PCI_0_IO_BASEADDR' > `XPAR_PCI_0_CONFIG_ADDR' > `XPAR_PCI_0_LCONFIG_ADDR' > > All these parameters I believe get added in xparamters_ml300.h file. If > I am > using ml300 board and I add the pci module in the bsp then they get > added. > However the ml310 board has a different architecture and hence the pci > bridge > parameters get added instead of the above. > How do I get around this problem.If I disable the pci then I can > compile the > kernel succesfully. But to use the networking feature I believe I have > to use > pci. > Has anyone come across this problem? > Has anyone successfully compiled linux kernel with pci support on > ml310? > Thanks, > Nitesh >Article: 91562
mughat wrote: > What does this "Intellectual Property" actually mean. is it like copyright? > Is it the oposite of opencores ? It means some implementation of an idea that is not actual property (ie not physical) but is being represented or sold as a physical quantity. ie you can buy an IP core from someone, but that doesn't entitle you to any rights other than the usage of this core and possible redistribution based on royalties etc. You can't disclose the contents of the core, or attempt to reverse engineer it, much like a standard product.Article: 91563
"IP Core" is often [mis]used even when the writer does not mean to
exclude public domain or open source works. For this reason, the term
"gateware" is preferred unless you intend to deliberately exclude
noncommercial creations.
http://en.wikipedia.org/wiki/Gateware
- a
"mughat" <mughat@gmail.com> writes:
> What does this "Intellectual Property" actually mean. is it like copyright?
> Is it the oposite of opencores ?
>
> <allanherriman@hotmail.com> wrote in message
> news:1131431142.314073.177710@o13g2000cwo.googlegroups.com...
>> mughat wrote:
>>>
>>
>> Intellectual Property.
>>
>> http://www.acronymfinder.com/af-query.asp?String=exact&Acronym=ip&Find=Find
>>
>> Regards,
>> Allan
>>
>
>
--
PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380
Q: "Won't the pendulum swing back?"
A: "It has never been a pendulum. Think tectonic plates instead."
-- from patrick.net
Article: 91564Hi all, I mean that how to use the registers and fifo when I am creating my own IP core. How to transfer data with my ip core. Thank you. AthenaArticle: 91565
>I'm currently doing some research into Intellectual Property for SoC >designs and just wanted to get a feal for the things that are important >to people who actually purcahse/use IP. For example support from the >vendor after sale seems to be important from people I have already >spoken to. The top of my list would be a clean design. In particular, the interface to your block of logic. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 91566
On Tue, 08 Nov 2005 13:59:57 GMT, "Vanheesbeke Stefaan" <svhb@pandora.be> wrote: >Hello, > >What tools do I need for changing an outsourced dising from a 3020A to a >3030A Xilinx device (the 3020A is obsolete). Are you changing the design, or just migrating from one device size to another? I would have thought that if the 3020A was unavailable, the 3030A would also be unavailable http://www.fpga-faq.org/FAQ_Pages/0009_Xilinx_sw_versions.htm >I only have a XNF netlist available. If you are not changing the design, then this is a simple edit of this file where the part number is specified. Look for a line like this: PART, 3020APC84-100 and change it to PART, 3030APC84-100 then re-run place and route and bitstream generate. If you are changing the design as well, then this will make a very difficult project, extremely difficult. As this is all you have, you will have to edit this netlist, which can be done, but it was never designed for. >Thanks While this may not be what you want to hear, you may be better off figuring out your desired function, and starting a new design with current products. This is not easy either, as you probably have existing boards, and everything runs at 5V . There are no current products that will fit into the old footprint of the 3020A, and almost none of the current products tolerate 5V. Good luck, PhilipArticle: 91567
> 4. Jan Panteltje > > OK I respect your view, but I also respect my view and experience > and that even more ;-) > > So, you do not seem to get what I am hinting at :-) In passing I came across this thread so as the author of the Zeus editor I though I might add my 2 cents worth. > Some observations: > This syntax highlighting/coloring has nothing to do with > vision sharpness, IMHO Syntax highlighting does make coding easier, but like so many things, it takes some practice and it is not for everybody. For example I personally have bad habit of transposing characters when I type too fast. This means when I try to type this: true I end up with this: ture With syntax highlighting this mistake is very easy to detect, because the word "true" is a keyword and I know it must be blue in color. > we have even less color sensors in the eye then BW, and these > need more light too, so reading color takes more brain cycles! I don't know if I'm thinking any harder, but I do know that after years of reading syntax highlighted code, I find it very hard to read mono colored code. Similarly, I was one of those coders that never saw a need for features like code folding, but now that I have been using it for a few months, I do find there are times when it come in handy (ie finding missing brace characters, hiding unwanted text, copying or deleting a block of code). > In the even older days (of editors) there were no full screen > editors, and one worked at a line at the time while you hade a > VERY clear picture in your head of the whole source (text)! This hold true even today. IMHO any programmer that can create a "clear picture" the code in their head will be more productive than those that can't. The fact that modern day editors display more information might discourage some programmers from forming this view, but IMHO this has more to do with the quality of the programmer than the tool they are using. > When we get really decadent and use a MS product with very small > windows with graphics that 'pre-types' half a C++ function for > you (Visual Studio), then yes that may seem easy, especially to > the beginner. However *I* personally find it annoying when using > these windows in windows in windows that you constantly need to > scroll even on a 19 inch monitor.. I agree 100%. The Microsoft VC++ has an amazing ability of wasting screen real-estate, forcing the programmer to code in a space the size of a postage stamp :) But it is unfair to think all tools are like MSVC++. Zeus definitely does not impose these types of constraints on the user. > Then use a makefile, drop that GUI. Zeus, like many other programming editors will quite happily let you use make files. > GUI is handy for SOME applications, like moving modules around > perhaps in a diagram, and buttons, sliders, graphs, what not. > But not for text oriented code. Once again I agree totally. > For TEXT oriented code you need (are best of with) a TEXT oriented > editor, no mouse, no, set mouse traps, get rid of these.. Zeus is just such an editor, which I assume is why Eli uses it ;) > Fingers on the keyboard. Always. > But if you CANNOT have the code picture in your head, forgat > about programming. Agreed, but this has more to do with the individual rather than the tool they are using. Jussi Jumppanen Author: Zeus for Windows Programmer's IDEArticle: 91568
Hi Kevin, I can't figure your explanation. Even if you wnated to step (in clock cycles) the IO enable could still be in the IOB! Using an internal FF, with defined placement and routing, gives control of scew within the same cycle - if you wanted it! Anthony.Article: 91569
If you let us know what CAD system you are using... there might be a foot print about that's already getting produced. I've been using Spartan 2e 150 and Spartan 3 200 / 1000 in ft256 and fg360 respectively. The Spartan 2 footprint is tried and true for Protel 99SE.. all you need to do is to add the optional outer 2 rows of vias (it uses pre-routes) The Spartan 3 is based upon the Spartan 2 version and boards are expected next month. Simon <Terradestroyer@gmail.com> wrote in message news:1131485645.572608.153500@z14g2000cwz.googlegroups.com... > Thanks for the info > > Looking more and more like going to have to use a custom pcb anyway. > The code were using is small so a spartan 3 is ideal but it just needs > so many I/O's (just the way it has to work with the other components) > > Hopefully I'll be able to get something worked out > > Keith Wakeham >Article: 91570
its important to note that IF you ever user a reset on a shift register, the a SRL16 CAN'T be inferred as it doesn't have a reset! "Ray Andraka" <ray@andraka.com> wrote in message news:P7Jbf.2$Mi5.0@dukeread07... > Antti Lukats wrote: > > >AGREE 100% > > > >SRL16 is way useful but I do not see it nearly possible that they will be > >used the best > >way with regular synthesis. so the customer should be at least aware of what > >is needed > >to get the SRL16 being used (automatically) or then use them directly. > > > >Antti > > > > > > > Current synthesis pretty much only instantiates the SRL16 as a fixed > length shift register, and then only if the designer didn't put resets > on the registers. There is supposedly a magic incantation in Synplicity > that will infer a dynamic shift, but for th elife of me I have not been > able to get it to infer that consistently, and the words to the > incantation seem to change with each revision of the software. I find > it to require less effort just to instantiate the SRL16, especially if > you are actually using the dynamic capability. Also, a common mistake > with inferred fixed length shift registers is the synthesis often does > not infer a flip-flop at the SRL16 outputs, which kills clock > performance. Synplify will put a flip-flop at the output of a delay, > but if you have a register deeper than 17 clocks, it strings together > SLR16's with no flip-flops between, which again kills the performance. > (This may have been fixed in later versions, I haven't checked). > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 91571
I am a student and a novicee for FFT... can any one tell me how to start with implementing Fast Fourier Transform on xilinx virtex pro. i know there xilinx core generator which can do... but i want to do it for floating point.... any help for this starter... would be highly appreciated... i am getting lots of info, but there is nothing that is convincing me... IF any one can tell me the steps how to atleast start with this project thanks in Advance PeaceArticle: 91572
Now including the core generator in webpack would defiantly be a plus :-) Simon "Eric Smith" <eric@brouhaha.com> wrote in message news:qh8xw082b2.fsf@ruckus.brouhaha.com... > I just found this article by accident, and haven't seen this information > widely publicized: > > http://www.esp2000.ro/articol.php?id_ar=2850 > > Summary: > > There won't be a BaseX version of 8.1i. However, BaseX customers still > in-warranty will be offered an upgrade to full ISE Foundation for $1495. > Alternatively, they can transition to WebPack 8.1i with no loss of > functionality. > > WebPack 8.1i will still be available at no charge, and will have all the > features that BaseX had. In particular, it will support all the > devices formerly supported by BaseX, and will also now include the > FPGA Editor, ISE Simulator Lite, and CORE Generator. > > Disclaimer: that's just what I found in the article, and I have no idea > how accurate the information is. > > EricArticle: 91573
http://www.context.cx/ I have been using the above editor for 2 or three years with VHDL.. the best editor at the price IMO Simon "Eli Hughes" <emh203@psu.edu> wrote in message news:dkodda$1f9c$1@f04n12.cac.psu.edu... > Check out the Zeus Editor. www.zeusedit.com > > > Is is very lost cost and now supports Verilog files with nice code > folding! (begin/end case/endcase) > > -EliArticle: 91574
Hi I had a similar problem time back.... I was using a spartan series xcs10. but I solved the problem by debugging arch.... on debug request FPGA Translates the data into UART....JTAG??? I have got to see giohdl@netscape.net wrote: > Hi all. > I'm using a Virtex2 fpga which uses a lot of BRAMs. > The design modifies the content of these BRAMs during elaboration. > Is it possible to dynamically readback the BRAMs contents in a text > file using JTAG? > I've read the Xilinx documentation (impact) but I can't find a simple > and fast solution. > Can anybody help me? > Thanks.
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