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On Thu, 17 Nov 2005 17:19:17 +1000, "Michael Chan" <mchan@itee.uq.edu.au> wrote: >I'm looking for a good book that goes deeply into theory about transmission >lines and crosstalk in high speed communications systems. If anyone has any >good references, please let me know. > >I have the book High-Speed Digital Design by Howard Johnson, which has some >good stuff in it, but I'm looking for another reference which gives detailed >attention to crosstalk. In particular, how crosstalk is modelled, and >methods for mitigating crosstalk. > >Thanks in advance, > >Michael. > I strongly recommend "Signal Integrity Simplified" by Eric Bogatin. It's well-written, and manages to go into a lot of detail without overwhelming the SI newcomer. And there's a 68-page chapter on crosstalk. Bob Perlman Cambrian Design WorksArticle: 91951
21127 would not cause what Sebastien is experiencing (on V4), That concerns itself with a lower than 500 MHz possible CLKIN if the device has been baked at high Vdd AND high temperature (see the NBTI white paper). In actual fact, we saw this effect in HTOL testing with the production tester, but have never seen it in actual fact either on the test bench, or in any testing done by any customers. There is a suspicion that the testing done is far too tough, and the problem only appears on the production tester (which tests to >700 MHz, with a +/- 100 MHz sampling) in its tests to ensure that the DCM will operate over all corners of the process, voltage and temperatures). For any device with a DCM: More likely is that the placement of the DCM affects the timing of the paths that are used. Check all the constraints, and check to see that the global clock resources are bring routed properly by looking at the design in FPGA Editor. For V2 Pro there are clock macros which are used to minimize the possible skew from different DCM locations. If this is V2 Pro, then I could see this happening if the macros were not being used. Austin Symon wrote: > Cher Sebastien, > What part are you using? Virtex4? Have you seen answer 21127? > HTH, Syms. > > "seb_tech_fr" <sebastien.coquet@techway-dot-fr.no-spam.invalid> wrote in > message news:G-SdnWildOwnJ-HeRVn_vA@giganews.com... > >>Hi, >>Does somebody know DCM corner issues? My DCM is not running at very >>high clock rate (only 107MHz), so I don't think this issue is >>connected with XAPP685 application notes > > >Article: 91952
Stephane, I experienced a somewhat similar problem several months back, and it too was with ise6.2. All the project files were on a remote workstation for some type of corporate back-up thing. It was rumored that it did on the fly file compression, had some type of disk file caching system, any who knows what else. I tried putting all my files on the local hard disk, and compiled from there. That solved my ISE dependence compiling problem. -NewmanArticle: 91953
On Thu, 17 Nov 2005 18:26:49 +0100, "Gunter Knittel" <knittel@gris.uni-tuebingen.de> wrote: >Michael, > >I don't know a good book, but a few web sites were helpful >for me, and may serve as a starting point. > >http://www.ek.isy.liu.se/courses/tsek35/files2004/3.wires.pdf > >http://www.bolton.ac.uk/mind/corep/sig-int/sig-int-1/lesson1.html#6 > >http://www.sp.se/electronics/RnD/reports/EMC/lccalc.pdf > >At > >http://www.sp.se/electronics/RnD/software/eng/LC-Calc.htm > >you can find a tool for computing the mutual inductance and capacitance >matrices from conductor cross-sections. The matrices can be >used with PSpice to simulate crosstalk. >I experienced good agreement between the explicit formulas in the topmost >reference, the simulations, and later the measurements at the PCBs. >It appears that with the appropriate design style you can drastically reduce >XT - to a point where it is of no concern any more. I have a bus of >36 single-ended lines, each wire being 0.1mm (4mil) wide and >only 0.21mm apart from each neighbor (edge to edge), >running strictly parallel for >30cm (12"). Rise time is <1ns (ALVCH). >This appears to be a worst-case scenario, but XT never reaches critical >levels. >The important thing is to use a stripline configuration, in which inductive >and capacitive forward crosstalk cancel out. Backward crosstalk can be >controlled by series termination. > >Hope this is of use for you, >cheers >Gunter Thanks for the list of interesting links and documents. I agree with what you said about using stripline to greatly reduce forward crosstalk. But I don't agree that backward crosstalk can be controlled with series termination, at least not in a way that's generally useful. If you have two co-located drivers sending signals along parallel traces to two co-located receivers somewhere else on your board, series termination certainly helps control reflections on both lines. But you'll still see the effects of backward crosstalk at the receivers between time T and 3T, where T is the one-way line delay. Give it a try in a SPICE coupled-line simulation. By the way, the first edition of "High-Speed Digital Design" got this wrong. Section 5.7.6 originally suggested that series termination would improve crosstalk considerably; this has been amended in the errata (http://www.sigcon.com/errataHSDD.htm). If Howard Johnson can get it wrong, you know it's tricky. Bob Perlman Cambrian Design WorksArticle: 91954
XMD uses the PPC to peek/poke the memory. In other words, XMD forces the PPC to issue a PLB bus (or other interface) read/write operation. For this to happen XMD first stops the PPC. - Peter tony.p.lee@gmail.com wrote: > Newman, > > Do you know if it is possible to peek/poke the memory via XMD - BRAM > or > cache memory (ultra-controller mode) without halting the PPC? > > I heard reading the BRAM can crorrupt it. > > -Tony >Article: 91955
It looks like Altera's Flex20 is the only FPGA with build in support for instantiate high density CAM/TCAM. The Xilinx approach not as dense as Altera. I am looking for a 70x16K solutions and can't find any good one. FLEX20 is .15 um and 5 years old. But Altera doesn't seem to support CAM in the later Cyclone or Stratix. Does anyone know why? High density CAM seems like a valuable addition to the megasize FPGA we have today, especially for network device. Almost all the CAM I seen are expensive and require over 100 pins to interface to them and cost over $40. Would be very nice to stuff them inside a Cyclone or Spartan. -TonyArticle: 91956
I am getting this error. ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site The clock IOB component <gpio_exp_hdr2<7>> is placed at site IOB_X0Y57. The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub optimal condition is acceptable for this design you may set the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and allow your design to continue. I did the Control Panel, System, Advanced, Environment Variables, System varaible, New, Variable Name XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING Varaible Value SET ? This worked but is SET necessary or just having the variable name there enough? This reduced the error to a warning. Is there a way to get around this without this cryptic ritual? Are there any clock inputs brought to headers on the ML403 or will I have to expand my board over to the DIFF CLK IN area and somehow tie into the SMA connectors there? Is there a way I can add a clock buf to the input I already have on the header? The signal is actually fairly slow since it frames the data, not clocks it. I feed it to a DCM to generate a clock signal internally. Brad Smallridge aivision.comArticle: 91957
tony.p.lee@gmail.com wrote:
> It looks like Altera's Flex20 is the only FPGA with build in support
> for CAM/TCAM.
> But Altera doesn't seem to support CAM in the later Cyclone or Stratix.
> Does anyone know why?
I expect that most customers didn't use it.
> High density CAM seems like a valuable addition to the megasize FPGA
> we have today, especially for network device.
The Altera CAM was inadequate for serious IP/IPv6 applications.
For less demanding applications, there are other ways
to cover a CAM function.
-- Mike Treseler
Article: 91958Thanks for the replies everyone, I'll look into the suggested links and books. Cheers, Michael. "Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:b6jpn11i2ef8l71loo42n2gn3lmlj7muei@4ax.com... > On Thu, 17 Nov 2005 17:19:17 +1000, "Michael Chan" > <mchan@itee.uq.edu.au> wrote: > >>I'm looking for a good book that goes deeply into theory about >>transmission >>lines and crosstalk in high speed communications systems. If anyone has >>any >>good references, please let me know. >> >>I have the book High-Speed Digital Design by Howard Johnson, which has >>some >>good stuff in it, but I'm looking for another reference which gives >>detailed >>attention to crosstalk. In particular, how crosstalk is modelled, and >>methods for mitigating crosstalk. >> >>Thanks in advance, >> >>Michael. >> > > I strongly recommend "Signal Integrity Simplified" by Eric Bogatin. > It's well-written, and manages to go into a lot of detail without > overwhelming the SI newcomer. And there's a 68-page chapter on > crosstalk. > > Bob Perlman > Cambrian Design WorksArticle: 91959
Hi Steven, Stephen Craven wrote: > However, the DDR when used with the MicroBlaze does not initially > function correctly upon configuration and has to be reset using the CPU > reset button, after which it works fine until the next configuration. > This is true even for designs using the default BSB MicroBlaze design > for the board. There is an implementation note in the XBD files for the ML310, which says among other things that a minimum clock frequency of 66MHz is required for the DDR parts on this board. It also has a reference to Answer Record 19385. Might be worth a look. Cheers, JohnArticle: 91960
hi ,
when i synthesize using xst i get aliases for certain nets what
are these and why they appear.
Article: 91961
simple question...
IMPACT doesn't recognize my xilinx parallel cable IV when downloading
projects to the board.
I have read in some articles that a power supply is necessary to power
up
the cable, but there is no power supply or adapter in the box where the
cable came.
------Can any one tell me what do i do? as my laptop does not have the
socket for the pin
that is with parallel cable IV... which i think may be for
powering up the cable
-----and it also says
Checking cable driver.
File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found.
There was no driver cd withthe virtex -II pro xc2vp7 board...where do i
get this xusbdfwu.sys file...
Thanks in advance from this starter.
attached is the error i get when i am trying to connect the cable to
download the stream to board.
Regards
--------------------------------------------------------------------------------------------------------
INFO:iMPACT:1777 -
Reading C:/Xilinx/virtex2p/data/xc2vp70.bsd...
INFO:iMPACT:1777 -
Reading C:/Xilinx/virtex2p/data/xc2vp70.bsd...
INFO:iMPACT:501 - '1': Added Device XC2VP70 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
INFO:iMPACT:1777 -
Reading C:/Xilinx/virtex2p/data/xc2vp70.bsd...
----------------------------------------------------------------------
// *** BATCH CMD : setAttribute -position 1 -attr devicePartName -value
"xc2vp70"
// *** BATCH CMD : setAttribute -position 1 -attr configFileName -value
"C:\Xilinx\virtex2p\data\xc2vp70.bsd"
INFO:iMPACT:501 - '1': Added Device XC2VP70 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
INFO:iMPACT:1777 -
Reading C:/Xilinx/virtex2p/data/xc2vp70.bsd...
GUI --- Add one device.
GUI --- #1 xc2vp70 C:\Xilinx\virtex2p\data\xc2vp70.bsd
Device #1 selected
Device #1 selected
GUI --- Auto connect to cable...
// *** BATCH CMD : setCable -port auto
AutoDetecting cable. Please wait.
CB_PROGRESS_START - Starting Operation.
Connecting to cable (USB Port).
Cable connection failed.
Connecting to cable (Parallel Port - LPT1).
Checking cable driver.
Driver windrvr6.sys version = 6.2.2.2. LPT base address = 0378h.
ECP base address = 0778h.
Cable connection failed.
Connecting to cable (Parallel Port - LPT2).
Checking cable driver.
Driver windrvr6.sys version = 6.2.2.2.Cable connection failed.
Connecting to cable (Parallel Port - LPT3).
Checking cable driver.
Driver windrvr6.sys version = 6.2.2.2.Cable connection failed.
Connecting to cable (Parallel Port - LPT4).
Checking cable driver.
Driver windrvr6.sys version = 6.2.2.2.Cable connection failed.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found.
Driver file not found. Inf file version = 0.
Driver xusbdfwu.sys version: 1017 (1017).
Driver windrvr6.sys version = 6.2.2.2.Cable connection failed.
Connecting to cable (COM1 Port).
Cable connection failed.
Cable connection failed.
Cable connection failed.
Cable connection failed.
CB_PROGRESS_END - End Operation.
Elapsed time = 29 sec.
Cable autodetection failed.
WARNING:iMPACT:923 - Can not find cable, check cable setup !
Article: 91962aj wrote: > simple question... > IMPACT doesn't recognize my xilinx parallel cable IV when downloading > projects to the board. > I have read in some articles that a power supply is necessary to power > up > the cable, but there is no power supply or adapter in the box where the > > cable came. > ------Can any one tell me what do i do? as my laptop does not have the > socket for the pin > that is with parallel cable IV... which i think may be for > powering up the cable The dongle gets its power from the target board. -aArticle: 91963
How does one set the environmental variable in ISE 7.1? The following error message was obtained: ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site The clock IOB component <Clk> is placed at site IOB_X1Y48. The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub optimal condition is acceptable for this design you may set the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and allow your design to continue. The Xilinx support solution is: This error warns that you are not using optimal clock resources. The error occurs when the Clock input is Locked to either the N side of a Differential Pair of Clock Capable I/O or to a Low Capacitance input, because this results in a local route and causes additional delay. If this routing is acceptable, then the XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING environment variable should be set; this will relegate the error to a warning. If this routing is not acceptable, then the Clock should use either the P input of a Clock Capable I/O or a Global Clock input.Article: 91964
On 17 Nov 2005 21:53:05 -0800, "Andy Peters" <Bassman59a@yahoo.com> wrote: >aj wrote: >> simple question... >> IMPACT doesn't recognize my xilinx parallel cable IV when downloading >> projects to the board. >> I have read in some articles that a power supply is necessary to power >> up >> the cable, but there is no power supply or adapter in the box where the >> >> cable came. >> ------Can any one tell me what do i do? as my laptop does not have the >> socket for the pin >> that is with parallel cable IV... which i think may be for >> powering up the cable > >The dongle gets its power from the target board. > >-a False. Prallel Cable III getsi its power form the target board, but thisi is not true for Parallel Cable IV. Parallel IV cable gets its power form one of two sources: - PC Ps-2 connection. The cable comes with an adapter for this. It is normally enough, unless you are connecting the PCIV to a portable. In such case, use next option. - External adapter. I think it was a 5V DC, 0.5 Amp adapter (chek it in the docs!). You may buy it almost anywhere, it is pretty standard. The most imprtant thing: You will be unable to connect to PCIV unless its light is on (orange or green colour/color). Best regards, -- ZaraArticle: 91965
Hi Andrew, from the start menu go in Settings-> control panel in control panel click on system in system select the Advanced tab and then click on Envirable variable. press new and on the name write XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING and on the value write 1 FrancescoArticle: 91966
> Open-drain are outputs, not inputs (an I=B2C interface should have bidir > pins, though, but that's another problem). High-impedance has nothing > to do with inputs. Yes, I know. > The usual way is to have an internal signal (called scl_out for > example) that drives the pin's output enable: > > scl <=3D '0' when scl_out =3D '0' else 'Z'; But if I define scl_out permanent '0' the fitter will optimize the bidirection away. That is the problem. So is there a possibility to define a bidirectional port with open-drain-output direction without tristate enable ? >=20 > NicolasArticle: 91967
Usually the Parallel Cable IV comes with a PS2 (keyboard/mouse) type cable that you put between your keyboard and your PS2 socket. This is a major problem with most laptops as they don't have a PS2 socket. In part this is why Xilinx have now produced a USB cable. Easiest solution is to buy a mains adaptor with a suitable jack. You only need a 300/500mA type adaptor and you can usually buy multi-voltage, multi-head adaptors for about £5-10 (US$9-18). If this isn't a good solution you can sometimes get a USB to PS2 adaptor that can supply the 5V needed. Other cheap ways to solve your problem are to get hold of a suitable Parallel Cable 3 look-alike. Available from various manufacturers including ourselves but check the connection type as most don't have flying leads, or the 14 way 2mm cable. John Adair Enterpoint Ltd. - Home of MINI-CAN. The Spartan3 PCI and CAN Development Board. http://www.enterpoint.co.uk "aj" <aj.bohra@gmail.com> wrote in message news:1132292466.565039.196240@g47g2000cwa.googlegroups.com... > simple question... > IMPACT doesn't recognize my xilinx parallel cable IV when downloading > projects to the board. > I have read in some articles that a power supply is necessary to power > up > the cable, but there is no power supply or adapter in the box where the > > cable came. > ------Can any one tell me what do i do? as my laptop does not have the > socket for the pin > that is with parallel cable IV... which i think may be for > powering up the cable > > -----and it also says > Checking cable driver. > File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found. > There was no driver cd withthe virtex -II pro xc2vp7 board...where do i > get this xusbdfwu.sys file... > > > Thanks in advance from this starter. > attached is the error i get when i am trying to connect the cable to > download the stream to board. > Regards > -------------------------------------------------------------------------------------------------------- > > INFO:iMPACT:1777 - > Reading C:/Xilinx/virtex2p/data/xc2vp70.bsd... > INFO:iMPACT:1777 - > Reading C:/Xilinx/virtex2p/data/xc2vp70.bsd... > INFO:iMPACT:501 - '1': Added Device XC2VP70 successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > INFO:iMPACT:1777 - > Reading C:/Xilinx/virtex2p/data/xc2vp70.bsd... > ---------------------------------------------------------------------- > // *** BATCH CMD : setAttribute -position 1 -attr devicePartName -value > "xc2vp70" > // *** BATCH CMD : setAttribute -position 1 -attr configFileName -value > "C:\Xilinx\virtex2p\data\xc2vp70.bsd" > INFO:iMPACT:501 - '1': Added Device XC2VP70 successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > INFO:iMPACT:1777 - > Reading C:/Xilinx/virtex2p/data/xc2vp70.bsd... > GUI --- Add one device. > GUI --- #1 xc2vp70 C:\Xilinx\virtex2p\data\xc2vp70.bsd > Device #1 selected > Device #1 selected > GUI --- Auto connect to cable... > // *** BATCH CMD : setCable -port auto > AutoDetecting cable. Please wait. > CB_PROGRESS_START - Starting Operation. > Connecting to cable (USB Port). > Cable connection failed. > Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > Driver windrvr6.sys version = 6.2.2.2. LPT base address = 0378h. > ECP base address = 0778h. > Cable connection failed. > Connecting to cable (Parallel Port - LPT2). > Checking cable driver. > Driver windrvr6.sys version = 6.2.2.2.Cable connection failed. > Connecting to cable (Parallel Port - LPT3). > Checking cable driver. > Driver windrvr6.sys version = 6.2.2.2.Cable connection failed. > Connecting to cable (Parallel Port - LPT4). > Checking cable driver. > Driver windrvr6.sys version = 6.2.2.2.Cable connection failed. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found. > Driver file not found. Inf file version = 0. > Driver xusbdfwu.sys version: 1017 (1017). > Driver windrvr6.sys version = 6.2.2.2.Cable connection failed. > Connecting to cable (COM1 Port). > Cable connection failed. > Cable connection failed. > Cable connection failed. > Cable connection failed. > CB_PROGRESS_END - End Operation. > Elapsed time = 29 sec. > Cable autodetection failed. > WARNING:iMPACT:923 - Can not find cable, check cable setup ! >Article: 91968
Hello everybody, I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the right side. I heard that in Virtex-4, frames didn't go from the top of the device to the bottom but, that there were upper and a lower frames which could also be addressed separately. This would be helpful, concerning the problem described above. Unfortunately I didn't find any information on this topic in the Xilinx Data Sheets. Now, my question is: Are there upper and lower frames in a Virtex-4? Or do Virtex-4 frames look like the frames in Virtex and Virtex-II? Thanks in advance AndreasArticle: 91969
answer ... no you MUST have a tristate enable. If you want a repeater you will need additional hardware to detect current flow OR you can process commands for all devices and intelligently switch when you think they want to reply. Simon <ALuPin@web.de> wrote in message news:1132304348.633592.255990@z14g2000cwz.googlegroups.com... > Open-drain are outputs, not inputs (an I²C interface should have bidir > pins, though, but that's another problem). High-impedance has nothing > to do with inputs. Yes, I know. > The usual way is to have an internal signal (called scl_out for > example) that drives the pin's output enable: > > scl <= '0' when scl_out = '0' else 'Z'; But if I define scl_out permanent '0' the fitter will optimize the bidirection away. That is the problem. So is there a possibility to define a bidirectional port with open-drain-output direction without tristate enable ? > > NicolasArticle: 91970
hi, i'm grant, studying computer engineering in university of ottawa. i'm using altera cyclone II on up3 board with quartus II enviorment. how is it? is it leading in industry? what kind of job can i get when i'm done. guys, forgive me if i have tons of questions, coz i do care about my career while i know nothing about it right now. :pArticle: 91971
Hi Austin, I use an V2P70, which is loaded at 76%. I don't use any macro for DCM. Which one should I use? Concerning placement and routing, all constraints have been met. It's possible that this part is not constraint enough... Additional information. When I use a lighter version of my design (which is loaded at 20%), it works.. > Austin Leseawrote: 21127 would not cause what Sebastien is experiencing (on V4), > > That concerns itself with a lower than 500 MHz possible CLKIN if the > device has been baked at high Vdd AND high temperature (see the NBTI > white paper). > > In actual fact, we saw this effect in HTOL testing with the production > tester, but have never seen it in actual fact either on the test bench, > or in any testing done by any customers. > > There is a suspicion that the testing done is far too tough, and the > problem only appears on the production tester (which tests to >700 MHz, > with a +/- 100 MHz sampling) in its tests to ensure that the DCM will > operate over all corners of the process, voltage and temperatures). > > > For any device with a DCM: > > More likely is that the placement of the DCM affects the timing of the > paths that are used. > > Check all the constraints, and check to see that the global clock > resources are bring routed properly by looking at the design in FPGA Editor. > > For V2 Pro there are clock macros which are used to minimize the > possible skew from different DCM locations. If this is V2 Pro, then I > could see this happening if the macros were not being used. > > Austin > > > > Symon wrote: > > Cher Sebastien, > What part are you using? Virtex4? Have you seen answer 21127? > HTH, Syms. > > "seb_tech_fr" <sebastien.coquet@techway-dot-fr.no-spam.invalid> wrote in > message news:G-SdnWildOwnJ-HeRVn_vA@giganews.com... > > Hi, > Does somebody know DCM corner issues? My DCM is not running at very > high clock rate (only 107MHz), so I don't think this issue is > connected with XAPP685 application notes > > > [/quote:e23a8545fa]Article: 91972
badgrant wrote:
> hi, i'm grant, studying computer engineering in university of ottawa.
> i'm using altera cyclone II on up3 board with quartus II enviorment.
> how is it? is it leading in industry? what kind of job can i get when
> i'm done.
>
> guys, forgive me if i have tons of questions, coz i do care about my
> career while i know nothing about it right now. :p
Welcome to the fpga world Grant!
Your two best sources for this type of information will be:
http://www.altera.com/literature/lit-cyc2.jsp
http://www.google.com
Talk to your college tutors about local companies doing Fpga
there in Ottawa, they'll be able to get you in touch with people using
these devices in industry. That'll give you a feel for what it's all
about.
Alan
Article: 91973Andreas Nett wrote: > Hello everybody, > > I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the right side. > > I heard that in Virtex-4, frames didn't go from the top of the device to the bottom but, that there were upper and a lower frames which could also be addressed separately. This would be helpful, concerning the problem described above. Unfortunately I didn't find any information on this topic in the Xilinx Data Sheets. > > Now, my question is: Are there upper and lower frames in a Virtex-4? Or do Virtex-4 frames look like the frames in Virtex and Virtex-II? > > Thanks in advance Andreas The height that a frame covers is a clock region, and the number of regions depends of your V4 size. You'll find additional infos on the dedicated mailing list: http://www.itee.uq.edu.au/~listarch/partial-reconfig/ Don't loose time with the tools: it is said that ISE 8.1i will address this issue with V4, but yet I've seen no date of availability. Anyone?Article: 91974
I found the problem description in the Xilinx Answers database (Answer Record #21168), the downloads can be found at http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp - use the ISP SP, even if you're using Webpack (both use the same installer). For the code - just start with something REALLY simple, then build up from there... jvdh
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