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Does anyone know the process of installing FPGA Adv on Linux based system? Does FPGA Adv be have Linux support or not? I have to install modelsim and leonardo spectrum on linux machine separately as well. please suggest if anybody has already done the process. Regards, FahadArticle: 91576
Hi... I am having a quite similar issue... I am using FPGA board Gigilent XS10... with xilinx spartan FPGA.XCS10... I used FS 1.5e and FS2.1E... But then I downloaded web pack 6.xx. Surpeise was that this version didnot supported Spartan XCS10, not even Spartan -II.... I wish Xilinx Management should think on that, although they have made the components obsolete, but poor people like us are still learning on the same... Well then... what to do next... What i did was a little nasty.... Webpack 6.xx supported Vertex - II... And so did previous version FS 3.3 (which a good man donated me). I made my design in 6.xx on device V-II, opened the project in FS 3.3 and then changed the device to Spartan XCS10-PC84..... It worked... Just remenber that keep the gate count under final target device.... and configure the pinouts in each implementation repeatedly..... If u have XNF file it should work... but can you send me little more detail on versions... I am a little shaky in understanding your requirements. At the end... While implementing a Servo control I have lost 8 I/O pins of my FPGA. And this was the only piece that I had. Still some pins are working but if some one can tell me about Availability of XCS10 Spartan FPGA or Can donate it, because i have only one FPGA and only one development board. And if there is an angle which can donate me a new better FPGA or development board, I would be thanful thanx ThanxArticle: 91577
Can you use the DLL to generate a ps clock shift to clock the two registers instead ?? I'm not sure exactly what you are after but you can create arbitrary shifts that way Simon "Gabor" <gabor@alacron.com> wrote in message news:1131487131.921751.238310@z14g2000cwz.googlegroups.com... > > Zara wrote: > > On Mon, 7 Nov 2005 23:42:57 -0500, "Dave Roberts" <anon@anon.com> > > wrote: > > > > >You are exactly right. I'm a researcher doing error control experiments and > > >I need to find a way of making an arbitrary delay between registers. Any > > >ideas how I can do this? Ideally I want to build a 32-bit wide bus between > > >registers where each bit line has approximately the same (long) delay. I > > >want to make a fake critical path. > > > > > >Regards, > > > > > >Dave. > > > > > ><robertncsu@gmail.com> wrote in message > > >news:1131423585.021801.150580@g49g2000cwa.googlegroups.com... > > >> When you say logic delay, do you mean you want to increase delay in the > > >> same clock or do you just want to add delays? > > >> > > >> For just delays, you can add as many flip-flops as the number of > > >> clock-delays you need. But I am guessing you need delay between two > > >> registers, right? > > >> > > >> I am wondering why do you need such a delay? > > >> > > >> Robert. > > >> > > > > > > > You should use primitives, and check out "Optimize instantiated > > primitives". I think you should alos LOC or RLOC the primitives, to > > have more control over the delay > > > > -- Zara > > Use LUT primitives (not gates) to ensure that the tools don't remove > them. Also > it is possible to get finer-grained delays using carry-chain > primitives, but you'll > need to do a lot more work to achieve this. Xilinx has an appnote > XAPP250 > with a reference design in verilog and VHDL. Look at the Verilog > module > muxdelchain32.v for an example of using carry chain primitives. >Article: 91578
Finally got to the heart of the problem. Apparently when porting xco files over to a project for a new device (in this case V4) there is a problem that ISE 7.1 will not upgrade the core to current settings with the new device. This apparently happens even when the logicore is the same version (multiplier in this case). The logicore has to be rebuilt and hence the proper construction for the V4 follows. Thanks for all your help!! -Andrew "Ray Andraka" <ray@andraka.com> wrote in message news:ftybf.3488$IC.1370@dukeread07... > > > Andrew Lohbihler wrote: > >>Thanks John, >> >>The code did work for a Virtex-II and the details of the packing don't >>indicate which column constraint was used. Any idea what constraint should >>be changed to make it work in a Virtex-4? There must be a way to tweak the >>design for the V4 to make it pack similarily as a V2. Any help will do. >> >>Thanks, >>Andrew >> >> > Most of the time, you can re-do the layout so as to not RLOC SRL16s ore > RAM16's into odd columns (this is what you need to do). It is going to > require you to get familiar with the floorplanning that was done for V2 > for this design, and then alter it so that those memory elements only fall > in even columns. > > There is also a bug in the mapper that does not allow RPMs with memory > elements to straddle DSP48 or BRAM columns if there are any memory > elements to the left of the DSP48/BRAM column (in other words, you can't > have any DSP48 or BRAM columns between the RPM's origin and any column > containing either SRL16 or RAM16 elements). That bug was present in 6.x > and 7.1 at least through SP3. I haven't checked to see if it was > corrected in SP4. I don't believe that it was however. In practical > terms, this means any of your macros that use the LUT memory elements must > be less than 4 columns until the bug is fixed, which may require you > breaking them into separately placed pieces (you can do it by just adding > different HU_SET attributes to the elements in each 4 column zone). > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com http://www.andraka.com > "They that give up essential liberty to obtain a little temporary safety > deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 91579
"Bevan Weiss" <kaizen__@NOSPAM.hotmail.com> wrote in message news:uFacf.1820$xD6.102150@news.xtra.co.nz... > langwadt@ieee.org wrote: >> Ray Andraka wrote: >>> Tobias Weingartner wrote: >>> >>>> I realize that there are people out there that need the 1000+ pin >>>> packages >>>> that large-scale FPGAs offer... but I do wish that 2-5 million "gate" >>>> FPGAs >>>> would come in VQ100/144 packages. Personally, I'd love to have the >>>> capacity, >>>> but I really dont need (or want) the complexity and raw bandwidth of >>>> having >>>> to deal with several hundred (or a thousand) pins... >>>> >>>> >>> Unfortunately, the size of the cavity in those small packages is far too >>> small to fit the die for the high density parts, and even if it did fit, >>> you may have power dissipation issues as well. >>> >>> -- >>> --Ray Andraka, P.E. >> >> any idea how big the dies are?, what will fit in a vq100, the only >> thing I could find on the web was something like 3x3mm sounds small >> for a 10x10 package? >> >> -Lasse > > That sounds about right to me. > You've got to remember there's a tolerance on the die placement, so the > interior die 'room' needs to be larger, then you've got the anchor space > for the pins themselves and then the added space for the wirebonds. > > BGAs can accommodate much larger dies given equivalent sizing to QFP etc > etc. They don't require any room for wirebonds in almost all cases. Guys, Here's the problem. These days all the parts are made on 90-130 nm processes. This means that the transistors switch very quickly. They also have lower power supply voltages, lowering the noise threshold. This means that even if the dice fitted the lead frame of a PQFP, the SI would be awful, probably such that the thing wouldn't work. There'd be bloody great inductors between the board ground and the die ground. The frequency isn't the limiting thing, it's the rise time. So, saying you're only gonna drive the outputs at 20 Mbps, doesn't fix the problem of sub ns rise/fall time. You could have small packages like Amkor's micro-lead-frame (MLF) QFN stuff with exposed paddles, but I guess if you don't like BGA, you're not gonna like that either. Cheers, Syms.Article: 91580
Hello, When implementing a 4 bits up/down counter on a Xilinx FPGA, the synthesis tool doesn't do it the "classic" way, it doesn't use the dedicated carry logic and instead use more LUTs to implement a 5 input - 4 output combinatorial logic and is not especially clever about it since it uses like 8 LUTs to do it ... All I want is a plain old carry-ripple adder in 4 LUTs ... And if possible I'd like to avoid having to instanciate everything by hand ... Thanks, SylvainArticle: 91581
hi a quick question I have and microblaze in Virtex4 (EDK 7.1 SPx), the system has several GPIO instances it all works OK until I try to add "PULLUP" on the second GPIO port, then there will be several DRC errors complaing that OLOGIC_OFF1 must have signal on CLOCK pin. I see no difference between the 2 GPIO instances in my system, but on one of them the IOB PULLUP can not be used, or it seems so. any ideas for workaround ?? AnttiArticle: 91582
Sylvain, Which synthesis tool are you using? Also, if you could you post a brief example of your code it might help you get an answer. Cheers, Syms.Article: 91583
I am using MultiLinx to program my XC2V1000 thru JTAG connector. I got TMS, TCK, TDI, TDO correctly, but unable to find the 3.3V and GND. Without this 3.3V, I can detect devices on two out of three JTAG ports on my board, and I need the third port to work. I am applying a 2.5V on the PWR & GND of the SelectMAP(?) connector on my Multilinx and it drew 0.9A power. I am unable to find another power supply to make 3.3V now. :( What can I do with this situation? ThanksArticle: 91584
Sylvain Munaut wrote:
>Hello,
>
>
>When implementing a 4 bits up/down counter on a Xilinx FPGA,
>the synthesis tool doesn't do it the "classic" way, it doesn't
>use the dedicated carry logic and instead use more LUTs to implement
>a 5 input - 4 output combinatorial logic and is not especially clever
>about it since it uses like 8 LUTs to do it ...
>
>All I want is a plain old carry-ripple adder in 4 LUTs ... And if
>possible I'd like to avoid having to instanciate everything by hand ...
>
>
It does this because it is faster than the carry chain. The carry chain
incurs a relatively large propagation time penalty for getting on/off
the chain. For anything less than about 7 bits (varies by tool and
version of the tool), an adder is inferred without the carry chain. I'm
not aware of any way to force it other than instantiation.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 91585
fad wrote:
> Does FPGA Adv be have Linux support or not?
Don't know, but emacs vhdl-mode does and is
much more useful. And free.
> I have to install modelsim and leonardo spectrum on linux machine
> separately as well.
Modelsim runs well an linux, but requires a floating license.
Leo has no linux support. Precision does, but requires
a new license.
-- Mike Treseler
Article: 91586
aj wrote:
>I am a student and a novicee for FFT... can any one tell me how to
>start with implementing Fast Fourier Transform on xilinx virtex pro. i
>know there xilinx core generator which can do... but i want to do it
>for floating point....
>any help for this starter... would be highly appreciated...
>i am getting lots of info, but there is nothing that is convincing
>me...
>IF any one can tell me the steps how to atleast start with this project
>thanks in Advance
>Peace
>
>
>
Start at the algorithm level. look at the math that has to be done, and
then figure out what the digital circuit
to do that math should look like, then finally tailor that circuit to
the FPGA's resources. Even at the algorithm
level, there are many ways to do the fft, some are better suited to a
hardware implementation than others.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 91587Hello everyone, I am trying to implement ethernet MAC on a fpga using vhdl. I have a transmit module which generates the ethernet frame and transmits to the PC through the ethernet cable. The ethernet frame consists of preamble, sfd, destination(MAC), source(MAC), length,data,crc. I am using ethereal to detect this frame I definitely think that my crc is right. But i am not able to detect any frames in the ethereal. I understand that by default ethereal has been set to detect ethernet frame of layer 3 or above. But the ethernet frame which i am sending is layer2. How do i change my options in ethereal so, that i can detect this type of frame. AshwinArticle: 91588
I use ISE7.1 last service pack. It's for a SRL based FIFO and I need it
to be small. Currently, it can run at 400 MHz (post P&R) but I don't
need it that fast but if I could win a few slice ...
Here is the code :
srl_addr_move <= srl_write xor srl_read;
srl_addr_nxt <= (srl_addr - 1) when srl_read = '1' else (srl_addr + 1);
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
srl_addr <= (others => '1');
elsif srl_addr_move = '1' then
srl_addr <= srl_addr_nxt;
end if;
end if;
end process;
Article: 91589Which kernel are u using...I have been trying to get a custom kernel on the ml-310 since many months and still I am not successful...Anyways I ported 2.4 and 2.6 without PCI support , but with PCI, I could compile the kernel but I couldnt get it to boot... -- ParagArticle: 91590
"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote in message news:1131552462.713930.323890@z14g2000cwz.googlegroups.com... >I use ISE7.1 last service pack. It's for a SRL based FIFO and I need it > to be small. Currently, it can run at 400 MHz (post P&R) but I don't > need it that fast but if I could win a few slice ... > > Here is the code : > > srl_addr_move <= srl_write xor srl_read; > srl_addr_nxt <= (srl_addr - 1) when srl_read = '1' else (srl_addr + 1); > > process (clk) > begin > if rising_edge(clk) then > if rst = '1' then > srl_addr <= (others => '1'); > elsif srl_addr_move = '1' then > srl_addr <= srl_addr_nxt; > end if; > end if; > end process; > Sylvain, I'm confused. For a FIFO the read and the write counters only need increase. Are you implementing a stack or LIFO? I do concur with Ray. The implementation your synthesis tool has chosen is probably the fastest solution for the reasons he's outlined. Cheers, Syms.Article: 91591
Well, a changing the signals to 8 bits makes what I want and it still works at >360 Mhz wich is good for me ... I guess, I will instanciate itArticle: 91592
It's a synchronous FIFO based on the SRL16 based element and has only a
depth of 16.
So I have only 1 counter that tells where to read inside the SRL16.
When I write a new data, it's inputed into the SRL16, so that I need to
increment the address I read to stay on the same data. When I read a
data, I must decrease the pointer to read the next data (time-wise).
And if I read and write at the same time, the counter must not move.
SRL16
/--- Data input
__V__
|____|
|____| <- --- srl_addr (where to read)
|____|
|____|
| |
.......
Article: 91593Noway2 wrote: > I would recommend Altera. They provide very nice development tools on > the web for free. If you are looking at the 9500 series, from Brand X, > I would suggest looking at the Max7000 series. Having used both, I > highly prefer the Altera. I'm familiar with the Xilinx 9500 series, but not with the Altera Max7000 series. Out of curiousity, why do you "highly prefer the Altera" ? -Dave PollumArticle: 91594
Maybe, you could tell us what are the characteristics of your FFT: -clock frequency -FFT size -Input Data size and format(signed or unsigned) -Coefficient size and format. I know Techway distribute FFT QinetiQ IP :http://www.techway.fr/pdf/quixilica/quixilica_high_throughput_fast_fourier_transform_core.pdf RegardsArticle: 91595
Terradestroyer@gmail.com wrote: > Strange request but I'm looking for an fpga board that pretty much only > has an fpga (perferably xilinx because i've only worked with xilinx so > far) a prom and just a whole lot of i/o pins that are easily > accessible. > > I've done all i can on my protoboard (digilent spartan 3 board) and now > i need to move to a more finished device. Problem is designing such an > intricate pcb (espically with bga) for someone who hasn't done bga > stuff before but requires many i/o pins and have never done a board > more than 2 layers is leaving me a little challenged. So I'm hoping a > small board that will give me most of the I/O's in headers would be > available, but as of yet I haven't found any. > > Does any know any that exsists? > > Thank you > Keith Wakeham You may want to take a look at the BurchEd B5-X300, which uses a Spartan-IIE (300K gates), and has lots of headers. It's US$226. The web site doesn't show dimensions for the board, so I don't know how big it is. (http://www.burched.biz/b5x300.html) -Dave PollumArticle: 91596
I recommend to start with the MontaVista Linux Preview Kit for the ML300. It can be downloaded from http://www.mvista.com/previewkit free of charge. The web pages I pointed you to are based on the MontaVista Linux 3.1 Pro edition. The previewkit is the same as far as the kernel goes but does not have the advanced development tools (Eclipse, etc). - Peter beeraka@gmail.com wrote: > Which kernel are u using...I have been trying to get a custom kernel on > the ml-310 since many months and still I am not successful...Anyways I > ported 2.4 and 2.6 without PCI support , but with PCI, I could compile > the kernel but I couldnt get it to boot... > > -- > Parag >Article: 91597
ashwin wrote: > Hello everyone, > I am trying to implement ethernet MAC on a fpga using vhdl. I have a > transmit module which generates the ethernet frame and transmits to the > PC through the ethernet cable. > The ethernet frame consists of preamble, sfd, destination(MAC), > source(MAC), length,data,crc. I am using ethereal to detect this frame > > I definitely think that my crc is right. But i am not able to detect > any frames in the ethereal. > I understand that by default ethereal has been set to detect ethernet > frame of layer 3 or above. > > But the ethernet frame which i am sending is layer2. How do i change > my options in ethereal so, that i can detect this type of frame. > > Ashwin Ethereal will pick up any type of ethernet frame regardless of the layers contained therein. Have you verified your CRC against a known good frame? Are you using the right type of cable (crossover or straight-through)? AlanArticle: 91598
"Philip Freidin" <philip@fliptronics.com> wrote in message news:kjp2n1hrhl6jvmldnbapl8mjcd3hs0v202@4ax.com... > > While this may not be what you want to hear, you may be better off > figuring out your desired function, and starting a new design with > current products. This is not easy either, as you probably have > existing boards, and everything runs at 5V . There are no current > products that will fit into the old footprint of the 3020A, and > almost none of the current products tolerate 5V. > The bad thing is that we need a last production batch of 500 pieces for spare parts, the project is dead already for some time ...Article: 91599
I would recommend that you stick with the Xilinx CPLD. The 9500 family is a nice family. We have developed several products with this device. I would also highly recommend doing the project in VHDL. You could also consider outsourcing it to someonw who might be interested in a little side job. An experienced engineer would be able to put this out in no time.
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