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<snip> > PS we have also an Avnet FX board (LX25) I idid order it the minut it was > announced, it was the FIRST V4 board announced as 'available' - first Avnet > did delay about 6 months !!! then when I got the board only to find out that > XMD does not suport usb cable and Virtex 4!!!! so I was not able todo any > EDK system debugging on that board. The board itself works also with usb > cable I think, the issue was only with the combination of V4+usb cable+edk > xmd Does anyone know if using XMD over the USB cable (specifically the newer Platform USB Cable from Xilinx) is possible these days? I wasn't sure if you were only referencing your first experience Antti. I just picked up a ML403 with the Platform USB cable, and am hoping to be able to debug over XMD with it...on Windoze,that is... Thanks, JohnArticle: 90801
Austin Lesea wrote: > Since we wrote this, IEEE owns the copyrights, and we can no longer > distribute the paper. Not true. The IEEE copyright poolicy states that "Upon transferring copyright to IEEE, authors and/or their companies have the right to post their IEEE-copyrighted material on their own servers without permission, provided that the server displays a prominent notice alerting readers to their obligations with respect to copyrighted material and that the posted work includes an IEEE copyright notice." As Xilinx employees are authors and co-authors of quite a number of papers, a collection - maybe on the XUP homepage - would be nice. Kolja SulimmaArticle: 90802
OK, now I'm confused... If, apropos of nothing, Peter says the FIFO depth in the Virtex-4 devices are exact powers of 2, I'd be inclined to believe him. If I factored in that he designed the "crucial asynchronous empty arbitration logic" for said FIFOs, any remaining doubts would surely vanish. If however, I woke up in a sweat in the night, suddenly unsure of the depth of Virtex-4 FIFOs, I'd probably go and read the User Guide before posting anything here... Cheers, RobinArticle: 90803
Ah, i'd be careful probing the configuration signals while the device is programming-Make sure you have the scope set up so that the impedance of the Probe is not going to unduly effect the quality of the signals on the board. From what you say it sounds like the probe termination is interfering with the signals you're scoping. it can happen if you have slow probes, i.e. old stuff, or if you have the termination of the scope set to something untoward, (50-Ohms would probably kill your config) anyways, even if it looks great on the scope, you might be making some standing waves later down the line. HTH Ben <nithin.pal@gmail.com> wrote in message news:1129738420.486603.327530@o13g2000cwo.googlegroups.com... > Hello, > > I am a newbie to the group and FPGAs in general. We have a board with > XC3S1500 FPGA on it. We use the master serial mode to configure the > FPGA using a platform flash (PROM) with the FPGA providing the CCLK > (confg rate -50). For debug reasons we also have the confg. signals > going to a POD header. > > We see that sometimes when we probe the CCLK on the POD header the FPGA > fails to configure. On the scope , we could see the sequence of INIT > going high, CCLK going active (clocking), DONE being low and after some > time, the INIT goes high, the CCLK stops clocking but the DONE pin does > not go high. We have 330 ohm pull-up on DONE pin. > > If i remove the probe from the CCLK pin on the POD header the board > starts-up with successful configuration. > > I was wondering if anybody in the group has seen such behaviour before > or may be the experts in the group could guide me on the possible > issues involved. > > Also, sometimes I have also seen that as the INIT goes low, CCLK goes > high but does not begin to clock . In this case, a configuration > failure is obvious. So, is this a problem with the chip not being > consistent? > > > Thanks a lot in advance > > Regards > Nithin >Article: 90804
Some body please advice me in this issue as i am still wondering aout what to do ???Article: 90805
Kim, thank you for that clarification. That means I was right in considering any simulation of metastability-causing asynchronous clocking impossible. There is no substitute for creativity, circuit analysis, some deep thinking, and experimentation. All of that we have done to verify the metastable behavior of our flip-flops, and to verify the behavior of our asynchronous FIFO in Virtex-4. Obviously, one can always simulate the effect that a given metastable delay has on the rest of the circuitry, but one cannot simulate the origin of the metastable delay. Peter Alfke, Xilinx ApplicationsArticle: 90806
Hi, I am trying to use Coregen to generate a single port memory with its content initialized. I defined a memory with depth 16 and width 8. In the options, I chose the following .coe file to initialize the contents: -----------------------------code starts------------------------------- ; This .COE file specifies initialization values for a ; block memory of depth=16, and width=8. In this case, ; values are specified in hexadecimal format. memory_initialization_radix=16; memory_initialization_vector= ff, ab, f0, 11, 11, 00, 01, aa, bb, cc, dd, ef, ee, ff, 00, ff; ---------- code ends -------------- When I tried to generate this code, the following error occurs: ERROR: sim - Invalid commmand: CSET coefficient_file = C:\Coregen Memory\data_new.coe WARNING:encore - Error whilst reading C:\Coregen Memory\rob_memory.xco I don't know what's wrong with this. Any help would be appreciated. Robert.Article: 90807
<john.orlando@gmail.com> schrieb im Newsbeitrag news:1129895423.936566.210780@g43g2000cwa.googlegroups.com... > <snip> > > PS we have also an Avnet FX board (LX25) I idid order it the minut it was > > announced, it was the FIRST V4 board announced as 'available' - first Avnet > > did delay about 6 months !!! then when I got the board only to find out that > > XMD does not suport usb cable and Virtex 4!!!! so I was not able todo any > > EDK system debugging on that board. The board itself works also with usb > > cable I think, the issue was only with the combination of V4+usb cable+edk > > xmd > > Does anyone know if using XMD over the USB cable (specifically the > newer Platform USB Cable from Xilinx) is possible these days? I wasn't > sure if you were only referencing your first experience Antti. I just > picked up a ML403 with the Platform USB cable, and am hoping to be able > to debug over XMD with it...on Windoze,that is... > > Thanks, > John > not sure. the usb cable works. the xmd works. V4 is supported. just at the time I needed them together they did not together. I think there have been no edk service packs since that so possible the issues still remains. in that case you would need to wait for EDK 8.1 update scheduled for dec 2005. maybe I am wrong and there is a patch fix for the issue, after getting frustrated at first attempts I have had no more time to play with that board. AnttiArticle: 90808
Hi, There is no need to simulate metastability. The RTL simulations are functional. All conditions of empty and full have been verified with directed and random behavior over long simulations with clocks sliding past each other. The FIFOs are as assymetrical as 128 bits in and 16 bits out and with clocks as different as 37.125 MHz and 100 MHz. The simulations have been proven correct in the lab on Virtex-2 Xilinx FPGAs running for several hours with real data. ModelSim PE's code profiler said that time was being spent mostly in the Xilinx FIFOs. RAULArticle: 90809
"Lionel Damez" <damez@lasmea.univ-bpclermont.fr> wrote in message news:ee910b9.1@webx.sUN8CHnE... > Mike Treseler wrote : > > Try a simpler case first. Maybe four microblazes? > > > > > I have already tested simpler designs with less microblazes and place and > route was successful with each of them. > > What I want to know is how much processors can I put in a virtex4 device. > I hope to put 32 in the largest devices. > > Trying with 16 processors, I encountered this place and route problem. > > The par tool outputs "CHANGE PLACEMENT or EASE CONSTRAINTS". > > Is it possible to do that with the EDK interface, or do I have to export > my design to Projet Navigator(ISE)? > > Thanks, Lionel Damez The tool is telling you that 16 won't fit ... I doubt there is much you can do other than reduce the number of instances of the processor. MikeArticle: 90810
Bevan Weiss wrote: > Getting single cycle high speed multipliers is a very challenging > prospect, and one which much research is still ongoing. Actually, if you cannot do full custom circuit optimizations (e.g. because you do standard cell design or because you are using LUTs in an FPGA) swapping wires is the only possible structural optimization. All other multiplier transformations can be reduced to swaps. An extremely nice property of swapping wires is, that it can be done after placement. This is such a huge advantage that we were able to beat sophisticated multiplier generators with a simple greedy algorithm when applying it after placement: http://eis.eit.uni-kl.de/eis/research/publications/papers/iccd04.pdf Kolja SulimmaArticle: 90811
vssumesh wrote: > Hi all, > Thinking of a 5 stage pipeline risc. > 1. fetch > 2. decode > 3. execute > 4. buffer > 5. write back > The result of execution stage is buffered at the +ve edge of the > buffer cycle. And this works if we enable the data forwarding method. > And the next instruction will get the updated values from the buffer > register at its execution stage. And the buffered data will be placed > to memory ony at the write back stage. > My doubt is if this is true where will we buffer the output of the > execution stage of the second instruction at the +ve edge of its buffer > cycle as the buffer is still holding the result of the previous > instruction. > I am a beginer to these type of things. This is similar to the ARM9 > pipeline. Whats their way of tackling this situation. Really its a bit strange that a complete beginner would jump into the deep end when in the past we went through some baby steps 1st. Are you doing this in Verilog/VHDL or C or some other academic cpu design tool? You do have the Hennessy-Patterson book right (from MKP)? Not actually in this book but one radical suggestion I have is to throw this horrible design model away and do a multi threaded architecture. You replace one set of cycle sucking performance limits with a much simpler thread engine that ultimately boils down to a 2 or so bit counter in state control. Such a design can run around 2x as fast as the single threaded design at circuit levels, and that 2x can be traded back for many simplifications to get back same speed but with much less hardware. Definitely you don't need register forwarding, or hazard logic detection logic in MTA designs, but you do end up with a couple of threads for the end user to deal with. Many more issues there. John gmail or transputer2 at yahooArticle: 90812
I am not too far into the ML403 board yet. It is a very sophisticated multilayer board. I was able to get all the demos to work. Nothing has blown up so far. I did feel that the point-and-click hand holding dropped off rather suddenly after running the demos, but I will attend an Avnet class next week for basic training. I am working presently on an add-on board to bring Camera Link signals from two line scan cameras into the board. Brad Smallridge aivision.comArticle: 90813
Michael Schuster wrote: > news.hinet.net wrote: > > > Yes it comes with a linux and solaris cd too > not mine, only device files for all plattforms (or I didnot see it > anyhow ...) > > Michael > -- > Remove the sport from my address to obtain email > www.enertex.de - Innovative Systeml=F6sungen der Energie- und Elektrotech= nik For the record, mine sadly came with only win32 binaries. Can anyone at Xilinx explain why this is? Is it just to save the cost of a few CDs? Are Linux users still considered second class users? I have to stoop to running it on VirtualPC on my Mac. Not exactly speedy. Other the above problem, I find the Spartan-3 starter kit to be a tremendous value. Thanks to Xilinx for providing some really powerful tools and a decent hardware platform for next to nothing. cheers, aaronArticle: 90814
I am using the EDK to configure a sytem using the MicroBlaze core. We have several user IP's that are used to perform various functions. One of those is a 3-wire serial interface module. It provides several different interfaces to whatever chipset we are talking to (each one uses a different protocol). The data line in this module is used as both input and output. Everything is configured correctly up to the top level. I have one port that I route up through my verilog into the user logic and out to external pins. This port is used as a debug signal. I can connect internal signals at the lowest level of my code and bring them out externally. This has worked for us in the past with no problem. However, for this particular build of the module, if the debug port is being used and brought out externally, then there appears to be an extra capacitative load presented on the serial data interface line. Writing to our parts is fine, but reading back does NOT work when a scope probe is attached. We found that a 1 to 0 transition in the readback data is actually read in as a 1. Removing the scope probe works fine. If I take the debug port out completely (not routed externally) then everything is fine. The connections are all still there interanlly, but just not routed to an output port. I can't figure out what the XST tool is doing that is adding extra load to that particular signal. All I am doing is adding a little more logic to the module. The timing analysis is fine. It is actually being clocked 1/3 slower than rated. I have tried registering the debug output as well and that hasn't worked. Is there a way to tell what is going on here, or does anyone have suggestions? Like I said, it works, but this behavior scares me. I would like to know EXACTLY what the tools are doing. thanksArticle: 90815
Its interesting to learn about the disabling the unused inputs - how are the inputs disabled? I am assuming a FET. In that case wouldn't there still be some leakage especially in a 90nm process?Article: 90816
Kolja, Interesting. I knew I could distribute it internally, but fram what you say, it appears I may also publicly post it on the Xilinx web site (external world)? That doesn't seem right to me... Austin Kolja Sulimma wrote: > Austin Lesea wrote: > > >>Since we wrote this, IEEE owns the copyrights, and we can no longer >>distribute the paper. > > > Not true. The IEEE copyright poolicy states that > > "Upon transferring copyright to IEEE, authors and/or their companies have the right to post their IEEE-copyrighted material on their own servers without > permission, provided that the server displays a prominent notice alerting readers to their obligations with respect to copyrighted material and that the posted > work includes an IEEE copyright notice." > > As Xilinx employees are authors and co-authors of quite a number of papers, a collection - maybe on the XUP homepage - would be nice. > > Kolja SulimmaArticle: 90817
Mike Lewis wrote: >Lionel Damez wrote: > > Is it possible to do that with the EDK interface, or do I have to export > > my design to Projet Navigator(ISE)? > The tool is telling you that 16 won't fit ... I doubt there is much you can > do other than reduce the number of instances of the processor. > > Mike - The logic for 16 microblazes fits. - A single microblaze is routable. - The communication between the prozessors is systolic. From that information I would say that floorplanning is very likely to yield a routable design. This means that you tell the placer beforehand were in which reagion of the chip it should put each processor and the corresponding memory. You can not do that from EDK AFAIK. Kolja SulimmaArticle: 90818
bobrics wrote: > Hi, > > I am trying to synthesize hardware which changes one values in a > register array at rising and falling edge of the clock. Basically I am > trying to synchronize different actions on different edges of the clock > and write, for example, signal1 to reg(1)(31 downto 0) and signal2 to > reg(2)(31 downto 0). The line with *** gives an error. > > if reset='1' then > -- initialization of reg > ***elsif rising_edge(clock) and (write_flag = '1') then > reg(CONV_INTEGER(unsigned(reg_address1))) <= signal1; > elsif falling_edge(clk) and (write_flag = '1') then > reg(CONV_INTEGER(unsigned(reg_address2))) <= signal2; > end if; > How about using two separate 32-bit registers, reg1 and reg2, instead of reg(1) and reg(2). You need to use 2 processes. The process for reg1 would use the rising edge of the clock, and the process for reg2 would use the falling edge of the clock. -DaveArticle: 90819
Jim Granville wrote: > luc wrote: > > Jim, > > > > If I'm not mistaken, the datasheet of the 4000Z provides both static > > power, and a graph showing the dynamic power requirements. > > There is even a complete technical note about the power coefficients. > > Yes, but I was refering to the Web hoopla, > [ There are NO relative claims in the Data sheets ] > see > http://www.latticesemi.com/products/cpldspld/ispmach4000z.cfm > > and not a squeak on mA/MHz ? > > [Aug-27-04 is also getting a tad long in the tooth ? ] > > ISTR a quick compare did confirm that mA/MHz number was not so great.... > > -jg Take another look at that web page. In the "Family Member Selector Guide" table the 6th column is labeled "Typical Standby Current (A)". I'm gueesing they meant uA, not Amps! -DaveArticle: 90820
Thank you for the pointers. Do you cover any of this in your forthcomming book? /rickArticle: 90821
On Mon, 17 Oct 2005 22:37:09 GMT, Philip Freidin <philip@fliptronics.com> wrote: >Ok, here goes: Why are you trying to do this with an FPGA ??? A very good question. >Look at products from: > >National Instruments: http://www.ni.com/ >Data Translation: http://www.datatranslation.com/ >IO Tech: http://www.iotech.com/index.html >Omega: http://www.omega.com/prodinfo/dataacquisition.html >Measurement Computing: http://www.measurementcomputing.com/ >Dataq Instruments: http://www.dataq.com > >Get started at $25 http://www.dataq.com/194.htm Excellent advice, probably the most important kick-start the OP received - unless he's doing something really unusual. Most of the usual industrial plant-control applications are well covered by standard hardware these days. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 90822
On Wed, 19 Oct 2005 09:25:12 -0700, Tim Wescott wrote: > Jeorg's question on sci.electronics.design for an under $2 DSP chip got > me to thinking: > > How are 1-cycle multipliers implemented in silicon? I don't know how they do it this days, but I do know that with a whole shitpot load of adders, you could do it in n propagation delays, where n is the width of whichever operand you arrange to come in sideways. I almost drew a schematic. You have a set of adders as wide as operand "A", and its inputs are operand "A" and the "latest" partial product - and its outputs go to another bank of adders whose other inputs are either "A" again or 0, and so on - the other operand, "B", would be presented down the side of the array, deciding which partial products get added to and which don't. The LSB, of course, gets sent out as "product", and the carry is the MSB of the next partial product. They form a parallelogram. I just fired up that Xilinx S/W to see what it's got in the way of symbols, and it already has a 16-bit adder. With 16 of them, and 256 AND gates, I could build a 16 x 16 multiplier that would have an answer in about 16 or 17 propagation delays. :-) <Rich fires up Xilinx ISE...> OK, it's gonna be a day or so. Please be gentle, it's my first time. :-) Thanks! RichArticle: 90823
Hi all, I have this xess board which has a tool to initialise an SDRAM with data. I have 16-bit numbers that I want to load into the SDRAM. The tool needs .hex/.mcs format and I read that I need the promgen to convert from .bit to .hex. My question is how to convert from this .dat file (which is my input data file) to the .bit file. Does anyone know of such an utility? Otherwise can someone explain wat the .bit file contains? ThanksArticle: 90824
Hi Kedar, To generate a post-synthesis netlist along with an SDO timing file, use the following commands: quartus_map <project name> -c <revision> quartus_tan <project name> -c <revision> --post_map --zero_ic_delays quartus_eda <project name> -c <revision> --simulation --tool=<toolname> --format=verilog When you generate the VO/VHO and SDO file using the quartus_eda executable, you will receive the following warning message: Warning: Standard Delay Output File (.sdo) contains estimated delays -- run Fitter first to annotate SDF Output File with exact delays After you perform your post-synthesis simulations, Altera recommends that you complete a full compilation and regenerate the VO/VHO and SDO files to include exact delays of your design for gate-level timing simulations. A full compilation in the Quartus II software includes synthesis, placement and route. For more information, please refer to the following solution http://www.altera.com/support/kdb/2005/10/rd10192005_405.html If you do not want to wait for a full place-and-route, you can use the Early Timing Estimator, in the Quartus II software, to perform a preliminary place-and-route in a fraction of the time of a full place-and-route. After the Early Timing Estimator, you can generate a simulation netlist with the early timing estimates. Albert Chang Senior Applications Engineer Altera Corporation kedarpapte@gmail.com wrote: > Hi Morpheus And Ben > > Thanks for your reply but my confusion is > 1. In Quartus tool Full Compilation means complete implementation and > that generates both .vho and .sdo file for me after fitting and place > route. > > 2. But is there any option to generate a back anotated post synthesis > .vhd file or .vho file with a .sdo file after gate level synthesis > > so after simulating the post synthesis .sdo file can we get only gate > delays in simulation and not the net or routing(wire) delays > > thanks > regards > Kedar
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