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fecs@usa-dot-com.no-spam.invalid (fecs2) writes: > i need help for a Simple PWM Spartan 3, i dont know how to activate > the spartan3 board help I useusally activate my Spartan 3 board using a 5V 1A power supply. The board has regulators that produce the lower voltages needed by the FPGA chip. Your board might be different; I'd recommend checking the documentation.Article: 90776
fecs2 wrote: > i need help for a Simple PWM Spartan 3, i dont know how to activate > the spartan3 board help > I doubt there's a significant amount of help available for the board. Perhaps just some interfacing information, such as which pinouts go to where etc. This shouldn't be too important until you get to the point of actually targetting your design. You can still do all of the core creation. Perhaps you should specify which parts of the process you're having trouble with, might actually get you some answers then.Article: 90777
I think the problem is that the lame-ass Windows emulation libraries have limited environment variable space. A typical BSD env is too long. It works for me when I start it up with a minimum environment, like so: $ env - PATH=$PATH HOME=$HOME sh $ . settings.sh $ ise Darius wrote: > Still trying to figure out why my file dialogs complain about long > paths though..Article: 90778
Tim Wescott skrev: snip > The original question was for an under-$2 DSP chip capable of doing > audio frequency stuff, including FFTs. I'm not the fellow who asked; it > just sparked a tangential thought in my head about why there isn't some > intermediate step on the way to a full-speed DSP. > I never have to buy stuff so I don't know anything about prices, but philips recently announced a couple of 70MHz ARM7TDMIs in the 2$ range, it's not DSPs but at 70MHz and one cycle per 8bits of 32*32->64bit multiply it'll do some dsp -LasseArticle: 90779
I believe that connecting any unused i/os to gnd instead of leaving them floating helps in static power dissipation in generally any fpga. I am referring to the static power dissipated by the connection matrix in the fpga. Am I correct? Thanks. -sanjayArticle: 90780
Rick North wrote:
>Hi all,
>
>I have a FIR filter which I would like to make a RPM of to see what all
>the fuss is about. But I don't know the appropriate approach. I
>understand that I can get a RPM from the Floorplaner, but then I guess
>I have to place the logic by hand my self. Is there a way to write it
>in VHDL? Do anybody have a "how-to.." reference design to share?
>
>All the best,
>Rick
>
>
>
You can embed the placement info in the VHDL, but that doesn't alleviate
the need to do the placement by hand, in fact you will likely go back
and forth between your VHDL and the floorplanner to get the placement
correct. For a one-off RPM, it is easier to just do it in the
floorplanner and be done with it. For something that is going to be
reused, it makes sense to put the placement in the VHDL.
To put it in the VHDL you need to add RLOC attributes:
attribute RLOC: string;
attribute RLOC of u1:label is "x2y3";
The placement in VHDL has to go onto xilinx primitives, which means your
design is structural instantiation rather than RTL.
If you just want to preserve the placement PAR automatically generated,
you can use the floorplanner to capture that placement and write it out
to an RPM.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90781langwadt@ieee.org wrote: > Tim Wescott skrev: > > snip > >>The original question was for an under-$2 DSP chip capable of doing >>audio frequency stuff, including FFTs. I'm not the fellow who asked; it >>just sparked a tangential thought in my head about why there isn't some >>intermediate step on the way to a full-speed DSP. >> > > > I never have to buy stuff so I don't know anything about prices, but > philips recently announced a couple of 70MHz ARM7TDMIs in the 2$ > range, it's not DSPs but at 70MHz and one cycle per 8bits of > 32*32->64bit multiply it'll do some dsp TI have just volume-released their 100MHz FLASH controllers, start at sub $5, so not quite a $2 target, but these have FLASH(not ROM) and include 12 bit 6Msps ADCs, a 150ps resolution PWM, and CAN bus 150ps PWM is a challenge even for FPGA .... http://focus.ti.com/docs/pr/pressrelease.jhtml?prelId=sc05231 The sub $2 Philips devices have quite low code sizes, but they could do some 'audio frequency stuff'... -jgArticle: 90782
You would be right,if the inputs were really floating, acting an antenna... Xilinx (and probably others too) has high-impedance weak pull-up resistors (really transistors) per default on each pin. Unless you have very strong crosstalk, those unused pins stay High, and cause no undesired dynamic or static power consumption. Peter Alfke from home.Article: 90783
Did you mean pulse-width modulator? Beware of unexplained TLA (Three-letter acronyms) Peter AlfkeArticle: 90784
I would like to buy an ML401 Board from Xilinx. Would somebody give me some indications about this card? Does it have any specific problems? I'd never used such cards, what is forbidden to do with it? I don't want to burn it the first week :)Article: 90785
Peter Alfke wrote: > You would be right,if the inputs were really floating, acting an > antenna... > Xilinx (and probably others too) has high-impedance weak pull-up > resistors (really transistors) per default on each pin. Unless you have > very strong crosstalk, those unused pins stay High, and cause no > undesired dynamic or static power consumption. > > Peter Alfke from home. Some other manufacturers effectively disable unused inputs -- no possibility of totem pole current so no extra current. Of course, take care of some special pins that depending on the manufacturer may not follow the standard rules -- they are special pins! For instance, check all the clock pins. And most importantly in life, ground TRST* hard (for those devices that have that optional JTAG pin). TRST* has an internal pull-up resistor so that by default the TAP controller is not forced to stay in the TEST-LOGIC-RESET state and a bit of noise or an upset can result in bad things. -- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, WestworldArticle: 90786
thats what im using. I just explained the structure of it.Article: 90787
"Pete" <padudle@sandia.gov> writes: > I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC > (TEMAC) of the Virtex4 FX parts. EDK offers several options for Ethernet MAC > type but they are all soft MACs. EDK 7.1 has a wrapper for the hard MAC. And there's an update for that wrapper downloadable from the Xilinx web site. EricArticle: 90788
Thanks. When I posted I was pretty steamed was probably venting more than looking for help. But, here's some of the details. I should have been more specific. It's the is the Virtex-4 LX60 Eval Board. I don't actaully know where the issue(s) is/are. It could be in one of at least three places. 1. A board level issue. 2. The Platform Cable USB used to interface to JTAG 3. Xilinx's Impact software. I have been attempting basic communication to the board. Nothing fancy. I tried using Impact's "Initialize Chain" command to see if the software could find and recognize the devices (PROM and Virtex-4) on the JTAG chain. I get the following: Identifying chain contents ....read count != nBytes, rc = 20000015. read failed 20000015. '1': : Manufacturer's ID =Unknown INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. '2': : Manufacturer's ID =Unknown INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. '3': : Manufacturer's ID =Unknown INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ... And it goes on telling me that there's a huge number of UNKNOWN devices on the board I have also tried checking the ID_REGISTER values with Impact and got the following. // *** BATCH CMD : ReadIdcode -p 2 read count != nBytes, rc = 20000015. read failed 20000015. ERROR:iMPACT:583 - '2': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '2': Device IDCODE : 00000000111111000000001110010000 INFO:iMPACT:1579 - '2': Expected IDCODE: 00000001011010110100000010010011 write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. ... Which looks to me like the communication is just Garbage. I have tripple checked and the Board's Jumpers are all positioned correctly for JTAG. I have also opened up a Web Case with Xilinx, but am still waiting to get some more information back. If anyone has some insight I'd be very thankful to get some feedback. Thanks!Article: 90789
Excuse me ... It wasn't the ML401 but ML403 with Virtex-4 FX12Article: 90790
CMOS wrote: > thats what im using. I just explained the structure of it. > You explained that you were using an IBUF and an OBUF and that the number of connections I listed - the .I, .O, .T, and .IO - fell one showrt for your parts. Parts plural. Are you 1) using an IBUF primitive with .I and .O ports and an OBUFT primitive with a .I, .O, and .T port or are you 2) using a single IOBUF primitive with the _oen connected to the .T, the _o connected to the .I, the _i connected to the .o and the pad connected to the .IO. YOU NEED ONE PRIMITIVE - the IOBUF If you use the IBUF and the OBUFT primitivers, it will be like trying to convince the tools that two latch primitives make up a flop. From before: sda_pad_o to IOBUF.I sda_pad_oen to IOBUF.T sda_pad_i to IOBUF.O pad to IOBUF.IO And also from before: if i do that there will be an output ( out put of the input Buffer ) without any connections. ( the IO buffer im talking about is made up of one OBUF and one IBUF.). You cannot make your own IOBUF from the OBUF and IBUF primitives. Use the IOBUF primitive as declared at: http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/lib/lib0234_220.html Here the primitive has two buffers but it DOES NOT have an IBUF and an OBUF primitive. It is a single primitive itself. Dogspeed.Article: 90791
hi, how i can prevent netgen (ise7.1i) from renaming std_logic_vector ports like this X1_CON(7 downto 0) -> X1_CON_0_Q, X1_CON_1_Q, X1_CON_2_Q, .... any ideas ? -- Dr.-Ing. A. Wassatsch Max-Planck-Institut für Physik München email : wassatsch@mppmu.mpg.de Dept. Electronic Tel/Fax.: ++49+89 32354 271/444 Föhringer Ring 6 mobil : 0170 92 05 801 80805 Munich (Germany)Article: 90792
"Waage" <chris@ednainc.com> schrieb im Newsbeitrag news:1129865780.677607.22780@z14g2000cwz.googlegroups.com... > Thanks. When I posted I was pretty steamed was probably venting more > than > looking for help. But, here's some of the details. > I should have been more specific. It's the is the Virtex-4 LX60 Eval > Board. > > I don't actaully know where the issue(s) is/are. It could be in one of > at least three places. > > 1. A board level issue. > 2. The Platform Cable USB used to interface to JTAG > 3. Xilinx's Impact software. > > I have been attempting basic communication to the board. Nothing > fancy. > I tried using Impact's "Initialize Chain" command to see if the > software could > find and recognize the devices (PROM and Virtex-4) on the JTAG chain. > > I get the following: > > Identifying chain contents ....read count != nBytes, rc = 20000015. > read failed 20000015. > '1': : Manufacturer's ID =Unknown > INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. Hi Chris, 1) what avnet told you first was good and correct, its EASIER to get FPGA tools to run on Windows then Linux. It just is like that. 2) Impact is not software. its nightmare. 3) USB Cable as the 'newest' one seems still to have most problems. So you fixed issue 1 what is under your control, but now you are stuck with an nightmare called impact and usb cable. There is unfortunatly little you can do: 1) jtag chain debugging, with impact, measure signals... boring timeconsuming most likely will only give you info that everything seems to be ok and SHOULD work 2) try use ChipScope to check the chain, the low level drivers/access of chipscope and impact are different, sometimes the other one works ! 3) open webcase, and be ready to prepare lot of impact log file, they will ask for them, or to speed up add the log files to your webcase to speed up the issue. 4) make more steam to avnet I could suggest to try our jtag software but as usb cable protocol is prop. we dont support it (only parallel cables) As the readback was something else than contstan 0or1 then I think the board is not completly dead, and that the jtag chain actually is scannable, so its some tool issue. make sure the usb cable is updated, well in our case 1 of 2 usb cable stopped to work completly after firmware update, but in that case you can return it, or open another webcase Antti PS we have also an Avnet FX board (LX25) I idid order it the minut it was announced, it was the FIRST V4 board announced as 'available' - first Avnet did delay about 6 months !!! then when I got the board only to find out that XMD does not suport usb cable and Virtex 4!!!! so I was not able todo any EDK system debugging on that board. The board itself works also with usb cable I think, the issue was only with the combination of V4+usb cable+edk xmdArticle: 90793
Tim Wescott wrote: >> Jeorg's question on sci.electronics.design for an under $2 DSP chip got >> me to thinking: >> >> How are 1-cycle multipliers implemented in silicon? My understanding is >> that when you go buy a DSP chip a good part of the real estate is taken >> up by the multiplier, and this is a good part of the reason that DSPs >> cost so much. I can't see it being a big gawdaful batch of >> combinatorial logic that has the multiply rippling through 16 32-bit >> adders, so I assume there's a big table look up involved, but that's as >> far as my knowledge extends. >> >> Yet the reason that you go shell out all the $$ for a DSP chip is to get >> a 1-cycle MAC that you have to bury in a few (or several) tens of cycles >> worth of housekeeping code to set up the pointers, counters, modes &c -- >> so you never get to multiply numbers in one cycle, really. >> >> How much less silicon would you use if an n-bit multiplier were >> implemented as an n-stage pipelined device? If I wanted to implement a >> 128-tap FIR filter and could live with 160 ticks instead of 140 would >> the chip be much smaller? If you leave out FFT-based multipliers which are only benefitial for really large mutliplicands (a few hundred bits) you need to perform N^2 1-bit additions for a multiplication. These N^2 1-bit adders can be arranged in different ways called for example array multipliers or wallace tree multipliers to change the critical path and the layout. But we proved that they all can be transformed into each other just by swapping wires around. http://eis.eit.uni-kl.de/eis/research/publications/papers/iccd04.pdf The only thing you can do about area is trading off area for delay. You can forexample reuse the same N adders over N clock cycles. Pipelining does not save area. But it can increase performance a little. You can cut the critical path in half by adding N pipeline stages. (Beware that without pipelining while you perform N additions of N bits the length of the critical path is only O(N) for all multiplier architectures achieved by reordering) The multiplier is a large part of the CPU core, probably the largest in a DSP, but the area of most processor chips including DSPs is dominated by caches and other memory like reordering buffers, shadow registers, TLA buffers, etc. Kolja SulimmaArticle: 90794
Hi all, Thank you for all your suggestions. I have both ISE and EDK7.0.1. At first, I don't have any conception about how to connect my IP CPRE with the plb or opb bus. I just know one side is the ip core written in VHDL, and the other side should be some driver written in C. I have read the drivers of Uartlite and spi, but I still couldn't be clear about how to connet the two sides. How to get the .tcl files? The articles suggested by Kunal are very good. I am reading them at present. I will discuss my thinking with you later. Thanks to all of you! AthenaArticle: 90795
Hi, Do you guys know the difference between the following two instructions: LW 0(R1), F2 LW F2, 0(R1) Are they equivalent? If yes, then I assume on a regular 5-stage pipeline, R1+0 will be executed in EX (ALU) stage and load to F2 will occur at MEM stage. Is that correct to assume? What I really need to know here is that for both commands, EX stage takes care of 0+R1 Thank youArticle: 90796
Peter Alfke wrote: > Raul, this may just reveal my ignornce, but anyhow: > > How do you model metastability, which needs sub-femtosecond resolution? > How do you model that an asynchronous FIFO generates its EMPTY flag in > time, even under the most adverse timing conditions between the two > incoming clocks? > Those have been things that kept me awake at night :-( Usually in RTL simulations you don't even want to model things like that. Most important thing is to get fast simulation times for the whole design. And at least in the past Xilinx models were overly complex for pure RTL simulations, and usually own simulation models were needed to get the speed. The correctness of the async fifos must come from the design, reviews etc. It's impossible to simulate all the cases. Of course with netlist simulations timing accurate models are needed, but that is small part of simulations. That is usually done to check timing constraints and synthesis bugs (if formal verification tools are not part of the users toolset). Asynch portions are almost impossible to simulate. Nowadays there are also formal tools that check clock domain crossing correctness etc. Those tools can even inject errors during simulation that could be caused by metastability (the places are found by the formal portion). --KimArticle: 90797
Thank you, I'll think how I should go around it To test this code, I am using a lower-end cheap and old FPGA (apex II).Article: 90798
Hi Pete, I'm working with a Virtex4FX12 at moment, and I'm designing a dual port Ethernet MAC (10/100/1000) for a VOIP application. I started with the XAPP 807 that shows how to use ultracontroller2 with a single MAC to have a simple webserver based on uIP (uIP is a simplified TCP/IP stack). (a TCP/IP stack in less then 16K... that is the size of the instruction cache of the PPC405) It works!! I was impressed to see how easy was to implement the webserver. I really reccomend you to start from here :-) At moment I'm designing the TCP/IP stack in HDL.... If you don't like this idea then I suggest to use: the plb_temac (from Xilinx Platform Studio go on Project->Add/Edit Cores... and add the plb_temac) Have a look at the PDF documantation . good luck! FrancescoArticle: 90799
Mike Treseler wrote :
Try a simpler case first. Maybe four microblazes?
I have already tested simpler designs with less microblazes and place and route was successful with each of them.
What I want to know is how much processors can I put in a virtex4 device. I hope to put 32 in the largest devices.
Trying with 16 processors, I encountered this place and route problem.
The par tool outputs "CHANGE PLACEMENT or EASE CONSTRAINTS".
Is it possible to do that with the EDK interface, or do I have to export my design to Projet Navigator(ISE)?
Thanks, Lionel Damez
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Compare FPGA features and resources
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