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ashwin wrote:
> 2)How do i view on my PC , what ethernet frames are being sent from the
> fpga board.
http://www.ethereal.com/
-- Mike Treseler
Article: 90951
Thirty hour and several hundred dollars later, it's working great. Details in my
blog entry:
http://whats.all.this.brouhaha.com/?p=149
Article: 90952Hi all, I am trying to get into FPGA development, just wonder besides "FPGAs are fun" (http://www.fpga4fun.com/WhatAreFPGAs.html) and opencores.org, is there any other sites I can find good introductary materials? My main interested is CPU cores and floating point units for DSP/control type of applications. Thanks in advance.Article: 90953
Good come back... i like it :)Article: 90954
Jan Panteltje wrote: > On a sunny day (Tue, 25 Oct 2005 11:15:57 -0700) it happened Phil Hays > <Spampostmaster@comcast.net> wrote in > <patsl15a4mb135g980b8mqt1t66snnukgf@4ax.com>: >>Depends on location. For the USA as a whole, I just checked >>Monster.com and found the following posted jobs: >> >>113 hits for "fpga and verilog" >>148 hits for "fpga and vhdl" >> >>Looks to me like VHDL is still more popular. > Google: > 'fpga vhdl sucks' 2460 hits > 'fpga verilog sucks' 1340 hits > ;-) "vhdl and verilog" = 79,100 google hits "verilog and vhdl" = 54,600 google hits :) -- Mike TreselerArticle: 90955
Eric Smith wrote: > Thirty hour and several hundred dollars later, it's working great. Details in my > blog entry: > http://whats.all.this.brouhaha.com/?p=149 The only thing I did not see you try, which I am going to try next is using Wine on my dual Opteron system to see if things will work. In my case I just want to use the free Webpack. Obviously, I cannot use the free Xilinx download for Linux as it is only 32-bit *sigh*. I can get the parallel cable driver working, but the interesting thing will be to see if Wine will let Webpack see it correctly. That is my next thing to try. If that does not work, I'll do the VMWare thing. Curse you Xilinx for not preparing better for 64-bit. *argh* -SteveArticle: 90956
Im just beginning with FPGAs too, and just completed my first design. I used the schematic entry capability of Quartus, and didn't have any problems really. I did read somewhere that if possible you should use the lpm_megafunctions in lieu of some of the old TTL parts you might be tempted to use at first. That is a very well founded piece of advice! Some of the implementations of the older parts are not as optimized as the lpm equivs (I'm guessing) and got caught with some very intermittant and glitchy outputs until I remembered reading that, and taking it to heart. Then, everything got much much better! Good luck! Len GArticle: 90957
I recommend "HDL Chip Design" by Douglas Smith (if I'm not mistaken). It shows both VHDL and Verilog in action. I think reading that book is a good start to know VHDL and Verilog concurrently. Other book, I've read "Fundamentals of Digital Logic with VHDL Design" from Brown and Vranesic. it gives a smooth transition from board application design to ic design. but it's for beginner to intermediate reader I think. -ivan-Article: 90958
Hi, Len! I was finishing my first design on jan 2005, and I was using Altera UP1X (yeah, it's a bit old). I really addict in FPGA (compared to uC), but unfortunately no job in IC design outside my campus (or it's hard to find). if I may know, what did you design on FPGA? -ivan-Article: 90959
A digital video graphic inserter for 601 video. It was a great learning experience, and I very much enjoyed it. I teamed up a Cyclone and a PIC18F8722. It was great to have the ability to shift a chore from software to hardware or visa-versa. I will check out the books you've mentioned! L.Article: 90960
Hi, for lots of information and links about vhdl and cores have a look at http://tech-www.informatik.uni-hamburg.de/vhdl/ Have fun Eilert ppirrip schrieb: > Hi all, > > I am trying to get into FPGA development, just wonder besides "FPGAs > are fun" (http://www.fpga4fun.com/WhatAreFPGAs.html) and opencores.org, > is there any other sites I can find good introductary materials? My > main interested is CPU cores and floating point units for DSP/control > type of applications. > > Thanks in advance. >Article: 90961
> As also indicated, an interesting question to ask is why do you want to > configure your CPLD every time you power up? Is your design pattern > changing all the time? Is this some sort of demo board? Not exactly, maybe i'm being a little ambitious... I'm just doing some research into making a test apparatus for some designs using various CPLDs. The idea was to make a discrete piece of hardware that the UUT would be plugged into, and then a little report saying whether it passes or fails - this needs to be rugged, and industrialised. Using boundary scan I can only verify about half the board, and the less critical half at that, so i'm wondering whether I could use one bit file to run a sequence of test vectors in conjunction with the external tester, and then once all the interconnects are established as correct, load the proper bit file. I guess you're wondering why I don't just go for a PC running impact... well i'm trying to avoid having to maintain a PC with the manufacturer, including the OS, the test software etc etc. BenArticle: 90962
aholtzma@gmail.com wrote: > There is no download location for EDK on linux or anything else (as far > as I can tell, I would love to be proven wrong). I've installed the win-bin yesterday with latest wine for suse. Well it seems to work out of the box here... Michael -- Remove the sport from my address to obtain email www.enertex.de - Innovative Systemlösungen der Energie- und ElektrotechnikArticle: 90963
Robert wrote: > This is not an answer to your query but rather a question to you: > > How did you include the generated FIFO from Core Generator in your > project? (I am assuming you're using ISE) > > Did you have to compile the cores seperately? Or did ISE take care of > it? I use ISE7.1. FIFO Generator works exactly like other cores. I just clicked on "Add new Source...". When I used ISE6.3 I was not able to get FIFO Generator work, it always generated empty cores!Article: 90964
Peter Alfke wrote: > If your 32 MHz clock is really derived from, and thus synchronous with, > the 128 MHz, then I would treat this as a synchronous FIFO. In the final design they should be synchronous, I should get them from a DCM with a 64MHz input. Now I just create them in the testbench. Anyway I don't think this is the problem, the test I'm performing is very simple, first I raise the wr_enable, I wait for the FULL signal, and then I lower the wr_enable and after a little bit of time I raise the rd_enable. > Asynchronous means that you have no idea of, and no control over, the > phase relationship between the two clocks. And asynchronous FIFO > control is far trickier than synchronous, just because of the unknown > and shifting phase relationships, and the associated possible decoding > glitches and even metastability. Synchronism makes all this so much > easier. I understand that asynchronous FIFOs are more trickier than synchronous ones ... but I don't want to use a synchronous FIFO, the clocks relation is not fixed, their ratio could change in the future. So I'm just asking, is possible to store 16 words in a 16 words deep FIFO? Or "Deep N" means that I can only store N-1 words? Is this problem somehow related to the old asynchronous-fifo core behaviour? I remember that it let me chose only the length like 7,15,31,63 ... i.e. (2^N)-1.Article: 90965
hello all! :P
who can tell me how to realize cic decimate filter by FPGA?
best regard!
Article: 90966Nemesis ha scritto: [...] > Is this problem somehow related to the old asynchronous-fifo core > behaviour? I remember that it let me chose only the length like > 7,15,31,63 ... i.e. (2^N)-1. OK, I just read carefully the summary screens that appears at the of the FIFO customization ... When you chose an asynchronous FIFO it says: "Write Depth:15 Read Depth:15. Actual FIFO depth differs from specified depth in this configuration". So this is a "limit" of the asyncrhonous FIFO.Article: 90967
> 1)My ethernet frame consists of > Preamble, destination address, source address, length/type, data, > padded zeros, crc > The destination and source address i am using the physical MAC address > and not ip addresses, is it okay? > They are the Physical MAC addresses, for now you can forget about IP addresses. You can choose your FPGA MAC address (Source Address in the Tx side of your MAC), for example "12.34.56.78.9a.bc". Ethereal will pick up all the packets from your MAC if you set it in 'promiscous mode'... -- I.U. Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O)Article: 90968
>So I'm just asking, is possible to store 16 words in a 16 words deep >FIFO? Or "Deep N" means that I can only store N-1 words? It's possible, but not simple. Keeping track of 0 to 16 words in a FIFO requires 17 states. That won't fit in 4 bits. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 90969
I can. But I can't be bothered. However, I know a friend who's much more helpful than I am. Mr. Google! He gave me these links for you, bless his cotton socks. http://www.xilinx.com/ipcenter/catalog/logicore/docs/cic.pdf http://www.xilinx.com/xcell/xl38/xcell38_48.pdf http://users.snip.net/~donadio/cic.pdf Cheers, Syms. ;-) p.s. Apologies for the sarcasm. I guess from your email address you're posting from China? Is Google blocked there? I heard the government got upset because Google Maps stopped calling Taiwan "a province of the People's Republic of China". Here's a BBC link about it, which I guess you won't be able to see either. http://news.bbc.co.uk/1/hi/world/asia-pacific/4356276.stm "zhl_gs1980" <zhl_gs1980@yahoo.com-dot-cn.no-spam.invalid> wrote in message news:qdadnfUyNYmtpsLeRVn_vA@giganews.com... > hello all! :P > who can tell me how to realize cic decimate filter by FPGA? > > best regard! >Article: 90970
Hi All, i request somebody who worked on or having knowledge about Physical interface for PCI express(PIPE) to reply for my below query. i am trying to understand the PIPE interface for my application. INTEL has no where specified the electrical interface of the PIPE if we use the PHY as an external component and PCI express link layer in FPGA. when i spend hours together to find this, finally i got one device from PHILIPS PX1011a which supports SSTL2 standard. is there any standard electrical interface defined for this kind of application? if it is, can anybody can share the link to those documents to me. thanks in advance S.RANGA REDDYArticle: 90971
Brad Smallridge wrote: > Thanks Peter. > > If you need master-slave ISERDES to get 7 bits, are there any layout issues, > pin assignment issues that would cause problems or crowding? I only need 16 > ISERDES total. If you need a slave ISERDES, you 'borrow' the ISERDES from the other IOB in the tile. In that case, the other IOB has no ISERDES available. If you have single ended inputs, you couldn't have two 7-bit ISERDES on 2 input pads in the same tile. If you have LVDS inputs you're OK because the 2 input pads form 1 internal signal that can feed to the 2 ISERDES in master-slave configuration. It's pretty easy to see if you make up an example design, place and route then look at the results with FPGA editor. --- Joe Samson (jsamson@) PixelVelocityArticle: 90972
Hello! I instantiated SDRAM memory in an EDK project, but I don't know what I have to do in order to boot from it. I want to store my instructions and data into it. Does anyone can help me? Thank you! MelissaArticle: 90973
Symon wrote: > > He gave me these links for you, bless his cotton socks. > Might those be Argoogle socks? Also, the online sample chapter of "Multirate Signal Processing" (harris/Prentice Hall PTR/2004) just happens to be the CIC chapter: http://www.phptr.com/articles/article.asp?p=361985&rl=1 Brian Symon wrote: > I can. But I can't be bothered. However, I know a friend who's much more > helpful than I am. Mr. Google! He gave me these links for you, bless his > cotton socks. > http://www.xilinx.com/ipcenter/catalog/logicore/docs/cic.pdf > http://www.xilinx.com/xcell/xl38/xcell38_48.pdf > http://users.snip.net/~donadio/cic.pdf > > Cheers, Syms. ;-)Article: 90974
Be careful of this... even in promiscuous mode, it will only pick up what is on it's network segment. So if you connect your FPGA board to a switch, it may or may not get to your computer if the MAC is wrong. because a switch knows what MAC is associated with what port, it may only transfer packets to the computer whos MAC address matches the computers. Connect the board to the compute rwith a crossover and you should be ok - Ethereal can capture everything in p. mode. You can start anywhere down from the MAC layer (ie: just mac addresses), and go all the way up to TCP and it should transmit fine. That's the whole beauty of Ethernet.
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