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On a sunny day (Mon, 07 Nov 2005 16:00:40 -0500) it happened Eli Hughes
<emh203@psu.edu> wrote in <dkof9p$1f9o$1@f04n12.cac.psu.edu>:
><quote>
>In my_view(C) if you cannot see '{' and '}' or align it, or 'wire',
> > or 'module' or ANY language specific word, then you are not suited
> > as programmer.
></quote>
>
>This is somewhat arrogant. Yes, I can use some crappy UNIX text editor.
> But I choose to use something to make like life a little easier. Why
>would I not want to use new tools? My vision is bad enough. I like
>having things highlighted. It also makes things easier for others to
>look at code that they are not familiar with.
>
>Thats like saying that a Doctor is a a good Doctor is he Doesn't use the
>same tools from 30 years ago. Ya, they worked at the time but there are
>much better tools now that make operations easier.
OK I respect your view, but I also respect my view and experience and that
even more ;-) So, you do not seem to get what I am hinting at :-)
Some observations:
This syntax highlighting / coloring has nothing to do with vision sharpness,
we have even less color sensors in the eye then BW, and these need more light
too, so reading color takes more brain cycles! It has to do with the way the
neural net processes the data.
In the even older days (of editors) there were no full screen editors, and
one worked at a line at the time while you hade a VERY clear picture in your
head of the whole source (text)!
When we get really decadent and use a MS product with very small windows with
graphics that 'pre-types' half a C++ function for you (Visual Studio), then
yes that may seem easy, especially to the beginner.
However *I* personally fuind it annoying when using these windows in windows
in windows that you constantly need to scroll even on a 19 inch monitor..
I use Linux and old fvwm (window manager)with 9 rxvt terminals and 9 virtual
screens.
Random access, HUGE characters, you'd like it!
Then use a makefile, drop that GUI.
No, I am not a GUI hater, no way, write so many GUI programs, but it needs
to be done in the right way.
GUI is handy for SOME applications, like moving modules around perhaps in
a diagram, and buttons, sliders, graphs, what not.
But not for text oriented code.
For TEXT oriented code you need (are best of with) a TEXT oriented editor,
no mouse, no, set mouse traps, get rid of these.. Fingers on the keyboard.
I admit I use cut and paste.
Use best of both worlds.
But if you CANNOT have the code picture in your head, forgat about programming.
Hey I use 'search' in my sources, no scrolling..... be a sharp shooter,
eye that ONE detail, find it, write it / fix it.
And have the big picture always in your head, else let go and do not
write until you are clear about that.
Article: 91526Henry wrote: > I'm looking for some suggestions/recommendations with CPLD's and > development software. Henry, three things to consider 1. You should be able to use parts of the libraries shipped with the software 2. Lattice, Altera are some other very "famous" CPLD manufactors with a similar programming interface 3. you should think of learning VHDL. In my expierience the learning curve is very fast and once you're used to it, you will be much faster than drawing... Michael -- Remove the sport from my address to obtain email www.enertex.de - Innovative Systemlösungen der Energie- und ElektrotechnikArticle: 91527
I would recommend Altera. They provide very nice development tools on the web for free. If you are looking at the 9500 series, from Brand X, I would suggest looking at the Max7000 series. Having used both, I highly prefer the Altera.Article: 91528
rha_x wrote:
>You should be able to. You'll probably have to code your own application
>though. You can readback that data through a JTAG interface, or even
>internally, using OPB-HWICAP core. There is a tool called JBITS, but I'm
>not sure if it supports V2, and it is written in java.
>regards,
>alonzo.
>
>
>
Be aware that reading back the BRAM contents while the BRAM is active in
the design can lead to corrupted contents. Do your readback before you
start the clock.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 91529Hello, What tools do I need for changing an outsourced dising from a 3020A to a 3030A Xilinx device (the 3020A is obsolete). I only have a XNF netlist available. ThanksArticle: 91530
"Vanheesbeke Stefaan" <svhb@pandora.be> schrieb im Newsbeitrag news:xb2cf.42389$vo1.2039857@phobos.telenet-ops.be... > Hello, > > What tools do I need for changing an outsourced dising from a 3020A to a > 3030A Xilinx device (the 3020A is obsolete). > > I only have a XNF netlist available. > > Thanks > > I just checked that I can compile an 'Logic Assembler' source file until .BIT using Foundation 1.5i for the P&R I guess that you can run Foundation implementation on the XNF as well. The 'ISE Classics' that are available from Xilinx website do not support 3030A AnttiArticle: 91531
How could I implement a bus in my Spartan3 to let it communicate thorough a 16bit wide, 100MHz bus with a Blackfin DSP? Thanks, MarcoArticle: 91532
"Marco" <marco@marylon.com> schrieb im Newsbeitrag news:1131461408.810685.93980@g14g2000cwa.googlegroups.com... > How could I implement a bus in my Spartan3 to let it communicate > thorough a 16bit wide, 100MHz bus with a Blackfin DSP? Thanks, Marco > its very easy. 1 Open BlackFin DSP datasheet in Acrobat 2 Start Xilin ISE, New Project 3 Proceed implementing your bus interface simple as that! Sorry Marco, there is no answer to your question. It all depends how you want to connect the BlackFin bus inside the FPGA and that is something you must know - we dont. AnttiArticle: 91533
Read my message again. I do that. Kunal Shenoy wrote: > Right-click on the project name and make sure 'Mark to Initialize > BRAMs" is ticked. > > Kunal@XilinxArticle: 91534
First of all I want to appologise if this is a bit off topic, but I think the people with the best expertise will be in this group. I'm currently doing some research into Intellectual Property for SoC designs and just wanted to get a feal for the things that are important to people who actually purcahse/use IP. For example support from the vendor after sale seems to be important from people I have already spoken to. I'm also interested in things that you think are missing from IP that would help integrate that IP into a design i.e. better test information, quality of the design etc. Any comments on this would be greatly appreciated. Kind Regards KemalArticle: 91535
> I detected soem time ago that, at least on EDK/ISE 7.1, the bram init > values are not updated automatically. You need to Tools/Clean/Bits > inside the EDK, compile the program, and then Update Bitstream with > Processor Data OK, I did that which got rid of the Nothing to be done for 'init_bram' message, but now I get quite a few messages indicating that microblaze bootloop program is being compiled, not the flash hello program that I made active on the Applications pane. Is there somewhere else I need to indicate where the Platform Studio is suppose to go and look for the software that it needs to compile? Brad Smallridge aivisionArticle: 91536
There is a difference between making a project 'active' (what you said in your message) and marking it for initialization to BRAM.Article: 91537
Put the data busses out of the process. Write it as a concurrent statement and use one output_enable(OE) signal to control the inout bus. inout_bus <= out_bus when OE = '1' ELSE (OTHERS => 'Z'); in_bus <= inout_bus; In this way you write to the INOUT only when OE is 1. The in_bus is always reading the INOUT.Article: 91538
> [largest fabric in small package among fpga families] Thanks Jim and Antti for clearing that up. -- JecelArticle: 91539
> There is a difference between making a project 'active' (what you said > in your message) and marking it for initialization to BRAM. Aha! Thank you. You would think that a little green arrow pointing down toward BRAM icon would mean that the BRAM was going to get loaded. Also, only one of these can be loaded this way? I had to turn off the initialization of BRAM to the bootloop program otherwise I got an error about headers overlapping. Are there any point and click descriptions of this Platform Studio or a description about what the compiler optimation and other features do? Brad Smallridge aivisionArticle: 91540
If a project is 'active' but not 'marked for initialization to BRAM' then the green arrow is marked with a red cross. If you do mark it for initialization the red cross goes away. The bootloop program and your program are linked separately and take up overlapping address spaces (boot section, text section etc). So there is contention between the data to be placed at a particular location in memory and that is the error message you are getting if 2 projects are initializd to BRAM. There is a manual for XPS online. As for the compiler, it is gcc, so the gcc manual should be a good place to find what different optimization levels do. Kunal@XilinxArticle: 91541
hi.. i am tryin to interface the pico blaze from SPRATAN III to a computer and hvin some trouble..can ny 1 guide me/??Article: 91542
In article <xVPbf.1529$xD6.92174@news.xtra.co.nz>, Bevan Weiss wrote: > > Just doesn't work that way unfortunately. The large fabric requires a > large chip package to contain it. If you were to reduce the number of > pin outs, the it would actually require an even larger chip package, as > you would now have to add additional multiplexers etc to control the > routing to the pins. You've got an FPGA to help you route stuff... :) -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 91543
In article <qhhdao850d.fsf@ruckus.brouhaha.com>, Eric Smith wrote: > > The problem is that you don't save any significant cost by having the > same size package with fewer balls or pins. So if the die size requires > a package 20mm on a side, it may as well have more than 350 balls, even > if some customers don't end up using all of them. There is a cost associated with me trying to acquire the resources and planning necessary to have a 1000+ pin FPGA mounted, routed and fed. On the other hand, 144 pins, or even 208 pins in a quad flat pack is pretty much doable... Now, my naivitee(sp?) may show here, it may be that the power requirements for feeding such a beast can simply not be reliably met by the (T)QFP type of package... -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 91544
Keith, I've just done two different boards with a bga each, and they are my first boards that are greater than single layer ;). There are a lot of electrical advantages that you lose if you go to a pin header design. Honestly, BGA's aren't as hard as everyone thinks they are. Just follow the recommendations for footprint layout in the datasheet, and use a manufacturer with 5/5/10 tolerances. I've pinned out well designed BGA's [~256 pins] on two layers that way [didn't fab that one, impedances didn't match up], and less well designed BGA's on 4-6 layers. Get a professional fab house to mount the BGAs for your prototype, usually costs us ~50 Canadian for bake + mount [on bare boards]. You'll also probably need gold immersion, depending on what the people who mount your BGA's want. --David CarneArticle: 91545
Hi, I am doing some experiments and I need to find out the total wirelength of my design. I am using Xilinx ISE 6.1 for doing place and route, but I cannot see anyway I can find this information. Does anyone with experience with this tool know if it is possible to find out total wirelength? Thanks, AnupArticle: 91546
Hi Anthony, The reason tri-state enable FFs are not included in AD[31:0], C/BE#[3:0], PAR's IOB is for timing reason. Xilinx (and many FPGA-based PCI IP cores) LogiCORE PCI is taking advantage of Address Stepping (Mentioned in PCI Specification) allowed by PCI Specification. Address Stepping allows the device to turn on data bus signals ( AD[31:0], C/BE#[3:0], PAR) multiple cycles (Usually one cycle to minimize performance hit.) before it needs to be turned on, giving very good timing margin. If Address Stepping wasn't allowed, yes, those tri-state enable FFs will have to be included in the IOBs, and will also have to rely on unregistered PCI control signals to turn on the data bus signals, making it very difficult to get the PCI IP core to meet PCI's setup time. (Particularly 66MHz PCI where the setup time is only 3ns.) Kevin Brace Anthony Ellis wrote: > I notice that the Xilinx PCI32 core for Spartan 3 does not map the tristate enable FF's for the AD(x) lines to IOB's. Is there a good reason for this? The only adantage I can see for this is to try and force the AD(x) data FF's to contain the newest data before the IOB's are enabled. > > Anthony. -- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.Article: 91547
Do you want wirelength in microns? Picoseconds? Why would this information help you? <anup@ece.ucsb.edu> wrote in message news:1131480824.352210.248050@g14g2000cwa.googlegroups.com... > Hi, > > I am doing some experiments and I need to find out the total > wirelength of my design. I am using Xilinx ISE 6.1 for doing place and > route, but I cannot see anyway I can find this information. Does anyone > with experience with this tool know if it is possible to find out total > wirelength? > > Thanks, > AnupArticle: 91548
What kind of help do you need? I am using a Spartan-3 board as well and I connect it to the parallel port of the computer using a Xilinx Parallel IV cable. You can use a Parallel III or a USB cable as well.Article: 91549
aydin3w@gmail.com wrote: > Is it possible to drive global clock routing networks with an internal > signal on a Virtex-E FPGA? > > I am trying to develop data/strobe enoding on an Virtex-E FGPA. It is > required that data and strobe signals are XORed to obtain a clock > signal. Then this clock signal will be fed to other logic in the FPGA. > Therefore I need to use the XORed signal to use as a clock signal. > > Thanks for your replies. Virtex-E is similar to other Xilinx devices and has internal global clock buffers (BUFG) that can be driven by logic such as an XOR gate as well as an external pin. In fact routing to the global buffer is not even restriced to the global clock input pins, but for external clock sources the input delay is significantly less on these global pins. If your signals to be XOR'd are external, you don't gain this advantage by using the global clock inputs as the routing must first go to a LUT using non-global resources. In this case it is better to use non-global I/O pins to feed your XOR gate. It is also possible to run logic signals to a DLL in ther Virtex-E parts. You may need to set the XIL_MAP_ALLOW_ANY_DLL_INPUT environment variable for this. Also this only works for free-running clocks that meet the minimum/maximum frequency limits of the DLL. So if your XOR clock doesn't form a constant clock of fixed period you can't take advantage of the DLL. Good luck, Gabor
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Compare FPGA features and resources
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