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I was hoping there *may* have been a manner to use all the flash. I'd thought that the flash memory must be oversized in typical cases - for example if in a design I specified all the the memory blocks to be ROMs (is this possible?) then their initialisation data would have to arrive in from that flash area....?however if I instead used only RAMs then that flash memory must be sitting there unused? Maybe it was just too fiddly for lattice to expose any "left over" flash memory - but even if it was a modest interface (SPI would do!) then that would be quite useful (for some designs).Article: 91926
Hi Andrew, Andrew wrote: >>Learn how to write makefiles, and use gnu make. Then don't worry >>about Xilinx GUIs again, excluding the tools that should be graphical: >>FPGAeditor and FloorPlanner. > > Got any info/links/tutorials on the best way to learn to use makefiles > and GNU make to build FPGAs? This is exactly what EDK does. Take a look at the Makefiles and associated synthesis scripts that are generated to build a MicroBlaze / PPC project. It exercises pretty much everything you'll need to know - xst, ngdbuild, map, par, bitgen,... JohnArticle: 91927
lesnleung@gmail.com wrote: > We are working on a proect using NIOS which needs to talk to the PC > Via a serial port, However we found that the core supplied by AILTERA > seems to work at slow speed only even the core is runing at 50mhz, it > seems that it cannot run faster than 2400baud, Any body has silmiar > problems? We are trying a UART with FIFO but still struggling with > it. You could try using the opencores 16550. Having a wishbone interface it wraps nicely into a SOPC component... Regards, MarkArticle: 91928
I'm looking for a good book that goes deeply into theory about transmission lines and crosstalk in high speed communications systems. If anyone has any good references, please let me know. I have the book High-Speed Digital Design by Howard Johnson, which has some good stuff in it, but I'm looking for another reference which gives detailed attention to crosstalk. In particular, how crosstalk is modelled, and methods for mitigating crosstalk. Thanks in advance, Michael.Article: 91929
Seemes strange to me. The UART supplied in SOPC builder, under Communication, on my system can be configured for up to 115200bps. It might not have a FIFO, but it supports streaming, so you should be able to connect it to your own FIFO.Article: 91930
Jim Granville wrote: > Amazing to see light bulbs exempt - given their short life spans, and > direct waste flows, shouldn't they be first in the line ? Didn't you realize that lightbulbs are slowly becoming out of fashion ? Where reliability matters, such as in traffic lights, they already have been replaced by LEDs. LEDs take giant leaps in terms of brightness and cost, Together with rising prices for power, it won't take a decade to replace most light bulbs. ReneArticle: 91931
Hi,
I am using Lattice FPGA EC10.
I have two pins "IIC_SCL_2V" and "IIC_SDA_2V" which I want to define
as opendrain outputs so that my external processor can drive the lines
to LOW.
In my VHDL top level file I define the following
ENTITY top IS
PORT ( ...
IIC_SCL_2V : INOUT std_logic;
IIC_SDA_2V : INOUT std_logic;
....
);
END top;
ARCHITECTURE struct OF top IS
.=2E.
BEGIN
IIC_SCL_2V <=3D '1';
IIC_SDA_2V <=3D '1';
END struct;
In the preference file I define OPENDRAIN option ON.
When performing synthesis the fitter changes the INOUT ports to
OUTPUTs.
Trying the following leads to the same result :
IIC_SCL_2V <=3D 'Z';
IIC_SDA_2V <=3D 'Z';
When trying to define two additional help output ports
the fitter changes the INOUT ports to
INPUTs so that the OPENDRAIN option is disabled again.
IIC_SCL_2V <=3D 'Z';
IIC_SDA_2V <=3D 'Z';
IIC_SCL_2V_HELP <=3D IIC_SCL_2V; -- IIC_SCL_2V_HELP defined as
OUTPUT in top level
IIC_SDA_2V_HELP <=3D IIC_SDA_2V; -- IIC_SDA_2V_HELP defined as OUTPUT
in top level
So how could I solve that problem ?
Thank you for your help.
Rgds
Andr=E9
Article: 91932Well are not exactly making money on that by the by the time you cost labour cost and packing cost of a decent box. If we were a catalogue company shipping hundreds or thousands of units a day then bringing down that cost would be possible. We are using a tracked service which isn't cheap and we would not do it any other way because of credit/debit card fraud. All in all if you don't like our shipping rates we do offer the option of shipping on customers own courier at their expense. Very few will do much better than the £10 we current charge. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Mike Harrison" <mike@whitewing.co.uk> wrote in message news:c8gnn1lfcl02lv8nqvdt2ei8tuhtdm2oas@4ax.com... > On Wed, 16 Nov 2005 14:16:01 -0000, "John Adair" > <removethisthenleavejea@replacewithcompanyname.co.uk> wrote: > >>For all of you that asked if we could do better on carriage we now have a >>low cost option for selected EEC countries. US and New Zealand may be >>added >>at a later date once we sorted out how duty collection would operate. >>Details are on the website on the relevant product pages. >> >>John Adair >>Enterpoint Ltd. - Home of Raggedstone1. The Low Cost XC3S400 Development >>Board. >>http://www.enterpoint.co.uk > > A tenner to the UK is still a bit steep....Article: 91933
Hi, I can suggest a user group hosted by cadence, spetraquest.com. You can post your queries out there regarding EMI issues and can get the answers from experts. Regards, FahadArticle: 91934
adnan.aziz@gmail.com wrote: > i everyone, > > i'm teaching a vlsi design class, and we're covering datapath this > week. > > we use weste and harris' new edition of "cmos vlsi design". it's a > great book; however, it doesn't discuss actual delays/area costs for > adders, multipliers, dividers, etc., and the other sources i've looked > at tend to be focused on asymptotics (O(log N) type analyses). > > does anyone know off the top of their heads what the actual delay/area > numbers are like on a modern FGPA for the following: > > - addition, multiplication, division > > - 16/32/64 bit > > - number of pipeline stages for these implementations. > > i'd also be interested in knowing correspondnig values for floating > point arithmetic, > > suggestions for survey articles would be welcome > > thanks in advance, > > adnan Area in a "modern FPGA" for arithmetic varies widely, due to the recent addition of dedicated blocks for multiply/accumulate functions. If you're only interested in functions using the FPGA fabric, your best bet is to use COREgen (or some other vendor's equivalent IP generator) to make the functions you want. The Xilinx version allows you to see the resulting coverage if you check the "Display Core Footprint" box in the dialog for the core. Most cores allow you to check off whether to use dedicated hardware if the FPGA family has it, the alternative being to generate the function using only the fabric (LUTs and flip-flops). The nice thing about the core generator is that you don't actually need to build the project to see the resource requirements. If you don't have ISE with COREgen, you can get some representative usage values from the IP function datasheets, mostly available at the Xilinx IP center.Article: 91935
I have no tristate enable signal available to define something like IIC_SCL_2V <= '1' WHEN Tristate_enable='1' ELSE 'Z'; IIC_SCL_2V_HELP <= IIC_SCL_2V;Article: 91936
In our lab we have a number of ml310s and use them for both PPC and MicroBlaze designs. For the PPC designs using the external DDR SDRAM that came with the board we experience no issues. However, the DDR when used with the MicroBlaze does not initially function correctly upon configuration and has to be reset using the CPU reset button, after which it works fine until the next configuration. This is true even for designs using the default BSB MicroBlaze design for the board. Upon initial configuration, MicroBlaze programs as well as XMD return junk when reading from the memory and the MicroBlaze will sometimes hang on write attempts, more so it seems at lower operating frequencies. The garbage read from the memory appears to vary slightly between consecutive reads. Again, everything works fine after a reset or two. Does anyone have any idea what could be causing this? Thank you in advance, StephenArticle: 91937
I am using version ISE7.1 and I have just come accross the same error message. here is the text vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv Optimizing FSM <FSM_0> on signal <state[1:2]> with gray encoding. ------------------- State | Encoding ------------------- 00 | 00 01 | 01 10 | 11 ------------------- failed to translate terminal to FCT $n0035[18] = If $n0017 Then $n0061[18] If $n0018 Then $n0063[18] If $n0019 Then $n0065[18] If $n0020 Then $n0067[18] If $n0021 Then $n0069[18] If $n0022 Then $n0071[18] If $n0023 Then $n0073[18] If $n0024 Then $n0075[18] If $n0025 Then $n0077[18] If $n0026 Then $n0079[18] If $n0027 Then $n0081[18] If $n0028 Then $n0083[18] If $n0029 Then $n0085[18] If $n0030 Then $n0087[18] If $n0031 Then $n0089[18] If $n0032 Then $n0091[18] If $n0033 Then $n0093[18] Default <u>0 --> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ So it seems very similar and I could not find neither the explanatio or a solution up to now. Hope someone can help! Erwan >Dear > >During synthesizing in XST of ISE 6.3, following error (?) is >encountered.... > >Does anyone have experience on this trouble? > >Thankyou for information in advance > >---------------- > >failed to translate terminal to FCT > >$n0133[7] = >If $n0243 Then $n0297[7] >If $n0245 Then $n0299[7] >If $n0247 Then $n0301[7] >If $n0249 Then $n0303[7] >If $n0251 Then $n0305[7] >If $n0253 Then $n0307[7] >If $n0255 Then $n0309[7] >If $n0310 Then address[7] >Default <u>0 >--> > >Total memory usage is 58984 kilobytes > > >ERROR: XST failed >Process "Synthesize" did not complete. > >Article: 91938
Nichael,
There are many books on E&M theory that detail the basis for calculating
cross-talk, but I am not sure that is going to help you at all.
Of more interest is calculating quickly the cross-talk coupling that you
actually have in your system?
To do that, it is a question of which tools to use.
A few simplistic formulas from a textbook will give you the theory, but
they will not be useful in finding what the actual cross-talk is.
A complete and accurate solution to any E&M problem can be found by
packages such as Ansoft's field solvers. Next on my list would be
Sigrity's modeling software. Cadence and Mentor both have signal
integrity packages which will extract parameters from your printed
circuit board, and report the cross-talk. One of my favorites is
Mentor's Hyperlynx which is a lower cost (and lower featured) version of
the more powerful (and capable) signal integrity tool suites -- and is
very easy to use.
Of course, spice has the W, T, and U transmission line models, and each
model is useful for different reasons. Not all model types are
supported by all versions of spice ('hspice' has them all).
For theory, I use Ramo, Whinnery, and Van Duzer "Fields and Waves in
Communications Electronics" only because I took the course from Whinnery
~30 years ago.
Austin
Michael Chan wrote:
> I'm looking for a good book that goes deeply into theory about transmission
> lines and crosstalk in high speed communications systems. If anyone has any
> good references, please let me know.
>
> I have the book High-Speed Digital Design by Howard Johnson, which has some
> good stuff in it, but I'm looking for another reference which gives detailed
> attention to crosstalk. In particular, how crosstalk is modelled, and
> methods for mitigating crosstalk.
>
> Thanks in advance,
>
> Michael.
>
>
Article: 91939You mentioned it's hard to look at the clock at the FPGA, but do you have any other FPGA pins that you can get to? Set up a simple toggle flip-flop to drive the pin and look at that. It will show you what the FPGA is seeing. If you get a nice square wave, the clock is getting in OK. If it isn't a perfect square wave, the input clock is bad. Try using a digital scope with infinite persistance turned on so you see a LOT of history. Else set the triggering to 'trigger on pulse less than N nsec'. John PArticle: 91940
ALuPin a =E9crit: > I have no tristate enable signal available to define something like > IIC_SCL_2V <=3D '1' WHEN Tristate_enable=3D'1' ELSE 'Z'; > IIC_SCL_2V_HELP <=3D IIC_SCL_2V; Open-drain are outputs, not inputs (an I=B2C interface should have bidir pins, though, but that's another problem). High-impedance has nothing to do with inputs. The usual way is to have an internal signal (called scl_out for example) that drives the pin's output enable: scl <=3D '0' when scl_out =3D '0' else 'Z'; NicolasArticle: 91941
From a 24 MHz input, the Xilinx DCM would provide a 100 MHz output (25/6 ratio) on the CLKFX outputs, not the CLK0 and CLK90 outputs. You would need to feed your 100 MHz clock into a separate DCM to provide the phase shifts. "prav" <praveen.kantharajapura@gmail.com> wrote in message news:1132200083.976139.272040@o13g2000cwo.googlegroups.com... > Hi all, > I have a doubt in application note XAPP224. > In my application the data is to be recovered at 100 Mb/s. > Now my question is should i use a 100 Mhz clock only to clock > the PLL, to derive > CLK0 and CLK 90 OR can i use a 24 MHZ clock as a input to my > PLL to derive CLK0(100 Mhz) and CLK90(100 Mhz with 90 degree) phase > shift. > > Regards, > PravArticle: 91942
Hi, Does somebody know DCM corner issues? My DCM is not running at very high clock rate (only 107MHz), so I don't think this issue is connected with XAPP685 application notes (http://direct.xilinx.com/bvdocs/appnotes/xapp685.pdf) This DCM is used with an DDR-SDRAM memory controller, and when I place it at X3Y0 instead of X2Y0, memory reading often fails (data are wrong). Thus the solution is not complicated, I just need not to use DCM X3Y0 but I would like to understand why it fails and if somebodyelse knows this problem. Thank you.Article: 91943
I think that CLK0 and CLK90 has the same frequency as the input clk. RegardsArticle: 91944
adnan.aziz@gmail.com wrote:
> i'm teaching a vlsi design class, and we're covering datapath this
> week.
> does anyone know off the top of their heads what the actual delay/area
> numbers are like on a modern FGPA for the following:
That might have to be a different class.
It seems to me that custom cmos design and
fpga design have very little in common
in terms of primitive elements.
-- Mike Treseler
Article: 91945Michael, I don't know a good book, but a few web sites were helpful for me, and may serve as a starting point. http://www.ek.isy.liu.se/courses/tsek35/files2004/3.wires.pdf http://www.bolton.ac.uk/mind/corep/sig-int/sig-int-1/lesson1.html#6 http://www.sp.se/electronics/RnD/reports/EMC/lccalc.pdf At http://www.sp.se/electronics/RnD/software/eng/LC-Calc.htm you can find a tool for computing the mutual inductance and capacitance matrices from conductor cross-sections. The matrices can be used with PSpice to simulate crosstalk. I experienced good agreement between the explicit formulas in the topmost reference, the simulations, and later the measurements at the PCBs. It appears that with the appropriate design style you can drastically reduce XT - to a point where it is of no concern any more. I have a bus of 36 single-ended lines, each wire being 0.1mm (4mil) wide and only 0.21mm apart from each neighbor (edge to edge), running strictly parallel for >30cm (12"). Rise time is <1ns (ALVCH). This appears to be a worst-case scenario, but XT never reaches critical levels. The important thing is to use a stripline configuration, in which inductive and capacitive forward crosstalk cancel out. Backward crosstalk can be controlled by series termination. Hope this is of use for you, cheers Gunter "Michael Chan" <mchan@itee.uq.edu.au> wrote in message news:newscache$5c83qi$qll$1@lbox.itee.uq.edu.au... > I'm looking for a good book that goes deeply into theory about > transmission lines and crosstalk in high speed communications systems. If > anyone has any good references, please let me know. > > I have the book High-Speed Digital Design by Howard Johnson, which has > some good stuff in it, but I'm looking for another reference which gives > detailed attention to crosstalk. In particular, how crosstalk is > modelled, and methods for mitigating crosstalk. > > Thanks in advance, > > Michael. >Article: 91946
<brassaro@iro.umontreal.ca> wrote in message news:1132178625.633742.197620@o13g2000cwo.googlegroups.com... > Forgot to mention that i am using EDK 6.3i. > Check the synthesis report for details, if you have not already done so. Sometimes errors don't appear inthe dialog but in the report for which there are various in ISE. Also, check to see if your connections are complete, perhaps none are recognized. If all fails try opening a web support issue with Xilinx. This can take time but the response often hits the heart ofthe problem. -AndrewArticle: 91947
"sjulhes" <t@aol.fr> wrote in message news:437b395e$0$10968$626a14ce@news.free.fr... > Hi ! > > I installed ISE and EDK 6.2i with SP3, and ISE as a stange behavior. > When I go through steps synthesis, P&R and .bit generation every thing is > ok. > If I launch impact or if I swap to another windows application and back to > ISE, all green marks go back to ? and ISE launches the wholel flow !!!! > It is a big waste of time ! > > Does anyone has a clue ? > > Just one point, there was a ISE 6.3 install on this computer which was not > removed correctly. > > Thank you. > > Stéphane. > > Try using the "Run All" option after right-clicking in iMPACT and see what happens. Could be that you have a corrupted version of ISE 6.2 for which later modules (i.e. ISE 6.3) are in your setup. I would uninstall everything from the Xilinx folder and reinstall from scratch, but saving your projects using the archive option. Also make sure you are using Win XP or 2K pro. -AndrewArticle: 91948
Cher Sebastien, What part are you using? Virtex4? Have you seen answer 21127? HTH, Syms. "seb_tech_fr" <sebastien.coquet@techway-dot-fr.no-spam.invalid> wrote in message news:G-SdnWildOwnJ-HeRVn_vA@giganews.com... > Hi, > Does somebody know DCM corner issues? My DCM is not running at very > high clock rate (only 107MHz), so I don't think this issue is > connected with XAPP685 application notesArticle: 91949
I checked the reports, and no other info except the one I posted is given. What bothers me also is that synthesis works on altera tools, like Quartus II. Could it be an error that Quartus does not find in the design, or is it a bug in Xilinx tools?
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z