Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, That would be more of a Q to your synthesis tool (which I'm not overly familiar with). However Modelsim has a nice "virtual bus" command/feature to do exactly what you wanted - check their doc. HTH Ajeetha www.noveldv.comArticle: 92051
Fred wrote: > "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message > news:dlskc7$610$1@news.datemas.de... > > On a sunny day (Mon, 21 Nov 2005 12:48:13 -0000) it happened "Fred" > > <fred@nowhere.com> wrote in <4381c20e$0$23287$db0fefd9@news.zen.co.uk>: > > > >>I find it frustrating that there is no way or telling if a compilation has > >>ended or not. I can't find any feature in ISE which makes a sound when > >>it's > >>finished. I am aware that some might find this an annoying feature but > >>would save me periodically checking to see if it's finished or come to an > >>end early due to a mistake. > >> > >>Any ideas? > > I'd think that hanging a themocouple with level detector on the processor, > > or heat exhaust, was a nice lunch 'time project ;-) > > > > In Linux you could use grep or awk on the output of 'top': > > > > CPU states: 0.5% user, 2.7% system, 15.4% nice, 81.1% idle > > > > look for > X percentage idle, and use keyboard beep: > > echo -e "\a" > > > > .... > > > > A utility to see if a file had been modified would be a possible method. I usually start the build by double-clicking "Generate PROM, ACE, or JTAG File" which will pop up an iMPACT window when finished. Sound would be nicer, though because I'm usually typing something when the window pops up and takes over the focus...Article: 92052
Mike Harrison wrote: > I would also find this very useful - I was wondering if there was > maybe a way to insert an extra program to go 'ping' into the list of > executables that are run as part of the build process. I'd also > really like to see an option to download to device on successful > compilation. You could do the entire flow with "make" from the command line. There you can add a command to issue a beep at the end, or send email, or send a Winpopup message, or whatever you like. The part about downloading to the device wouldn't be a problem either. And the makefile you'll only have to do once, that usually stays the same, since only the list of source files and the project name change. cu, SeanArticle: 92053
On Mon, 21 Nov 2005 04:44:45 -0800, "Georgios Sidiropoulos" <me00569@cc.uoi.gr> wrote: >I would like to monitor the functionality of a state machine I have designed using ISE 7.1. Is there a way to retain the state names (i.e. reset_state,idle_state,run_state)in the modelsim post place and route simulation? I find it more convienient to see the state names than the values of the chosen fsm encoding type. In each FSM I include a special section of code that assigns an ASCII string with the name of the current state to a reg variable. I then display the reg variable in the Modelsim waveform viewer in ASCII format. This section of code is inside an 'ifdef statement that is visible to the simulation tool but not the synthesizer. In Verilog it'd look like this: `ifdef synthesis `else //---- ASCII string code goes here `endif Bob Perlman Cambrian Design WorksArticle: 92054
jussij@zeusedit.com wrote: > > I'm still looking for a Verilog editor that will match BEGIN > > and END blocks just as they do parenthesis and braces. :-( > > FWIW the Zeus editor will do this :) > > It's Verilog configuration comes with brace matching for these > pairs of matching keywords: > > begin attribute case function module task > end endattribute endcase endfunction endmodule endtask > > So for example if the cursor is on or at the end of the endattribute > keyword, the Edit, Find Matching Brace menu will find the matching > attribute keyword. > > Note: The Zeus configuration assumes the file extension for a Verilog > file is V and like all most things in Zeus this can easily be > configured. How well does Zeus handle indenting? I have particular ways I like things lined up. -aArticle: 92055
Mike Treseler wrote:
> Hal Murray wrote:
> > I thought that consensus here was to use the global
> > reset hardware to (asynchronously) force your state
> > machines into a known state and then use a local
> > FF that has been synchronized to get out of that state.
>
> I don't think I'm contradicting that idea.
> The asynch reset gives you a starting
> point for simulation. After this, well-designed
> control logic will use an idle state for
> specific synchronous initialization.
You're right, Mike; the async reset is helpful for simulation. Looking
back at my recent designs, I see a pattern. All of my state machines
have a safe reset state. A slow reset (where some of the state flops
reset before others) on a one-hot machine decodes as an illegal state
so the machine automatically bounces to the reset state. Once
everything is reset then the machine synchronously transitions to an
"idle" state where it stays until other logic tells it to do something
interesting.
For things like loadable registers, the power-on reset is helpful, and
the usual template of
myreg : process (clk, reset) is
begin
if (reset = '1') then
register <= INITVAL;
....
tells the synthesis tool to use INITVAL as the power-on default as well
as the async reset value. Ususally the rest of the logic doesn't
depend on these values, and the registers are loaded before they're
used.
-a
Article: 92056NOTE: This is more of a curiosity than an actual problem. This weekend I discovered some strange behavior after reconfiguration of a xc2vp30. Upon power-up of the board (an ml310), I can use Impact to program the device with no problems. However, if I then reconfigure the device with certain other bitstreams w/o powering down first, impact claims it programs successfully but the device does not start running. I can attempt to connect to my non-running EDK design on the device using XMD -- if the design was MicroBlaze-based XMD connects but displays all zeros for memory and registers locations; if the design was PPC-based XMD returns the error: "ERROR: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000". Again, these bitstreams that fail to run work perfectly if I first power down the device. In searching for a solution, I came across this Answer Record (http://tinyurl.com/737xk) for the PPC error that suggested selecting "Pulse Program" in impact. This fixes the problem and results in consecutive reconfigurations working perfectly. I had thought, however, that the program pin got pulsed before every reconfiguration. What then does selecting "Pulse program pin" do, and why does it fix my problem? (For that matter, does anyone know why I had a problem to begin with?) Thanks! StephenArticle: 92057
Found a way to synthesize... Set the fsm_extract flag to false. Seems like FSM extraction does not work for my design!Article: 92058
I am using XPS to synthesize a Microblaze system with custom hardware functions connected with the FSL bus. The synthesis of the design is done by XST, which is launched from the XPS. I was wondering if there was a way to give options to XST for the synthesis, and if yes, where to specify them. Thank you!Article: 92059
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:3u9tgiFv35pmU1@individual.net... > The asynch reset gives you a starting > point for simulation. After this, well-designed > control logic will use an idle state for > specific synchronous initialization. > Mike, All, Yep. I use the same template as you. Every process has the same async reset and is used *only* in functional simulation. Startup in real life is taken care of by the FF initialisation on configuration. Any extra resets needed after startup are synchronous. The exceptions are when I want to infer SRLUTs, distributed RAM etc. In this case the template misses out the async reset, as it is not supported by the hardware. Cheers, Syms.Article: 92060
You should model your intentions in C or other language with both a floating point and integer version. If you use doubles and compare the final result with your proposed integer model, you will see dramatically different response, errors tend to accumulate unevenly. Even on a fairly small FFT used by a DCT in wavelet project, we got cought on this one even with a Phd on board. The logic design had been almost done without error analysis, when the anomalous integer results showed error peaks of several bits in magnitudes, the shifting had to be corrected to meet spec. Luckily in ASIC this can be reduced to an additional 2 gates of rounding penalty logic in the overall design. In FPGA this would not be the case, not sure if any include rounded division of 2^n. In order to preserve best S/N ratio you need to divide each stage by proper division of sqr 2 or 2 typically every other rank. In 2's complement math, shift down by n bits is not the same as / 2^n although with larger n, it gets closer. Div 2 requires that -ve nos scale towards 0 the same as +ve nos do. This means sign sensitive rounding that considers the bits falling out with the msb. Once this is done the integer results can be a very good approximation of full FP design. >From this I think you can conclude that FFTs generally need 1/2b extra precision for each doubling in size to keep the same S/N ratio. Most all the good DSP texts cover error analysis as a routine part of FFT design, I still use the old blue book from 70s Rabiner I think. johnjaksonArticle: 92061
fpga editor is an interesting tool to explore the internal resources of each family.Article: 92062
Georgios Sidiropoulos wrote:
> I would like to monitor the functionality of a state machine I have designed using ISE 7.1. Is there a way to retain the state names (i.e. reset_state,idle_state,run_state)in the modelsim post place and route simulation? I find it more convienient to see the state names than the values of the chosen fsm encoding type.
Modelsim will display variables of enumerated type by name.
For example:
main : process (clock, reset) is
type RxState_t is (
IDLE,
START,
RECEIVE,
STOP,
FULL,
ERR
);
variable RxState_v : RxState_t;
begin
-- . . .
Then tell modelsim to:
add wave /test_uart/dut/main/*
-- Mike Treseler
Article: 92063brassaro@iro.umontreal.ca wrote: > I am using XPS to synthesize a Microblaze system with custom hardware > functions connected with the FSL bus. The synthesis of the design is > done by XST, which is launched from the XPS. > I was wondering if there was a way to give options to XST for the > synthesis, and if yes, where to specify them. > Thank you! > Read Answer Record 20612. --- Joe Samson (jsamson) pixel-velocity dot comArticle: 92064
Hello, I have a question about reading data from an xc18v04 configuration memory. I am trying clock out 4096 bits plus a 32 bit CRC as I understand the bsdl file to say I should. The extra 32 bits for the CRC end up being the first 32 bits of the next 512 bytes. I viewed the output from the impact programmer from xilinx when doing a readback and it appears to read back 8192 bits with no crc at the end. Can someone help me understand how to read back the data via jtag for the configuration memory? Thanks, JimArticle: 92065
Thanks!Article: 92066
Just to let the group know about the status of the issue, a copy of a mail by Subroto: > The code changes to fix this problem will be available in 5.1 > SP1 to be released end of January, 2006. In the mean time you can try > the following: > > Set the Register Packing variable to Normal or Auto. This is a Fitter > setting. > > The value Minimize Area Register Packing triggers this problem. If you > cannot wait let me know and I will see if we can generate a code dix. Thank you Subroto for the quick response that solved the issue for me, Martin "Subroto Datta" <sdatta@altera.com> schrieb im Newsbeitrag news:kQHef.283$IC3.140@newssvr33.news.prodigy.com... > Hi Martin, > > If you have opened a mysupport case, send me the SR number. We will need your design to figure this out. Can you send me the > design qar also? > > > Subroto Datta > Altera Corp. > > "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> wrote in message news:437b406c$0$12642$3b214f66@tunews.univie.ac.at... >> Any ideas what causes (or better how to avoid) the following crash: >> >> Internal Error: Sub-system: FYGR, File: fygr_list_of_labs.cpp, Line: 2934 >> (atom_id1 >= 0) && (atom_id1 <= m_max_atom_id) && (atom_id2 >= 0) && (atom_id2 <= m_max_atom_id) >> (Fitter pre-processing) >> Quartus II Version 5.1 Build 176 10/26/2005 SJ Web Edition >> >> Regards, >> Martin >> > >Article: 92067
Heiner Litz wrote me personally: >Hello John, >Very interesting thanks! But i still do not get the point. I am using the following verilog statements:> >Always @(posedge clk or negedge res_n) > If(!res_n) > DO RESETS > Else > NORMAL OPERATION > >What bad things can happen using this style >if res_n is zero for more than one clock cycle? >The ansync reset may violate setup/hold of >registers but then after a while where res_n >stays low everything should be fine. >I have really strange problems as my >sdf anotated placed and routed design >works fine but the FPGA does not. >I will try it out but do not really know >what the problem is. > >Regards, Heiner Hello Heiner, I don't use Verilog on a regular basis (yet), and have not built up a repertoire of the natural forms of expression to produce solid results in that language. Since you wrote my personal address, I'm reposting this to c.a.f. for comment by others. My original point is that the place/route tools do not analyse clock setup and hold paths through an async reset. Here's what can happen in the case of a state machine that gets synthesized and expressed in one-hot format (I'm sure this has been described before): Assume the state machine starts changing states immediately after reset is removed. In one-hot form, there will be a FF, call it FF_rst, corresponding to the reset state, which is set to 1 by the reset. The first state FF after reset, call it FF_st1, will be set to 0 by reset. If working correctly, at the first clock edge after reset is removed, FF_rst -> 0, and FF_st1 -> 1. Now it is 99.99% (really, 100%) guaranteed that the delay of reset to FF_rst will be different than the delay to FF_st1. Assuming the reset delay is shorter to FF_rst, there is a timing window where the clock can transition such that FF_rst -> 0 because reset is not active there, but FF_st1 stays at 0 because reset is still asserted there. Voila, you've entered no-hotville. At the next clock edge, when reset has finally de-asserted at FF_st1, still nothing happens, because FF_st1 needs to see FF_rst = 1 in order to set. There's no road out from no-hotville. If that timing window is larger than your clock period, the SM will never start up. If that timing window is really small, you can get a design that works 99.9 % of the time and fails (by Murphy's law) when you really need it. People often don't travel this road, because state machines sit in reset waiting for some other synchronized signal to leave reset, as described by Andy, and this is perfectly legitimate. So no _single_ template fits every situation. As Syms says, SRLs and RAM based registers can't have any reset in code that infers them. It is important to distinguish between a global async reset and distributed sync resets. Ah-hah!, looks like there is a back door out of no-hotville. XST has a couple of new constraints on FSM expression: 'safe_implementation' and 'safe_recovery_state'. I haven't played with these yet, so don't know how much netlist inflation they produce, but if you (Heiner) want a quick and dirty way to imunize state machines from async startup woes, without having to modify any existing code, you might try these. I'm not advocating relying on these as a fix for final release, but they might be a tool to help show that a SM might be getting off track, and that you need to look deeper into your code. I would suggest them for final release if you have SEU concerns (provisionally, I haven't looked at their output yet). Has anyone any experience with these constraints they'd like to share? Do any other synthesis tools support them? Regards all, John p.s. I rely on Google for my c.a.f. browsing/posting. I'm glad they've sped up their posting, I was finally able to participate in real-time with a discussion here (formerly, they had a half day wait from posting to appearance). Google makes me put my real address in, but please try to refrain from writing me directly on thread topics, I feel guilty if I don't have time or inclination to respond.Article: 92068
> How well does Zeus handle indenting? I have particular ways
> I like things lined up.
Zeus has at least four indenting modes.
1) Smart Indenting
This indenting is tied to the enter key and it simply lines up
the new cursor position with the line aboves. But this indenting
also maintains the white space from the line above, which is
important to white space sensitive languages like Python.
2) Smart Brace Indenting
This indenting detects the start brace character/string, add
the matching end brace character/string and then indents the
cursor.
So excusing my very limited knowledge of Verilog but here is
a simple example of how this works:
function Something
begin|<- Cursor here when enter key pressed
becomes:
function Something
begin
|<-Cursor now here
end
3) Templates
Zeus also lets you define code templates that get expanded on
the space key. For example the following 'foi' template is defined
for the c++ document type and if you type in this:
foi|<-space key here
it will expand to:
for (int i = 0; i < |; ++i)
{ ^
} Cursor here
4) Macros
Finally Zeus is fully scriptable so it is also possible to write
a macros script to do some specialised form of indenting.
Jussi Jumppanen
Author: Zeus for Windows IDE
http://www.zeusedit.com
Article: 92069Hal Murray wrote: > >My code template assumes one global reset pulse > >that occurs once, on a low-skew path, > >after the fpga image has loaded. > >I also assume that this pulse has a source > >external to, but using the same clock as the fpga. > >In my case, it comes from a cpu that loads > >the binary fpga image. > > Is that good enough? > > Don't you also need the prop time on that low-skew path > to be short enough relative to your clock cycle time so > that you know when it gets to your FFs? > > Last I checked, the global reset on most Xilinx parts > was too slow to be useful in that context. > > I thought that consensus here was to use the global > reset hardware to (asynchronously) force your state > machines into a known state and then use a local > FF that has been synchronized to get out of that state. > > -- How about using a bufgce instead of a bufg and gate off the clock during and sometime after async reset? -LasseArticle: 92070
Lasse wrote: >How about using a bufgce instead of a bufg and gate off the clock >during and sometime after async reset? Can be done with care, but there's a chorus of "don't gate clocks in an FPGA" as a general design practice. See e.g. http://tinyurl.com/73st2 for an answer record containing the caveat: "CE must not change during a short setup window just prior to the rising clock edge on the BUFGCE input I. Violating this setup time requirement can result in an undefined runt pulse output." The list of "ways to do it wrong" is far larger than "ways to do it do it right", and even the do it right list can have some ways to do it wrong as a subset.Article: 92071
I "normally" use Altera devices. I have a personal preference for them over Xilinx in addition to a poor technical experience with their XC9500 series PLDS. I would assume that you are either using a set purchased development tools or their webpack ISE. EIther one should have a synthesis step as part of the compile or build process. As I indicated, the synthese process converts the VHDL code into a format applicable to the logic family. The synethesizer must be aware of the resources available in the device, e.g. how many global clock buffers are available, or are global resets available, etc. If you are interested in the nuts and bolts of synthesis, a good place to start may be in compiler algorithms as this is basically what the synethizer is. Hope my explanation helps.Article: 92072
Bob,
I also follow that in old Verilog. Thanks to SV, we have enums.
However the OP asked about Post place-and-route sim, hence this trick
won't help much. One needs to build equivalent signal names and enum
mapping. I believe MTI's virtual bus fits the bill better.
Regards
Ajeetha
www.noveldv.com
Article: 92073On 21 Nov 2005 18:33:09 -0800, ajeetha@gmail.com wrote: >Bob, > I also follow that in old Verilog. Thanks to SV, we have enums. >However the OP asked about Post place-and-route sim, hence this trick >won't help much. One needs to build equivalent signal names and enum >mapping. I believe MTI's virtual bus fits the bill better. > >Regards >Ajeetha >www.noveldv.com My mistake--I missed the part about post-place-and-route. Bob Perlman Cambrian Design WorksArticle: 92074
Given that editors are like tooth paste, everyone has a favorite and hates all other brands, I've hesitated to chime into this thread, but... I've been using Vim for a number of years to do Verilog editing and am very happy with it. It has syntax hi-lighting, auto-indent, and tags. It also runs on every platform I've ever cared about. If you load the right plug-in, it understands begin...end. It's an excellent program and keeps getting better. John Providenza
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z