Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
langwadt@ieee.org wrote: > Marco skrev: > > >>"Symon" <symon_brewer@hotmail.com> wrote in message >>news:4363c605$0$41142$14726298@news.sunsite.dk... >> >>>Marco, >>>This any good? >>>http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870 >>>Ciao, Syms. >>>"Marco" <marcotoschi@nospam.it> wrote in message >>>news:djtebp$m2k$1@nnrp.ngi.it... >>> >>>>Hallo, >>>>is there anybody who can help me to find out the scheme of a 16-bit >>>>delta-sigma adc? >>>> >>>>I have already made some searches into google but I don't have found >>>>interesting informations. >>>> >>> >>> >> >>Now I'm trying to implement the sigma delta a/d. >>The range of my analog input will be from 0 to 3.3V >> >>Here the scheme of delta sigma modulator: >> >> _______ ________ __________ >>Analog In --|diff.amp.|---|Integrator|---|Comparator|----> dig.filter >> --| | | | |with gnd | >>| >> | >>| >> | ________ | >> ---------| 1-bit dac|------------------------- >> | | >> >>It's not clear the function of 1-bit DAC. If it's only 1 bit it should be as >>a switch, so, >>in my case, a comparator connected to ground. >>And also diff.amp should be a comparator? >> >>I think I'm making a mistake. >> >>Could you explain where is wrong? >> >>Many Thanks >>Marco > > > your scheme is hard to read, you probably used tabs instead of spaces. > the DAC should output 0v and 3.3V, your comparator should have a 3.3/2= > > 1.65V reference > > -Lasse > To answer another of Marco's questions, the diff. amp should not be a comparator. It must have a linear output and will usually be based on an op. amp. Regards, JohnArticle: 91126
"John Monro" <johnmonro@optusnet.com.au> wrote in message news:4364b60d$0$30257$afc38c87@news.optusnet.com.au... > langwadt@ieee.org wrote: >> Marco skrev: >> >> >>>"Symon" <symon_brewer@hotmail.com> wrote in message >>>news:4363c605$0$41142$14726298@news.sunsite.dk... >>> >>>>Marco, >>>>This any good? >>>>http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870 >>>>Ciao, Syms. >>>>"Marco" <marcotoschi@nospam.it> wrote in message >>>>news:djtebp$m2k$1@nnrp.ngi.it... >>>> >>>>>Hallo, >>>>>is there anybody who can help me to find out the scheme of a 16-bit >>>>>delta-sigma adc? >>>>> >>>>>I have already made some searches into google but I don't have found >>>>>interesting informations. >>>>> >>>> >>>> >>> >>>Now I'm trying to implement the sigma delta a/d. >>>The range of my analog input will be from 0 to 3.3V >>> >>>Here the scheme of delta sigma modulator: >>> >>> _______ ________ __________ >>>Analog In --|diff.amp.|---|Integrator|---|Comparator|----> dig.filter >>> --| | | | |with gnd >>> | >>>| >>> | >>>| >>> | ________ >>> | >>> ---------| 1-bit dac|------------------------- >>> | | >>> >>>It's not clear the function of 1-bit DAC. If it's only 1 bit it should be >>>as >>>a switch, so, >>>in my case, a comparator connected to ground. >>>And also diff.amp should be a comparator? >>> >>>I think I'm making a mistake. >>> >>>Could you explain where is wrong? >>> >>>Many Thanks >>>Marco >> >> >> your scheme is hard to read, you probably used tabs instead of spaces. >> the DAC should output 0v and 3.3V, your comparator should have a 3.3/2= >> >> 1.65V reference -Lasse >> > > To answer another of Marco's questions, the diff. amp should not be a > comparator. It must have a linear output and will usually be based on an > op. amp. > > > Regards, > John > Is it possible to use 2 LVDS pins? MarcoArticle: 91127
An.In --|diff.amp.|--|Integrator|--|Comparator|-+- dig.filt
+-| | | | |with gnd | |
| |
| ________ |
------------| 1-bit dac|-------------------
| |
Sorry, I hope this would be more clear
Article: 91128You could see a clear picture at the following link: http://www.maxim-ic.com/images/appnotes/1870/A237Fig04.gif The integrator can be made with a 1-bit accumulator? And differential amplifier can be made using a IBUFDS? Many Thanks MarcoArticle: 91129
First, I am not a lawyer, and I don't know what I am talking about. On 29 Oct 2005 18:02:03 -0700, "Weng Tianxiang" <wtx@umem.com> wrote: >Hi, Why are there two patents with same title? Patents can have any title they like. Sometimes they are descriptive of the patent contents, and sometimes they are deliberately poor to make searches fail. Usually they are descriptive. There are many reasons for apparently duplicated effort. You need to study the claims section carefully to see how they differ. I believe that patents can be described as "method patents" and "means patents". Sometimes the claims are combined in one patent and sometimes they are separate patents. After filing a patent, the engineering continues. If additional ideas are developed, or better implementations discovered, then a follow on patent may be filed to cover the new material. >What are their major purposes? To protect intellectual property. A means patent covers the mechanisms or structures needed to implement the patent. A methods patend covers how the means are applied to achieve the goal of the patent. (I may be totally screwed up on this). >For example: Altera patents: >6,859,065 Use of dangling partial lines for interfacing in a PLD >6,653,862 Use of dangling partial lines for interfacing in a PLD > >In the latest patent, it contains the following statements: > >This application is a continuation of U.S. patent application Ser. No. >10/140,911 filed on May 6, 2002, now U.S. Pat. No. 6,653,862, which >claims priority to U.S. Provisional Application Ser. No. 60/289,346, >filed May 6, 2001, and entitled "Use of Dangling Partial lines for >Interfacing in a PLD." This may be an example of the "additional ideas". I have not looked at the patents you reference. >Thank you. >Weng PhilipArticle: 91130
One common situation where patents have duplicate titles is simply that the patents cover (in a very general sense) similar subject matter. For example if you and I were independently working on ergonomic keyboard, there would be nothing unusual that we both file patent applications with the title "Ergonomic Keyboard." A second reason is that a patent application may spawn several patents. For example, if I apply for a patent on my ergonomic keyboard and half the claims are allowed, I may choose to go ahead and pay the fees and have the patent granted; meanwhile I could file a continuation application and pursue the remaining claims. It is likely that both patents would have the same title. Regarding the cases you cited, it is possible that the lawyer erred, more likely however the client and the lawyer decided to take what the patent office offered, and have a first patent issue. The client and lawyer would have also agreed to file an additional application. Yes, multiple patents generally cost more than a single patent, but it still may be good business strategy to go for multiple patents. In some cases the patent office requires that only one set of claims be examined, if you want the other claims you have to file another application; which is likely to have the same title. If you want to know more about what happened with those particular patents go to http://portal.uspto.gov/external/portal/pair , and look up the prosecution history. This answer to your question about when to file a provisional / regular application and if a c-i-p make sense depends on the details of the situation. One strategy is to file a provisional application with information X as soon as you can write a good description. When information Y becomes available, then file a provisional with a description of X+Y. When you have information Z, then file a provisional application with X+Y+Z. You just have to keep in mind that provisional applications lapse after one year. So if you wait to file a regular application for X until more than 1 year after filing provisional X, then you have to rely on the priority date of the X+Y provisional application(assuming that less than one year has passed since filing provisional X+Y). All of the above is a general discussion of U.S. patent law, and not intended as legal advice for any particular situation. RichardArticle: 91131
Antti Lukats wrote: > Hi > > as the ISE 8.1 is expected this months and EDK 8.1 in December I wonder if > some pre release info is already available, eg what is improved, etc.. > > specially EDK, if there are new cores added > > OPBor PLB DDR2 core as example, is it 8.1? Just a thought - Shouldn't Xilinx have Antti on their Beta testing program ? -jgArticle: 91132
fifo_data <= X"AA4F"; This representation gives an error " expecting an expression of type std_logic_vector" Remember ,my fifo_data is a std_logic_vector. regards, Anupam JainArticle: 91133
It is Monday :-) Simon "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1130631842.026203.205060@g14g2000cwa.googlegroups.com... > Let's straighten this out on Monday! > Peter Alfke, Xilinx Applications >Article: 91134
On 28 Oct 2005 17:43:10 -0700, alan@nishioka.com wrote: >Is there a way to: >1. Prefill the Microblaze instruction cache with program >2. Startup with caches enabled and locked > >Then I could put boot code in the icache which would load external ram. >I would then have a bigger cache since right now my block ram is split >between lmb ram and cache. > >Am I the only person who would find this useful? > >Alan Nishioka >alan@nishioka.com No, I think I will find it useful, as I will be designing with it in two weeks time. But I thought it was possible (well not really, think, it was an undocumented positive feeling ;-) If it is impossible, the it seems a not really nice problem to me (too).Article: 91135
hi In my implementation, top entity has some pins with array type in VHDL. It is strange that ISE does not map / place and route. Does someone have same experience?Article: 91136
Hi, Kunal said it right before. The first two cases are identical. The third has no outputs, therefore optimizes away the register. Mow, if you want 48 Outputs and (just a guess) 22 other I/Os +1 Clock have a look at the used IOBs: In the first two cases there are 70 IOBs used. (Too much for that small chip anyway) In the third case 48 outputs,are gone leaving 22 used I/Os. This fits into your chip, but all the output registers and their associated logic are gone. so first of all you need a chip with more pins so the design fits. The number of LUTs is quite irrelevant in this case, because you are using only 5% of the chipsize for logic. And for the observed "reduction" in LUTS: 81 remuved LUTS divided by 48 controlled FFs gives less than two LUTs per FF. This is a quite good ratio. My recommendation: Read the FPGAs datasheet and understand the SLICE and IOB structure and how the ressources are used by your synthesizer. Understand how to read a synthesis report. have a nice synthesis Eilert himassk schrieb: > output [47:0]Command; > > reg [47:0]Command; > Selected Device : 3s50vq100-5 > > Number of Slices: 51 out of 768 6% > Number of Slice Flip Flops: 4 out of 1536 0% > Number of 4 input LUTs: 89 out of 1536 5% > Number of bonded IOBs: 70 out of 63 111% > Number of GCLKs: 1 out of 8 12% > > _________________________________________________________________ > reg [47:0]Command; > > > Selected Device : 3s50vq100-5 > > Number of Slices: 4 out of 768 0% > Number of Slice Flip Flops: 4 out of 1536 0% > Number of 4 input LUTs: 8 out of 1536 0% > Number of bonded IOBs: 22 out of 63 34% > Number of GCLKs: 1 out of 8 12% >Article: 91137
Marco schrieb: > Hallo, > is there anybody who can help me to find out the scheme of a 16-bit > delta-sigma adc? Look for US Patents 6,351,145 and 6,246,258 at http://patft.uspto.gov/ They are about implementing ADCs by using differential FPGA inputs as analog comparators. Kolja SulimmaArticle: 91138
Jack schrieb: > hi > > In my implementation, top entity has some pins with array type in VHDL. > > It is strange that ISE does not map / place and route. > > Does someone have same experience? > Of course, many people have the same experience. It happens quite frequently that ISE does not map, place and route. And even more frequently that it does not synthesize. This happens both with and without arrays. Most of the time it is a bug in your HDL, sometimes it is a bug in ISE. One possible solution for the former case is to fix the bug. Kolja SulimmaArticle: 91139
anupam schrieb: > fifo_data <= X"AA4F"; > > This representation gives an error " expecting an expression of type > std_logic_vector" > Remember ,my fifo_data is a std_logic_vector. > > regards, > Anupam Jain > AFAIK this works only if the bus width is a integer multiple of four. Regards FalkArticle: 91140
Hi, Does anyone have any SystemACE parts for sale (upto 15 pieces) or know any distributor who has some in stock? Cheers, JonArticle: 91141
"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag news:1130753284.143142.3010@g44g2000cwa.googlegroups.com... > Hi, > > Does anyone have any SystemACE parts for sale (upto 15 pieces) or know > any distributor who has some in stock? > > Cheers, > Jon > I have never found any disti selling them in small quantity. its on my DONOTUSE list anyway. And will be obsoleted soon. (Antti's guess) anttiArticle: 91142
Marco wrote: > "John Monro" <johnmonro@optusnet.com.au> wrote in message > news:4364b60d$0$30257$afc38c87@news.optusnet.com.au... > >>langwadt@ieee.org wrote: >> >>>Marco skrev: >>> >>> >>> >>>>"Symon" <symon_brewer@hotmail.com> wrote in message >>>>news:4363c605$0$41142$14726298@news.sunsite.dk... >>>> >>>> >>>>>Marco, >>>>>This any good? >>>>>http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870 >>>>>Ciao, Syms. >>>>>"Marco" <marcotoschi@nospam.it> wrote in message >>>>>news:djtebp$m2k$1@nnrp.ngi.it... >>>>> >>>>> >>>>>>Hallo, >>>>>>is there anybody who can help me to find out the scheme of a 16-bit >>>>>>delta-sigma adc? >>>>>> >>>>>>I have already made some searches into google but I don't have found >>>>>>interesting informations. >>>>>> >>>>> >>>>> >>>>Now I'm trying to implement the sigma delta a/d. >>>>The range of my analog input will be from 0 to 3.3V >>>> >>>>Here the scheme of delta sigma modulator: >>>> >>>> _______ ________ __________ >>>>Analog In --|diff.amp.|---|Integrator|---|Comparator|----> dig.filter >>>> --| | | | |with gnd >>>>| >>>>| >>>> | >>>>| >>>> | ________ >>>>| >>>> ---------| 1-bit dac|------------------------- >>>> | | >>>> >>>>It's not clear the function of 1-bit DAC. If it's only 1 bit it should be >>>>as >>>>a switch, so, >>>>in my case, a comparator connected to ground. >>>>And also diff.amp should be a comparator? >>>> >>>>I think I'm making a mistake. >>>> >>>>Could you explain where is wrong? >>>> >>>>Many Thanks >>>>Marco >>> >>> >>>your scheme is hard to read, you probably used tabs instead of spaces. >>>the DAC should output 0v and 3.3V, your comparator should have a 3.3/2= >>> >>>1.65V reference -Lasse >>> >> >>To answer another of Marco's questions, the diff. amp should not be a >>comparator. It must have a linear output and will usually be based on an >>op. amp. >> >> >>Regards, >>John >> > > > Is it possible to use 2 LVDS pins? > > Marco > > Marco, I am afraid not. While the input circuit is differential, the rest of a LVDS buffer is optimised for digital performance, and not for the characteristics we require in a good operational amplifier. A LVDS buffer would make a worse integrator than the cheapest op. amp. so why bother? Regards, JohnArticle: 91143
Hi All, I am trying to P&R an XC2V8000 with a large number of MCP constraints on a 2GB (+2GB swap, /3GB switch in boot.ini) Win2K machine and I am running out of memory. If I take the constraints out then ISE only consumes 1GB. # ERROR:Portability:3 - This Xilinx application has run out of memory or has # encountered a memory conflict. Current memory usage is 1969212 kb. Memory # problems may require a simple increase in available system memory, or # possibly a fix to the software or a special workaround. To troubleshoot or # remedy the problem, first: Try increasing your system's RAM. Before I buy some extra memory, are there any switches or tips to reduce the memory requirements? I tried removing some of the MCP's to see if I could still meet timing but unfortunately I need them all. I also tried installing ISE on my Gentoo64 machine but after some hacking of libraries, portmap etc I got a "6031 Segmentation fault" during installation :-( Thanks, Hans. www.ht-lab.comArticle: 91144
Hey, i made a design for a LVDS input (with some tweaks) and the design is = working but i found this info warning in the syr and i was wondering why = i get this warning ... since all of the clks are generated by a DCM and = each clk has its own bufg ... what happens is, the lvds clk is coming in on a BUFGDS input buffer and = goes to a DCM module, this DCM module has the DCM + all of the recovery = logic + all the other buffers for the feedback and output clks... so = every clk goes through a buffer but why do i get the following warning: Clock Information: ------------------ ------------------------------------------------------+------------------= -----------------------------------------------------------------+-------= + Clock Signal | Clock buffer(FF name) | Load | ------------------------------------------------------+------------------= -----------------------------------------------------------------+-------= + c_input_LVDS/lvds_dcm/DCM_PS_inst:CLK0 | BUFG | 0 | c_input_LVDS/lvds_dcm/DCM_PS_inst:CLKFX | BUFG | 0 | c_input_LVDS/lvds_dcm/DCM_PS_inst:CLKFX180 | BUFG | 0 | rxclk_out_OBUF(c_input_LVDS/lvds_dcm/rxclk1_bufg:O) | NONE(*) | 0 | c_input_LVDS/rxclkin0(c_input_LVDS/rxclkin0_ibufgds:O)| = c_input_LVDS/lvds_dcm/DCM_PS_inst:CLK0(*)(c_input_scan/PARAMATERS/BU19) = | 697 | c_input_LVDS/rxclkin0(c_input_LVDS/rxclkin0_ibufgds:O)| = c_input_LVDS/lvds_dcm/DCM_PS_inst:CLKFX(*)(c_input_LVDS/lvds_rx0/rx1/fdce= _dpb1) | 192 | c_input_LVDS/rxclkin0(c_input_LVDS/rxclkin0_ibufgds:O)| = c_input_LVDS/lvds_dcm/DCM_PS_inst:CLKFX180(*)(c_input_LVDS/lvds_rx0/rx1/f= dce_dna0)| 176 | xtal_clk | BUFGP | 25 | sysclk | BUFGP | 31 | ------------------------------------------------------+------------------= -----------------------------------------------------------------+-------= + (*) These 4 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) = generated by combinatorial logic. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically = buffered by XST with BUFG/BUFR resources. Please use the buffer_type = constraint in order to insert these buffers to the clock signals to help = prevent skew problems. Thank you for you help in advance, kind regardsArticle: 91145
> Marco, > I am afraid not. While the input circuit is differential, the rest of a > LVDS buffer is optimised for digital performance, and not for the > characteristics we require in a good operational amplifier. > A LVDS buffer would make a worse integrator than the cheapest op. amp. so > why bother? > > Regards, > John Hi John, sorry for my terrible scheme. Please watch the picture at the link: http://www.maxim-ic.com/images/appnotes/1870/A237Fig04.gif That should be more clear. I thought that I could replace the 1-bit dac using a LVCMOS25 out pin (without dac because it is only 1 bit) and connecting it to the negative input of LVDS25. What do you think about it? Is it possible? Many Thanks MarcoArticle: 91146
Antti Lukats wrote: > "Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag > news:1130753284.143142.3010@g44g2000cwa.googlegroups.com... > >>Hi, >> >>Does anyone have any SystemACE parts for sale (upto 15 pieces) or know >>any distributor who has some in stock? >> >>Cheers, >>Jon >> > > > I have never found any disti selling them in small quantity. > > its on my DONOTUSE list anyway. > And will be obsoleted soon. (Antti's guess) > > antti > > Obsoleted! I sure hope not. I like the ability to use 'standard' memory cards to configure my FPGA. I also love the ability to store files in a FAT formatted card. It would be nice if they made a version in a smaller package. Or used SD memory cards instead!Article: 91147
"Eli Hughes" <emh203@psu.edu> schrieb im Newsbeitrag news:dk58j3$lge$1@f04n12.cac.psu.edu... > Antti Lukats wrote: > > "Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag > > news:1130753284.143142.3010@g44g2000cwa.googlegroups.com... > > > >>Hi, > >> > >>Does anyone have any SystemACE parts for sale (upto 15 pieces) or know > >>any distributor who has some in stock? > >> > >>Cheers, > >>Jon > >> > > > > > > I have never found any disti selling them in small quantity. > > > > its on my DONOTUSE list anyway. > > And will be obsoleted soon. (Antti's guess) > > > > antti > > > > > > Obsoleted! I sure hope not. I like the ability to use 'standard' memory > cards to configure my FPGA. I also love the ability to store files in a > FAT formatted card. > > It would be nice if they made a version in a smaller package. Or used > SD memory cards instead! > stay tuned. I will introduce one soon. have been working on it. all the nice features. smaller footprint and can be updated. AnttiArticle: 91148
Hallo, How may I realize an integrator into a FPGA? Many Thanks MarcoArticle: 91149
Anupam,
X"AA4F" should work, which simulator do you use? I believe this
is a VHDL-93 feature and it is amazing that even in 2005 end (almost 13
years!!) some tools require a Mode-93 kind of switch to their
compilers.
Your compiler may need a -V93 or some thing similar.
HTH
Ajeetha
www.noveldv.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z