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> Learn how to write makefiles, and use gnu make. Then don't worry > about Xilinx GUIs again, excluding the tools that should be graphical: > FPGAeditor and FloorPlanner. Got any info/links/tutorials on the best way to learn to use makefiles and GNU make to build FPGAs? AndrewArticle: 91801
Anthony Ellis wrote: > As a licensed user of the Xilinx PCI32 core, where does one get a > more comprehensive PCI testbench (stimulus generator) than what comes > with the Xilinx PING example. We modified the Opencores PCI testbench to provide an engine that would allow us to generate arbitrary PCI cycles. Regards, MarkArticle: 91802
"Andrew" wrote: >> Learn how to write makefiles, and use gnu make. Then don't worry >> about Xilinx GUIs again, excluding the tools that should be graphical: >> FPGAeditor and FloorPlanner. > >Got any info/links/tutorials on the best way to learn to use makefiles >and GNU make to build FPGAs? If you have some type of UNIX, you probably already have make installed. If you have windows easiest thing to do is to install Cygwin: http://www.cygwin.com/ Documentation on gnu make is at: http://www.gnu.org/software/make/manual/html_mono/make.html For how to use XST and the rest of the tools on command line, see the Xilinx documentation. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 91803
> At $39.95, it costs the same as Zeus. Just curious. For the same price, does UltraEdit also come with integrate version control, class browsing, intellisensing and macro scripting? The last time I checked, for these extra programming features you needed to move up to the UltraEdit Studio which comes in at twice the price. > And when you report a bug, they fix it, quickly. Zeus is no different in this regard. Jussi Jumppanen Author: Zeus for Windows Programmer's IDE http://www.zeusedit.comArticle: 91804
On 13 Nov 2005 18:30:33 -0800, jussij@zeusedit.com wrote: >> At $39.95, it costs the same as Zeus. > >Just curious. For the same price, does UltraEdit also come with >integrate version control, class browsing, intellisensing and >macro scripting? > >The last time I checked, for these extra programming features you >needed to move up to the UltraEdit Studio which comes in at twice >the price. Plain old UltraEdit has macro scripting. For version control, I use the Tortoise extension for subversion. As for the other features you mentioned, I don't know; I don't use them. And I also configure UltraEdit to run emacs Verilog mode in batch to get quick generation of port lists, etc. >> And when you report a bug, they fix it, quickly. > >Zeus is no different in this regard. Nor would I suggest otherwise. I posted not to disparage anyone else's editor, but to say that UltraEdit is nothing short of terrific. I don't use many software packages that elict grudging acceptance, much less praise, so when I find a good one, I like to spread the word. Bob Perlman Cambrian Design WorksArticle: 91805
"Paul R" <paul_p_roberts@bigpond.com> wrote in message news:eBEdf.16405$Hj2.13728@news-server.bigpond.net.au... >I was wondering what anyone else's experience ahs been with getting hold of > Virtex4 FX 20 and 60 devices (The ones with the up to 10 GBPs MGTs). I > have > had 3 of the XC4VFX60-10FF672CES2 (That is engineering sample stepping 2) > devices on order since May this year, originally with a 6 week lead time. > I > have had constant series of delays for no clear reasons given by our local > agent (I'm in Australia). Xilinx won't talk directly, everything has to go > through this agent MEMEC, the sole authorized distributer for Xilinx in > Oz. > They are either unwilling or don't have the info themselves. I get given > snippets about speed of the MGTs , yield problems, new speed grade > desiginations but no real info. The Xilinx website has nothing but its > totally positive marketing hype. To add insult to injury I was due to get > my > chips late October. At this time MEMEC was bought by AVNET, all the > puchase > orders with xilinx were reraised under the AVNET banner but they stuffed > up > and reraised at the current market leadtime of 16 weeks odd! > > I have a fully designed (12 layer) PCB which is fully populated with a big > blank where the FPGA is to go and its seriously delaying our whole > project. > The project also relies on the 10 GBPs serial data rate capability of the > V4 > RocketIOs. Do any of you people not so far away from the source as I am > know > what the story is with the FX devices? Should I be redesigning my sytem to > use external SERDES and not rely on the V4 FXs coming along. I spoke to > one > of the hard to find parts specialists in the US and they said the > engineering sample V4 devices are free in the US. I'm paying $1300 each > for > them is this true? > > When I looked at going back one step to the Viretex2 pro X 10 GBPs devices > I > find all reference to the -5 10 GBPS devices has totally vanished from the > Xilinx datasheets. What's going on here? > > Paul R > > I know some of the CSIRO guys have had v4 chips for a while. They were using avnet/memec but now are supposedly buying from the US to get decent service and pricing. Apparently with the memec to avnet switch 4 month leads turned into 8 month leads. So you are not alone. Local TI guys told us to talk to avnet but they don't bother returning phone calls. AlexArticle: 91806
Mike Treseler wrote: > I use single process entities > with no signal declarations. > I declare process variables for every > local register and output port. > I use functions to create values > and procedures to collect and name > all repeated command sequences. That can be a dangerous style. Some tools are quite bad with VHDL procedures and functions. I have seen a some formal tools to create just insane netlists out of procedures, some synthesizers can have problems with them. Also some code chekers understand procedures quite badly and can show problems that are not real (they can't figure out the control flow and report extra latches that are not in reality there etc.) Procedures are nice way to make the code clear to read, but unfortunately the tool support is still problematic. I can't understand what is so difficult in that support. --KimArticle: 91807
Thanks all for suggestions. with my version of ISE, I can not put the IOB attribute on a signal: I get the error ERROR:HDLParsers:1202 - "/home/XXX/XXX/XXX.vhd" Line 210. Redeclaration of symbol tristate_enable_reg. --> (the same attribute on the process generates no error but no IOB register.) My workaround is to put the clocked process into a file: register.vhd then I put the attribute on the instantiation of the component.Article: 91808
Hallo to everybody, I bought a "Spartan 3 Starter Kit" and to program the board there's a JTAG cable. I've two questions: Can I use the same cable to do In Circuit Debugging with JTAG System? Do I need some software not bundled with Xilinx ISE to do it? Thanks, Massimo.Article: 91809
"Massimo Gaggero" <max@crs4.it> schrieb im Newsbeitrag news:dl9gqh$dge$1@pietro.crs4.it... > Hallo to everybody, > I bought a "Spartan 3 Starter Kit" and to program the board there's a JTAG > cable. > > I've two questions: Can I use the same cable to do In Circuit Debugging > with JTAG System? > Do I need some software not bundled with Xilinx ISE to do it? > > Thanks, > Massimo. you can use ChipScopePro with the JTAG cable. ChipScopePro is a separate product - free evaluation is available from Xilinx Antti, E-Bokk: "DIY FPGA Logic Analyzer" http://ebook.openchip.orgArticle: 91810
Hi Paul, I got 5 FX 20's a couple of months ago in the UK. We are a small customer. Don't forget to check the errata before using those engineering samples, particularly if you want to use the MGTs and you've already made your PCB! Cheers, JonArticle: 91811
Hi all I have problem in designing a circuit which is recursive Suppose i am designing a schematic of BRLSHIFTER and suppose i want assign all outputs to inputs then what changes should I made in ".vhf" file? Thanking youArticle: 91812
"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag news:1131963536.332953.27970@g44g2000cwa.googlegroups.com... > Hi Paul, > > I got 5 FX 20's a couple of months ago in the UK. We are a small > customer. Don't forget to check the errata before using those > engineering samples, particularly if you want to use the MGTs and > you've already made your PCB! > > Cheers, > Jon > oh FX20 was available for small customers some time already, but only ES with no functional MGTs and the original poster was only interested in FX60 and 10GB use of MGTs AnttiArticle: 91813
Finally a credible answer. ThanksArticle: 91814
Hi, I'am wondering about the download capabilities of XMD. If an FPGA is configured with impact on the JTAG, then software uses XMD with the JTAG cable to be downloaded in FPGA. If for example my SOC has a PPC, some BRAM, an OPB_EMC peripheral and some externalSRAM attacheds to it. Is XMD able to directely download my .elf into the external SRAM through the EMC peripheral and launch software from the external SRAM ??? This is what I understand of the xilinx's webserver reference design to work. I'm not sure of this, I would thing there has to be a bootloader to interface with XMD that will drive the EMC peripheral ??? But they don't speak about it... Can someone clear this point ? Thak you. Stéphane.Article: 91815
sjulhes wrote: > Hi, > > I'am wondering about the download capabilities of XMD. > > If an FPGA is configured with impact on the JTAG, then software uses XMD > with the JTAG cable to be downloaded in FPGA. > > If for example my SOC has a PPC, some BRAM, an OPB_EMC peripheral and some > externalSRAM attacheds to it. > > Is XMD able to directely download my .elf into the external SRAM through = the > EMC peripheral and launch software from the external SRAM ??? Yes > > This is what I understand of the xilinx's webserver reference design to > work. > I'm not sure of this, I would thing there has to be a bootloader to > interface with XMD that will drive the EMC peripheral ??? > But they don't speak about it... The reset vector is at 0xfffffffc, so there has to be some memory to vector the program off to where the rest of the memory is. If you notice, from XMD, there are commands like mrd and mwr (memory read) and (memory write) that are available via the JTAG emulator through XMD. One could write a tcl program that did a series of writes and reads to load the program into memory. There is a the "dow" command available that takes an elf file and loads sram. Others have written tcl programs to program flash, which needs a series of mwr, mrd commands. - Hope this helps Newman >=20 > Can someone clear this point ? > Thak you. >=20 > St=E9phane.Article: 91816
> I was wondering what anyone else's experience ahs been with getting hold of > Virtex4 FX 20 and 60 devices Seems like he was interested in the FX 20's. Cheers, JonArticle: 91817
I'm using a VIRTEX4 FX12 it should be ready by the end of October, but now it seems that the production will start end of Febrary. FrancescoArticle: 91818
Ok, thank you, it's getting clearer ! Stéphane. "Newman" <newman5382@yahoo.com> a écrit dans le message de news: 1131979709.484972.194960@f14g2000cwb.googlegroups.com... sjulhes wrote: > Hi, > > I'am wondering about the download capabilities of XMD. > > If an FPGA is configured with impact on the JTAG, then software uses XMD > with the JTAG cable to be downloaded in FPGA. > > If for example my SOC has a PPC, some BRAM, an OPB_EMC peripheral and some > externalSRAM attacheds to it. > > Is XMD able to directely download my .elf into the external SRAM through the > EMC peripheral and launch software from the external SRAM ??? Yes > > This is what I understand of the xilinx's webserver reference design to > work. > I'm not sure of this, I would thing there has to be a bootloader to > interface with XMD that will drive the EMC peripheral ??? > But they don't speak about it... The reset vector is at 0xfffffffc, so there has to be some memory to vector the program off to where the rest of the memory is. If you notice, from XMD, there are commands like mrd and mwr (memory read) and (memory write) that are available via the JTAG emulator through XMD. One could write a tcl program that did a series of writes and reads to load the program into memory. There is a the "dow" command available that takes an elf file and loads sram. Others have written tcl programs to program flash, which needs a series of mwr, mrd commands. - Hope this helps Newman > > Can someone clear this point ? > Thak you. > > Stéphane.Article: 91819
Hi I am using a Spartan XC3S400 FPGA. Initially after poweron one particular signal read_enable does not get enabled. It is a simple logic. There is just one additional signal controlling it. And this control signal has the expected status level as i observed with chipscope. But the read_enable signal does not act until the system is resetted. This read enable signal is connected to the input of asynchronous FIFO. Once resetted there are no problems. My question is, is there some way on how to find out why the signal is behaving differently by looking at the schematic by the Xilinx after synthesis . And whether has it got to do something with being connected to the Asynchronous FIFO. Are the FIFO inputs tristated after the FPGA is configured from the PROM on poweron until resetted. The asynchronous FIFO is from Xilinx Coregen. Thank you for your help regards vasuArticle: 91820
> when monitored by the chipScope logic analyzer, it seems like the > sensor does not acknowlege when i write the device address Plus write > bit. im sure the device address i sent is correct. the sensor im using > is KAC-9630 from Kodak. Please let me know if someone can figure this > out. Maybe it's a timing issue. Some I2C devices are slower than others. Does your chipScope analyzer show any drop in the clk signal at all? Does the Kodak part have any address pins that augment the address? Good luck, I know how frustrating the I2C bus can be. Brad Smallridge aivision.comArticle: 91821
Kim Enkovaara wrote:
> Mike Treseler wrote:
>
>> I use single process entities
>> with no signal declarations.
>> I declare process variables for every
>> local register and output port.
>> I use functions to create values
>> and procedures to collect and name
>> all repeated command sequences.
>
>
> That can be a dangerous style. Some tools are quite bad with VHDL
> procedures and functions.
I use modelsim, leo and quartus and have
not had a bit of trouble.
I have seen a some formal tools to create just insane
> netlists out of procedures, some synthesizers can have problems with them.
I would not use such a tool.
-- Mike Treseler
Article: 91822svasus@gmail.com wrote: > Hi > I am using a Spartan XC3S400 FPGA. > Initially after poweron one particular signal read_enable does not get > enabled. It is a simple logic. There is just one additional signal > controlling it. > And this control signal has the expected status level as i observed > with chipscope. > But the read_enable signal does not act until the system is resetted. > This read enable signal is connected to the input of asynchronous FIFO. It might if you posted the code for this read_enable signal. > Once resetted there are no problems. That's why you use a reset ... > My question is, is there some way on how to find out why the signal is > behaving differently by looking at the schematic by the Xilinx after > synthesis . Yes, you could simulate your design. > And whether has it got to do something with being connected to the > Asynchronous FIFO. Are the FIFO inputs tristated after the FPGA is > configured from the PROM on poweron until resetted. The asynchronous > FIFO is from Xilinx Coregen. No, the FIFO outputs are not tristated. -aArticle: 91823
Anthony Ellis wrote: > As a licensed user of the Xilinx PCI32 core, where does one get a more comprehensive > PCI testbench (stimulus generator) than what comes with the Xilinx PING example. QuickLogic have a nice set of PCI models for both master and target, but I would imagine that they prefer you use them to design-in one of their chips. -aArticle: 91824
Brad Smallridge wrote: > Maybe it's a timing issue. Some I2C devices are slower than others. Does > your chipScope analyzer show any drop in the clk signal at all? Does the > Kodak part have any address pins that augment the address? Good luck, > I know how frustrating the I2C bus can be. The other option could just be to scan the bus - do a read from every address to see whether you get any ACK at all. This could help if you have a bug in the addressing - I know I've had some confusion before when reading datasheets for certain parts. The other point of course is just checking with an oscilloscope, to check whether you've got something that's not being pulled up/down hard enough, and hence not registering. Jeremy
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