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hirenshah.05@gmail.com wrote: > hi, > > I am implementing data encryption standard using verilog. can anyone > suggest efficient algorith to implemnt data encryption standard ( > especially S-box). > The S-Boxes are the easy part. They are just LUTs.Article: 92126
Duane wrote:
> johnp wrote:
>> The suggestion to recode the Verilog to look like:
>> always @(posedge clk)
>> sig4 <= (sig1 & ~sig2) ? sig3 : sig4;
>>
>> concerns me since a smart synthesizer would recognize this to be
>> EXACTLY the sime code, just written in an odd way.
>That would require that the synthesis tool specifically look for the
>default value on the right be the same signal as is being assigned to.
>While I suppose it is possible that a synthesis tool might do that, I
>kind of doubt it.
I'd bet it would. I am continually amazed at how good the synthesis
optimizers are getting.
OP can probably force the results he's asking for by using a 'keep'
attribute, if he really wants to. I don't know how to express it in
Verilog, but the VHDL code follows. See 'KEEP' in the constraints guide
for Verilog syntax.
I couldn't resist on this one, had to do the experiment, and Antti is
100% right in this instance. P/R into an XC2V40-5 with CE logic in the
same LUT along with the CE MUX gives _slower_ results than putting only
the CE logic into a LUT and using the CE pin and and its built-in CE
MUX:
Using CE pin: under 2 ns.
Using LUT : over 2 ns.
An odd thing is that XST infers 2 FFs for the LUT version.
(Did someone say pushing a rope?)
Nice that the synthesis tools keep getting better, and there are less
opportunities to second guess them.
Regards,
John
entity CE_Inferral is
Port ( clk : in std_logic;
rst : in std_logic;
a_in : in std_logic;
b_in : in std_logic;
c_in : in std_logic;
q_out : out std_logic);
end CE_Inferral;
architecture Behavioral of CE_Inferral is
signal q : std_logic;
signal a : std_logic;
signal b : std_logic;
signal c : std_logic;
signal d_lut : std_logic;
attribute keep : string;
attribute keep of d_lut : signal is "true";
begin
q_out <= q;
--d_lut <= c when a = '1' and b = '0' -- Uncomment these two lines
-- else q; -- for 'CE' in LUT logic (slower)
process( clk )
begin
if RISING_EDGE( clk ) then
a <= a_in; -- sync port inputs
b <= b_in;
c <= c_in;
if rst = '1' then
q <= '0';
else
-- q <= d_lut; -- Uncomment this 1 line for 'CE' in LUT logic
if a = '1' and b = '0' then -- Uncomment these 3 lines
q <= c; -- to use CE pin on FF with only
end if; -- 'a and not b' function in a LUT
end if; end if;
end process;
end Behavioral;
Article: 92127
Hi ,
Has anyone implemented a design using Aurora over Rocket IO in
EDK...If so please point me to the correct document....
What I am trying to do is to hook up a BRAM in an OPB core to
send data to the Rocket I/O through Aurora and then on the Receiver
side, use a BRAM to receieve the data...
I wrote the code but I have lots of questions regarding
generating the differential clock and the RESET..So if anyone can help
me out, then that would be great..
Thanks in advance....
--
Parag
Article: 92128Hi, can someone tell me where I can access (read/write) the horizontal long lines in the Virtex-II architecture. In the FPGA editor the long lines are connected to blocks on either ends of the FPGA and they are connected to the switch boxes of the CLBs. However, when implementing small designs the routing tools seem to drive the long lines only from the ends. Can they be driven and read from each CLB, too? Regards HeikoArticle: 92129
Hi, I am dealing with reconfigurable computing and relocating modules within a Virtex-II FPGA. In order to save and restore the current flip-flop states I need to determine where to find the states in a readback stream. All necessary equations were provided in xapp151, but only for the Virtex not the Virtex-II FPGAs. Given the row and column, as well as the slice and FF, I would like to know the frame and the offset within the frame where to find the flip flop state. Is there anyone who can help. Regards HeikoArticle: 92130
JustJohn wrote: > Duane wrote: > > johnp wrote: > >> The suggestion to recode the Verilog to look like: > >> always @(posedge clk) > >> sig4 <= (sig1 & ~sig2) ? sig3 : sig4; > >> > >> concerns me since a smart synthesizer would recognize this to be > >> EXACTLY the sime code, just written in an odd way. > >That would require that the synthesis tool specifically look for the > >default value on the right be the same signal as is being assigned to. > >While I suppose it is possible that a synthesis tool might do that, I > >kind of doubt it. > > I'd bet it would. I am continually amazed at how good the synthesis > optimizers are getting. The OP is using XST 6.2.03. It's not that smart. Regards, Allan.Article: 92131
Since my 'sig3' vector is four bits wide, the signal from the CE logic needs to fan out to the 4 flip flops. Now we get routing delay. Antti's example may be correct, but for the 4 bit wide destination, I think I get a performance penalty. I love synthesis, but... It sure would be nice to have any easier way to direct it! In any event, it sure beats schematics. John ProvidenzaArticle: 92132
Hi Manfred, This message is being incorrectly printed. It is a bug that it is printed, and it has been corrected (by removing the message) in Quartus II 5.1 SP1. Ignore the message -- your design functionality and optimization are fine. Basically our most recent FPGA families (Stratix, Stratix II, Cyclone, etc.) use a different method of storing delay information for optimization during the fitting procedure. This message says that new method is not being used. For APEX that is expected -- it uses a different method, and always will. Regards, Vaughn Betz [v b e t z (at) altera.com]Article: 92133
I am implemnting S-box by using case statement. 6'b000000: SB[1]=4'd14; 6'b000010: SB[1]=4'd4; 6'b000100: SB[1]=4'd13; 6'b000110: SB[1]=4'd1; 6'b001000: SB[1]=4'd2; 6'b001010: SB[1]=4'd15; 6'b001100: SB[1]=4'd11; 6'b001110: SB[1]=4'd8; 6'b010000: SB[1]=4'd3; 6'b010010: SB[1]=4'd10; 6'b010100: SB[1]=4'd6; 6'b010110: SB[1]=4'd12; 6'b011000: SB[1]=4'd5; 6'b011010: SB[1]=4'd9; 6'b011100: SB[1]=4'd0; 6'b011110: SB[1]=4'd7; 6'b000001: SB[1]=4'd0; 6'b000011: SB[1]=4'd15; 6'b000101: SB[1]=4'd7; 6'b000111: SB[1]=4'd4; 6'b001001: SB[1]=4'd14; 6'b001011: SB[1]=4'd2; 6'b001101: SB[1]=4'd13; 6'b001111: SB[1]=4'd1; 6'b010001: SB[1]=4'd10; 6'b010011: SB[1]=4'd6; 6'b010101: SB[1]=4'd12; 6'b010111: SB[1]=4'd11; 6'b011001: SB[1]=4'd9; 6'b011011: SB[1]=4'd5; 6'b011101: SB[1]=4'd3; 6'b011111: SB[1]=4'd8; 6'b100000: SB[1]=4'd4; 6'b100010: SB[1]=4'd1; 6'b100100: SB[1]=4'd14; 6'b100110: SB[1]=4'd8; Is this efficient way? Or is any other method t o implemnt LUTArticle: 92134
There are several possible solutions. 1. Stratix II clocks don't have to come from dedicated clock inputs to reach the global clock networks. The dedicated clock inputs can reach the global clock networks without using any regular routing, so they result in less clock delay to your registers, and that is useful if you need a fast Tco to another chip. However, any I/O can reach dedicated global clock networks by using regular routing to get to the global network drive point. A clock constructed this way will have extra delay to reach each register, but the skew within the clock domain will still be fine. This will happen automatically when you compile in Quartus II -- no need to do anything. If you have 16 or fewer clocks, you are done. 33 MHz PCI has a loose enough Tco that you should comfortably meet it even with the larger clock delay that results from not using a dedicated clock pin. 2. Quartus II only promotes non-PLL clocks to "chip-wide global networks" by default. There are 16 of these. If you have more than 16 clocks in your design, you probably want to use the 32 regional (1/4 chip) global networks as well. You can tell Quartus II to put a clock on a regional network by using the assignment editor to make a "global signal = regional clock" assignment to the clock signal. Since regional clocks can only reach 1/4 of the chip, you should make these assignments carefully -- ensure that all fanouts of the clock can be placed in the quadrant of the chip near the I/O driving the clock. Generally you should use up all 16 chip-wide global clocks first, and then use the regional clocks for the lower fanout clocks, or clocks that need faster Tco on registers driving output I/Os (regional clocks have lower delay). If you have a clock that fits in 1/2 the chip, but not in 1/4 of the chip, use "global signal = dual regional clock" to combine two regional clock networks into one 1/2 chip-wide network for that clock signal. This burns two of your 32 regional clocks though. 3. You can use locally routed clocks. Such clocks use general routing, and have higher skew than the dedicated (chip-wide global or regional) clock networks. However, they have low delay if the clock fanout is low, and hence can be good for Tco to an output I/O. To minimize the skew on such networks, you should make the assignment: "maximum clock arrival skew = 0" to the clock signal. This will tell the fitter to optimize this signal for low-skew. The skew we achieve is generally quite reasonable on such clocks (~300 - 600 ps, with higher fanout clocks near the upper end of the range), but it still isn't as good as that of a global clock. Hence I'd recommend the global clock approaches (#1 and #2) first. If you need more than 48 clocks (a lot!) use this technique to make low-skew locally routed clocks for the lowest fanout clocks. 4. You could redesign your circuit to use fewer clocks, as other posters have suggested, but I suspect from your description that that is not necessary, and Stratix II in fact has plenty of clocks for what you need. Regards, Vaughn Betz Altera [v b e t z (at) altera.com] "huangjie" <huangjielg@gmail.com> wrote in message news:1132486415.614548.139310@g49g2000cwa.googlegroups.com... > Hi All! > > I have a project that use Altera Stratix II 2S180 as ASIC prototype. > Because the ASIC > has too many interface therefor too many clk and some of the clk does > not route to > fpga's dedicated clk pin ,for eg, pci clk does route to an normal I/O > pin . > > Because the fpga and the board expensive,the BOSS does not want to make > a new board. > After I read throught 2S180's datasheet and throught a lot ,I found > this is a very hard problem because : > 1 ) Global buffer tree's delay is very long , about 5ns. > 2 ) From PAD to core , normal I/O has about 1ns's delay, > 3 ) I can't use PLL to compensate I/O delay or global buffer delay > since PLL's input must > be a clk input pin or a global buffer. > 4) Inserting LCELL into datapath of input signal will make my Tco > bad. > > How can I deal with this ? Is altera here ? >Article: 92135
VPR does not count the transistor area used inside a logic block. It counts the area in the routing per tile and prints that out. To get a total area, you have to add in the area of the logic block, not including the routing or routing interfaces (output pin drivers & muxes before input pins). So basically just create a program or spreadsheet or layout to estimate the area of your new logic block. Then add in the routing per tile area from VPR, and use that to compute a height & width for a tile. That defines the physical length of your routing wires, which then lets you compute the R & C of your various routing wires. That must be entered in the VPR .arch file to get accurate timing results with your new CLB. I have a separate program from VPR that computes the area of "cluster-based logic blocks" (they are much like generalized Altera LABs). If your logic block fits into that category, let me know and I can email you that program. Some of the papers on my "academic" web site (www.eecg.toronto.edu/~vaughn) describe what cluster-based logic blocks are, if you need more info. Hope this is clear. Regards, Vaughn Betz [v b e t z (at) altera.com] <vivekgarg330@gmail.com> wrote in message news:1132379405.063121.69480@g49g2000cwa.googlegroups.com... > Hi, > > We need to evaluate new CLB architectures for routing area and delay. > In VPR how can I specify my CLB architecture accurately. In > architecture file all I could find out was that we can change number of > LUTs and their input size. But in our architectures apart from LUTs we > also have some extra combinational modules. Is it possible for me to > specify no of transistors that my CLB takes in VPR and then let VPR do > placement and routing because that will give routing area and delay > according to our architecture. If yes where should I do that. > I feel that currently VPR finds out number of transistors of a CLB > based on number of LUTs present but I was unable to figure out where > does it use this information after going through the code. > > Kindly help me if someone has gone through the code or has modified it. > > Thanks and regards, >Article: 92136
Hi Heiko, heiko@csse.uwa.edu.au wrote: > I am dealing with reconfigurable computing and relocating modules > within a Virtex-II FPGA. In order to save and restore the current > flip-flop states I need to determine where to find the states in a > readback stream. All necessary equations were provided in xapp151, but > only for the Virtex not the Virtex-II FPGAs. Given the row and column, > as well as the slice and FF, I would like to know the frame and the > offset within the frame where to find the flip flop state. The "-l" option to bitgen will give you an ASCII Logic Allocation file, that gives you these sort of details. > Is there anyone who can help. Maybe try the partial-config mailing list. Lots of expertise there. Be warned - partial reconfiguration is a cruel mistress! http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/index.html Cheers, JohnArticle: 92137
Thank you Austin. I'll check the documentation and secure the state machines. Regards, Nick On Tue, 22 Nov 2005 15:55:00 -0800, Austin Lesea <austin@xilinx.com> wrote: >Nick, > >I assume that Cyclone works similarly to our own FPGAs in that all flip >flops are inti tally set to 0 by the house-cleaning (initialization >prior to configuration) at power on. > >You can check this by reading their manual on what happens during power >on and configuration. > >Then, during configuration, the state of the flip flops for logic may >(or may not) be set, or reset to a state as specified by the bitstream >(depends on the device, and its options when being configured). > >If you have designed the state machine with no hidden states, and in >such a way that it will always return to a known state given a set of >good inputs, there is no need for a reset. > >In the case of a 1-hot state machine (very popular in FPGAs) this also >means that detection of having more than one state set (more than one >flip flop) must decode and send you back to a known state of having only >one state active! > >Austin > >Nick wrote: > >> Hello, >> >> I'm in the final phase of a design in VHDL on a Cyclon, and i am >> really puzzled by something. >> I do not have an external reset pin, so how can i ensure that my >> states machines start at the right state, that all values are well >> initialized and everything ? >> >> It seems to work as it is now, but i couldn't find any litterature on >> this subject. >> >> Many thanks >> NickArticle: 92138
Hi,
I am wondering if it is possible to implement adding peripheral(s)
to the local memory bus of the Microblaze so as to guarantee that these
peripheral(s) have single cycle access to the data and instruction
memories of the processor. I am wishing to model very tightly coupled
coprocessors, and I have custom peripherals that I have created, but I
dont know how to go about connecting them in such a way to guarantee
that they have complete single cycle access to the Microblaze's
memories, even if it means risking a clock frequency penalty on the
processor. Any solutions will be more than appreciated. Thanks!!
Scott
Article: 92139Andy Peters wrote: > Andreas wrote: >> Hello, >> I just got a new FPGA board (from Avnet, Xilinx Virtex4). The problem is >> that I never programmend a FPGA before. I use VHDL for programming and >> Precision from Mentor for synthesis. Xilinx ISE 7.1 is used for >> place-and-route. On the FPGA board is a push button. Within my VHDL code >> I defined a process, which is sensitive to the rising edge of the signal >> associated with that push button (I want to know, when the button is >> pushed). >> >> pb_proc: process (push_button) is >> begin >> if push_button'event and push_button='1' then >> .... >> >> The problem is, that Precision recognizes that signal and the associated >> pad as a clock input and the during place-and-route operation, ISE >> produces the following error message: >> >> ERROR:Place:645 - A clock IOB clock component is not placed at an >> optimal >> clock IOB site The clock IOB component <push_button> is placed at site >> IOB_X2Y112. The clock IO site can use the fast path between the IO and >> the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. >> If this sub optimal condition is acceptable for this design you may set >> the environmentvariable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this >> message to a WARNING and allow your design to continue. > > You got this error because your VHDL instantiates a flip-flop whose > clock is the signal push_button, and your constraints told the tools to > put the signal push_button onto a pin that's not a global clock pin. > > You should spend some quality time with the XST manual, especially the > sections that detail how certain structures are inferred from VHDL. > The instantiation of a flip-flop is exactly what I wanted as well as the connection between the push_button and the clock input of the flip-flop. The only thing I don't want is that the synthesis tool treats the push_button as an external clock input although it is connected to the clock input of a flip-flop. I've read the documentation before I wrote any posting, but I couldn't find the answers I need. >> P.S.: another question of topi: When I setup my Design, I have to chose >> technology(Virtex-IV), Device(4vlx25ff668) and Speed Grade(-10 or -11). >> Which speed grade do I have to choose? Do not know it. > > Choose the speed grade that matches the device installed on your board. > >> Does the board support -10 and -11? > > Dunno, look at the chip, or read the documents that came with your > board. I did it before my posting, but coudn't find any information. Thanks, AndreasArticle: 92140
Nick <nick@no-domain> wrote:
>I'm in the final phase of a design in VHDL on a Cyclon, and i am
>really puzzled by something.
>I do not have an external reset pin, so how can i ensure that my
>states machines start at the right state, that all values are well
>initialized and everything ?
I've never used Cyclon, but I'd expect that there is an asynchronous
reset and/or set applied as part of configuration. If so, then what
you need to worry about is the first clock. As the reset will be
released at different times across the chip, some FFs may be released
from reset before others, and a statemachine may end up in a non valid
state that will prevent correct functioning. This can be solved by
using safe statemachines, so that all non-valid states map into valid
states in at most a few clocks, or by using statemachines with no
invalid states at all. A binary counter, for example, has only valid
states.
Now, suppose there was a "reset" statemachine that held reset to the
rest of the statemachines until the configuration was released and
all?
This is fairly simple, put in a binary counter or similar safe
statemachine with more than enough counts (or states) to make sure
that the reset is released, have it hold synchronous reset to the
reset of the design until count complete, then release it. Example in
VHDL follows:
use ieee.numeric_std.all;
entity
...
architecture
...
Signal reset : std_logic := '1';
Signal count : unsigned(3 downto 0) := "0000";
begin
--
-- This counter is used to hold all statemachines in reset for the
-- first 8 or so clocks after the end of configuration.
--
RESET_STATE: process(clk)
begin
if rising_edge(clk) then
reset <= count(3);
if count(3) = '1' then
count <= count + 1;
end if;
end if;
end process;
(rest of code)
Note that not all synthesis tools can correctly handle this. Some of
the old tools would have problems with this. While I've used similar
tricks in the past, I have not verified this exact code.
Note that the number of bits in count needs to be large enough to get
well past the end of asynchronous reset, and not so large as to cause
startup delays.
--
Phil Hays to reply solve: phil_hays at not(coldmail) dot com
If not cold then hot
Article: 92141Hi John, thanks for you advice. Actually, I knew the -l option and I worked with that for months, but I could not remember that the frame address and offset is in there as well. Do you also have an idea in which frame at which offset to put the a new value for each flip flop, so that after downloading the manipulated bitstream to the FPGA and asserting reset, you have restored a previous state. I will try to mail to the other mailing list as well. HeikoArticle: 92142
Hi Scott, ssirowy@gmail.com wrote: > I am wondering if it is possible to implement adding peripheral(s) > to the local memory bus of the Microblaze so as to guarantee that these > peripheral(s) have single cycle access to the data and instruction > memories of the processor. LMB is a single-master bus. You can put peripherals on it, but they cannot bus master - only the microblaze can. I am wishing to model very tightly coupled > coprocessors, and I have custom peripherals that I have created, but I > dont know how to go about connecting them in such a way to guarantee > that they have complete single cycle access to the Microblaze's > memories, even if it means risking a clock frequency penalty on the > processor. Any solutions will be more than appreciated. Thanks!! BRAM is dual ported. Connect one port of a BRAM to the microblaze instruction or data LMB, and the other port to your peripheral. Arbitrating simultaneous write accesses to a shared memory is up to you. The default connectivity with MicroBlaze systems is to tie one port of the BRAM to ILMB, and the other to DLMB. You'll need to watch your bus address mapping scheme, and might need to go for a custom link script to support it. Regards, JohnArticle: 92143
Are there any equations, how to calculate the frame address and the frame offset out of the X, Y etc. position of the flip-flops or do I have to re-engineer them out of the ll file? HeikoArticle: 92144
Hello FFT guru's I am implementing 2048 point FFT on Virtex as a part of my small project at uni. i want to put couple of questions.. please help me to your best as i am a starter...:) I have gone through couple of IEEE papers and i have found that i should use (Mixed Radix alg).i.e. like Radix4 and Radix2 butterflies to implement this algorithm. i have an understanding to use total of 6 stages...i.e. 5 stages of Radix-4 and 1 stage of Radix-2 operations. Question 1. Is the aforementioned technique the best in terms of speed and area that operation will acquire.? Ans----> Question 2. I am very much confused about the Which ARCHITECTURE that i should use...??(any web links would be great) ?? what would be the input to 2048 point fft... ??l know it has to be streaming data.. where will that input come from....my understanding says that i have to feed x(n) n=0....2047 with data... but its kind of confusing me ... i am checking this site for reference...http://www.xilinx.com/ipcenter/catalog/logicore/docs/xfft.pdf Answer----> Quetion 3.----> my tutor also asked me to start my project with mapping "one kernel element of FFT to virtex-II board"...So what is the kernel element of FFT ?? .---->is this the Twiddle factor(e to the power of (-j*n*k*2*pi/N)) that is multiplied with the inputs... Ans-------> Question 4....----> (Most important for me)----------------> can i know the exact steps that i should follow to implement 2048 point FFT on Virtex2 pro.this answere will solve all my problems.... Ans---------> Question 5....Can any one tell me any website for getting source code for FFT in VHDL(for my reference) because i am using windows machine and the code from opencores(cf_fft) can be downloaded as .tz format...which i am not able to untar... and it is in verilog as well... Answer -----> AjArticle: 92145
Hi Andreas, I don't know how to do it in Precision but in XST you can tell the tool to use no GlobalClockBuffer at all (Xilinx Specific Options Tab). Then any Input can be (ab)used as a Clock input using normal routing resoources instead the global clock net. For one FF and Testing this might be OK. In a large design you will get into big trouble. Now, If you are a newbie you brobably intend to use the button for manual clocking, to allow single stepping of your design. Beware!!! Just imagine a simple counter driving some LEDs. What you expect is that it increments with every press on the button. But what happens will be random outputs to appear on your LEDs. Why is that? Because your Button bounces several times each time you press it and/or release it. Not very usefull, is it? To overcome this problem you need two things: One is a clock divider driven by the onboard Clock Oscillator. The Output can be something about 100Hz and needs only to create an impulse of a single clocks length. This signal can be used as a clock enable for a debouncing circuit which is described in the Xilinx synthesis template. Then you can use your button(s) for Input, and even (ab)use this Output signal as a Clock Signal. But remember: Only for testing SMALL designs! You also need to constrain the number of GCLK Buffers to 1. Have a nice Synthesis EilertArticle: 92146
don't you love spell checkers :-) "Symon" <symon_brewer@hotmail.com> wrote in message news:438356c9$0$41149$14726298@news.sunsite.dk... > > "Simon Peacock" <simon$actrix.co.nz> wrote in message > news:4382ea2a$1@news2.actrix.gen.nz... > > What happened to the text on the front of the chip.. if its been "erased" > > then you are trying to reverse engineer a design.. that will void the > > warrantee :-) > > > Voiding the warrantee could be much more serious to his own health than > reverse engineering the part! > > http://www.answers.com/warrantee > > ;-) > > Cheers, Syms. > >Article: 92147
When Quartus runs it prints a little message that all flip-flops that have a reset high.. will be high after initialisation.. or words to that effect. Simon "Austin Lesea" <austin@xilinx.com> wrote in message news:dm0b4s$4g56@xco-news.xilinx.com... > Nick, > > I assume that Cyclone works similarly to our own FPGAs in that all flip > flops are inti tally set to 0 by the house-cleaning (initialization > prior to configuration) at power on. > > You can check this by reading their manual on what happens during power > on and configuration. > > Then, during configuration, the state of the flip flops for logic may > (or may not) be set, or reset to a state as specified by the bitstream > (depends on the device, and its options when being configured). > > If you have designed the state machine with no hidden states, and in > such a way that it will always return to a known state given a set of > good inputs, there is no need for a reset. > > In the case of a 1-hot state machine (very popular in FPGAs) this also > means that detection of having more than one state set (more than one > flip flop) must decode and send you back to a known state of having only > one state active! > > Austin > > Nick wrote: > > > Hello, > > > > I'm in the final phase of a design in VHDL on a Cyclon, and i am > > really puzzled by something. > > I do not have an external reset pin, so how can i ensure that my > > states machines start at the right state, that all values are well > > initialized and everything ? > > > > It seems to work as it is now, but i couldn't find any litterature on > > this subject. > > > > Many thanks > > NickArticle: 92148
Just to correct you .. Just because 125 MHz is the reference... that doesn't mean it can't be an ungated clock too!!! you don't have to multiply the reference up .. you just run the entire device at 125 MHz and "ignore" the other clocks. However .. the suggestion by Vaughn is also good.. lots of clocks (if you can use them) Simon "huangjie" <huangjielg@gmail.com> wrote in message news:1132707932.396888.98280@f14g2000cwb.googlegroups.com... > I have understood your idea, and know why yours work but mine cann't . > Just because your slow clock is slow ,and mine is very fast. > How can I deal with 125M clocks just as it is 2M ? How fast my > "reference" for 125M ? > Perhaps I can use a group of some phase-shift clocks to get a clk > enable signals. > Thank you again! >Article: 92149
Depends... Synplify will turn that into a ROM or LUTs depending on what it thinks is best... Simon <hirenshah.05@gmail.com> wrote in message news:1132720626.914663.274130@g43g2000cwa.googlegroups.com... > I am implemnting S-box by using case statement. > > > 6'b000000: SB[1]=4'd14; > 6'b000010: SB[1]=4'd4; > 6'b000100: SB[1]=4'd13; > 6'b000110: SB[1]=4'd1; > 6'b001000: SB[1]=4'd2; > 6'b001010: SB[1]=4'd15; > 6'b001100: SB[1]=4'd11; > 6'b001110: SB[1]=4'd8; > 6'b010000: SB[1]=4'd3; > 6'b010010: SB[1]=4'd10; > 6'b010100: SB[1]=4'd6; > 6'b010110: SB[1]=4'd12; > 6'b011000: SB[1]=4'd5; > 6'b011010: SB[1]=4'd9; > 6'b011100: SB[1]=4'd0; > 6'b011110: SB[1]=4'd7; > 6'b000001: SB[1]=4'd0; > 6'b000011: SB[1]=4'd15; > 6'b000101: SB[1]=4'd7; > 6'b000111: SB[1]=4'd4; > 6'b001001: SB[1]=4'd14; > 6'b001011: SB[1]=4'd2; > 6'b001101: SB[1]=4'd13; > 6'b001111: SB[1]=4'd1; > 6'b010001: SB[1]=4'd10; > 6'b010011: SB[1]=4'd6; > 6'b010101: SB[1]=4'd12; > 6'b010111: SB[1]=4'd11; > 6'b011001: SB[1]=4'd9; > 6'b011011: SB[1]=4'd5; > 6'b011101: SB[1]=4'd3; > 6'b011111: SB[1]=4'd8; > 6'b100000: SB[1]=4'd4; > 6'b100010: SB[1]=4'd1; > 6'b100100: SB[1]=4'd14; > 6'b100110: SB[1]=4'd8; > > > > Is this efficient way? > > Or is any other method t o implemnt LUT >
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