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Hi all, i am having a problem with timing simulation. i am getting proper outputs for functional simulation and post-synthesis simulation.But after implementing the circuit on FPGA devices it is giving some kind of error message that "compnent declaration not fonud" because of this i am not able to do the timing simulation i am using activeHDL6.3 for VHDL and synplify pro for synthesis and implementation can anyone help me out in this issue thanks, Regards RamakrishnaArticle: 92651
I have a 16V (PALCE16V8H-15PC/4) that has lost it's program, and need a new copy made. Can you do it for me? Cost? The part is an HP 08751-80130, and I have a good one that could be copied from, and I have a new blank to be copied to. Stu Aplin 310-640-7262 > Oil4warwrote: 16V* is most pupular low cost chip. from 1984, Abel 1.1 and many DOS > stuff. If you want, I can burn a CD for you. I block E-mail in > this AOL. > > hope your E-mail addr. is real one.Article: 92652
Hi all, to be more clear about my problem with timing simulation after i implement it using xilinx it is creating one TIME_SIM.VHD and TIME_SIM.SDF file under the folder "timing" it has an identifier "X_INV_PP" in both files when i compile TIME_SIM.VHD it is giving an error "Unknown identifier "X_INV_PP"" Cannot find component declaration did anyone come across similar kind of problem.please help me out thanks, Regards RamakrishnaArticle: 92653
In the "Fairchild TT Applications Handbook" I wrote in 1973: "Adding two numbers of the same sign, or subtracting two numbers of opposite sign might generate a result which cannot be rpresented by a given word length. This is overflow. It must be detected and used to initiate some corrective routine. Overflow occurs when the Carry out of the sign position differs from the carry in to the sign position. OVERFLOW = Cs XOR C(s+1) When the carry into the most significant position is not directly accessable, it can be generated in one of several ways. The simplest is to use the equation: Cs = Ss XOR As XOR Bs, which makes OVERFLOW = Ss XOR As XOR Bs XOR C(s+1)" Has math changed in the past 32 years ? I bet there are lots of more famous textbooks that offer similar or more detailed descriptions. This stuff has been known for 100+ years... Peter Alfke, Xilinx ApplicationsArticle: 92654
In my chip I need seperate internal clock. can any one suggest how to implement internal clock using verilog.Article: 92655
Hi all! Can some one (hopelly prom Xilinx) tell me why when I connect a monitor to ML403 Borad, the board doesn't boot (error LED ON) if the monitor in ON BEFORE the board. But if I turn ON the board BEFORE the monitor all is ok. Very strange !! Is there some way to fix it ? A+ MehdiArticle: 92656
Hi all, I am currently working in PCB design and layout stream. And have decided to go for Hardware Modeling Verification stream. I have done my startup course in VLSI and I am well verse with VHDL, Verilog and a bit of SystemC (as I have started learning it on my own). If anybody out there is already in this field and would like to share some thin with me; please email. Akhil.Article: 92657
<hirenshah.05@gmail.com> schrieb im Newsbeitrag news:1133595471.974967.252570@g49g2000cwa.googlegroups.com... > In my chip I need seperate internal clock. > > can any one suggest how to implement internal clock using verilog. > Altera MAX2, Lattice MachXO,EC,XP do provide direct access to onchip oscillator - check out the datasheets Spartan3, Virtex4 and (some other virtex) also do have on chip oscilator but Xilinx has decided to prevent the regular user to gain access to this resource so the only solution for Xilinx FPGAs is to use in fabric oscillator. This can be implemented by different means. One example infabric oscillator IP core can be downloaded from the link below http://xilant.com/component/option,com_remository/Itemid,53/func,select/id,1/ AnttiArticle: 92658
>>It's an asynchronous signal going into your state machine. >>All the classic things can go wrong. The complicated one is >>metastability. The simple one is that it meets setup for >>some parts of your FSM but not for others. > >Ah ok, I forgot that the signal can be used at some different places >with different setup times. >Thanks, I hope everything is clear now. Even if it only goes to one place, you still have to consider Metastability. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 92659
Using RiscWatch with Xilinx FPGA's for powerpc. I have Xilinx 7.1 package with xilinx fpga boards , as well ML310 with virtex 2p devices ,on which powerpc and microblaze architectures are supported. I wanted to run an application on this powerpc architecutre and debug it. As i am using powerpc so i think risc watch debugger would be better. But my question is does xilinx provide support for riscwatch. I mean, i have a base system created using EDK 7.1. And thus i have a bitstream corresponding to this base system with powerpc as processor. Now i want to run application and collect some statistics. For this i want to use risc watch debugger. I don't know whether gdb available with EDK is of use for powerpc platform, because i want register level information.Article: 92660
"Pankaj" <pankajgode@gmail.com> schrieb im Newsbeitrag news:1133609780.108306.290080@z14g2000cwz.googlegroups.com... > Using RiscWatch with Xilinx FPGA's for powerpc. > I have Xilinx 7.1 package with xilinx fpga boards , as well ML310 > with virtex 2p devices ,on which powerpc and microblaze architectures > are supported. > I wanted to run an application on this powerpc architecutre and debug > it. > > As i am using powerpc so i think risc watch debugger would be better. > But my question is does xilinx provide support for riscwatch. > I mean, i have a base system created using EDK 7.1. And thus i have a > bitstream corresponding to this base system with powerpc as processor. > Now i want to run application and collect some statistics. For this i > want to use risc watch debugger. > I don't know whether gdb available with EDK is of use for powerpc > platform, because i want register level information. > reg level access is avilable from edk supplied debugger no need to use riscwatch anttiArticle: 92661
"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag news:438e3273_1@x-privat.org... > "Jim Granville" <no.spam@designtools.co.nz> wrote in message > news:438e0c5c$1@clear.net.nz... >> >> Don't you just love "SW that knows best", and tries to outhink the user >> ! :( >> This should be allowed, with a warning - but I can think on one caveat - >> possibly Xilinx do not have test coverage on unbonded IOs, and so >> gives no guarantee they actually work ? >> >> Peter/Austin ? - comments on user access to unbonded IO resource ? >> > So, to use unbonded IOBs in my V2PRO design I use something like:- > > NET "all_your_base" LOC="UNB700"; > > in my UCF file. You need to turn off the DRC check in the "Generate > Programming File" properties. Anyone able to try this in V4? FPGA editor > is a good way to get the names of the unbonded IOBs. > > Cheers, Syms. > Hi Symon, yes it works in V4 too, but the correct LOC syntax is NET iopad LOC="UNB_X2Y53"; and with 7.1 tools for V2/P the UCF should be NET iopad LOC="NOPAD45"; not UNBxxx http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,3/ there is IOB based onchip oscillator that can be used in unbonded IOB :) Cheers, AnttiArticle: 92662
Chloe You left out a few facts that might help the group understand where your problem has come from. (1) The behavoural model - was this a simulation output from ISE e.g. post translate model or one that you have written independently? (2) Did your model have signals relationships defined by timing relationships or by clock edges? Could it have been a model that might synthesise? (3) Do you have a macro (edif, ngc etc) that ISE might have picked up instead of the behavioural model? Translate report should tell you that. One thing to check is that you are not picking up a locally stored copy rather than one from a remote directory if that is what you are expecting. One trick if you are getting the unxpected is to change something in the design file that you can easily monitor in the real world, e.g. output your internal clock to a pin, and if that does not happen you know you are picking up something unexpected. Another thing to check is if increment synthesis is turned off in XST. There have been issues with this I believe. Finally if you have not loaded any service packs you should do so. Service pack 4 is the latest and can be loaded direct without loading any of the prior service packs. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost FPGA Development Board. http://www.enterpoint.co.uk "Chloe" <chloe_music2003@yahoo.co.uk> wrote in message news:1133512674.118506.213030@g43g2000cwa.googlegroups.com... > Calling all FPGA experts! > > I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter > 6.0a simulator. The FPGA which I am downloading my design onto is a > Spartan IIE (it's on the Spartan IIE LC Development Kit, with an > XC2S300E device). > > After synthesizing, implementing and programming the design onto the > FPGA, I tested the outputs of the FPGA on the development kit using a > digital oscilloscope. However, I was not getting the signals I wanted. > After simulating the design on ModelSim, and comparing the simulated > outputs with the actual FPGA outputs, I realised that the behavioral > model of the design was somehow transferred onto the FPGA, instead of > the place-and-routed model. > > I checked the synthesis report, but there were no errors. There were > some warnings, but they were unimportant (certain ports were assigned > but not used), thus, neglected at the moment. There were also no timing > violations. I also checked all the reports under "Implement Design", > and there were no errors. > > Can anyone tell me why the behavioral model was transferred onto the > FPGA instead of the place-and-routed model? Is that even possible? Can > anyone advise me on the methods of overcoming this problem? > > I'd be happy to provide any extra information you need. > > Thanks very much in advance. > > Regards, > Chloe >Article: 92663
On Fri, 02 Dec 2005 08:43:00 -0800, Austin Lesea <austin@xilinx.com> wrote: >John, > >You bring up an interesting point. > >Yes, the squeaky wheel gets the grease (or in this case, the gorillas >get the bananas). > >But, I had a strange thought: how many start-ups, consultants, etc. are >there that need prototyping quantities (1 to 3 parts)? > >Does it make sense to have a program for smaller outfits (which are no >less important to Xilinx, as CIS** was small once, too)? > >Is this the real case for web-based product availability? A tube of 25 ES parts might mean nothing to CIS**, but could make a dozen startups very happy. Obviously you don't want to undermine distributors business, so you may have to severely limit quantities per user, or maybe come in 10% above book price, but 2-off samples for prototyping isn't the business they really want anyway (IME, from both sides of the corporation/hobbyist fence). I'll retract this when I start seeing PayPal buttons instead of (or even alongside) price enquiry registration forms on distributor websites. - BrianArticle: 92664
Try to power cycle the board several times. If that helps you are more likely to see a problem described in Answer Record #22179 (http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22179) - Peter GaLaKtIkUs™ wrote: > Hi all! > Can some one (hopelly prom Xilinx) tell me why when I connect a monitor > to ML403 Borad, the board doesn't boot (error LED ON) if the monitor in > ON BEFORE the board. But if I turn ON the board BEFORE the monitor all > is ok. > Very strange !! > Is there some way to fix it ? > > A+ > Mehdi >Article: 92665
Hello, We have a FPGA system, listed below, and are looking for a consultant for doing development work on this system. Preferred location in Southern California. Must have experience in FPGA development, signal processing, PC Host interface and bidirectional data transfer; algorithms. Requirement is immediate, work to be done in 3 to 6 months. System description VMETRO PMC-FPGA03 (Xilinx XC2VP50 Virtex-II Pro=99 FPGA) VMETRO TPMB2, PCI_X carrier board Boards are in Host PC type system running under Windows XP. Development is a real time image processing; images are transferfered from a digital camera (IEEE 1394) to the host PC, and to the FPGA carrier board via PCI-X bus. Details will be provided to the later on. Please provide a summary of related experience. Send to nahum@oksi.com Thanks!Article: 92666
GaLaKtIkUs=99 wrote: > Can some one (hopelly prom Xilinx) tell me why when I connect a monitor > to ML403 Borad, the board doesn't boot (error LED ON) if the monitor in > ON BEFORE the board. But if I turn ON the board BEFORE the monitor all > is ok. > Is there some way to fix it ? If pushing the system ace reset button on the board clears the error and allows the board to boot, then the problem is the probably the power up reset circuit inside the system ace chip. It has been our experience that the power on reset in the system ace is not 100% reliable, and a power on reset IC is a really good idea. We never did characterize what it was about our design that caused this problem, could have been power supply sequencing or ramp rates. The external monitor might be leaking enough current into one or more signal pins to raise the power rail on the board to something slightly higher than zero, thus changing the power up characteristics. Alternately, the additional load could be changing the rate at which one or more of the power supplies is coming up. We have used the TC542702 voltage detector from Microchip on a number of different designs with the system ace. This will keep the ace in reset until the 3.3v rail hits 2.7V. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 92667
I already tried the reset button and it didn't solve the problem. The only solution was to turn off both of the card and the monitor, than turn on the card BEFORE the monitor. MehdiArticle: 92668
I am new to CPLD/FPGA programming. I have recently perchaged CoolRunner II EDK. I am trying to implement example VHDL Traffic Light Controller program from the Design Kit Programmable logic guide. I successfully completed Synthesis, Translate and fitted the design in xc2c256-7tq144. Thereafter, when I run "Simulate Post-Fit Model" the ModelSim XE 6.0a is invoked, simlation runs upto successful simulation and stops. When I view the simulation result in the wave-default window, I don't see FSM outputs "red_light" , "amber_light" , and "green_light" changed from low. Both the clock and reset input signal are toggling OK. If anybody knows why the ouput are not displayed on the wavefrom windows. I would appreciate any help on this issue. Thanks in advance. Best regards, Nabin ShresthaArticle: 92669
"Antti Lukats" <antti@openchip.org> wrote in message news:dmsdq1$lcp$1@online.de... > Hi Symon, > > yes it works in V4 too, but the correct LOC syntax is > > NET iopad LOC="UNB_X2Y53"; > > and with 7.1 tools for V2/P the UCF should be > > NET iopad LOC="NOPAD45"; > > not UNBxxx > Hi Antti, It seems there are two types of unbonded IOBs. One set called NOPADxx, another set called UNBxxx. Both seem to work in this type of application. My guess is that the UNBxxx type have a pad on the silicon for a bond wire which can be used in a package with a lot of balls (if you see what I mean!), whereas the NOPADxx ones are not used in any package so don't have this pad. Guesswork though! Cheers, Syms.Article: 92670
Hi all, i got a problem in building 32X32 LUT ROM from 32X1 ROM which is there in unisim library i am not able to figure the thing how we have to use 32 "init" values when using for generate the 32X32 ROM using 32X1 ROM can anyone help me in understanding the usage of INIT for the ROM thanks Regards Ramakrishna BachimanchiArticle: 92671
Under the installation path for Xilinx tools should be /doc/usenglish/docs/lib/lib.pdf. In the index for this document search for ROM32x1. There are examples for both verilog and vhdl for init usage. You also may want to use coregen. I think there is a ROM instantiator .... which lets you enter the parameters via a GUI. ( ughhh) If there is still a problem, post back. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado based Xilinx Consultant email : jretta@rtc-inc.com web : www.rtc-inc.com <bachimanchi@gmail.com> wrote in message news:1133656231.227983.325300@g44g2000cwa.googlegroups.com... > Hi all, > i got a problem in building 32X32 LUT ROM from 32X1 ROM which is there > in unisim library > i am not able to figure the thing how we have to use 32 "init" values > when using for generate > the 32X32 ROM using 32X1 ROM > can anyone help me in understanding the usage of INIT for the ROM > > thanks > > > Regards > Ramakrishna Bachimanchi >Article: 92672
The INIT value sets the contents of your RAM or ROM in this case. As posted already by John look in the Libraries Guide. You will also find an instantiation template under the lightbulb icon in ISE. Beware though I don't believe that 32xn RAM/ROM primative components are working in Spartan-3 due to the fact that some of the LUT based ram/rom features were removed from the architecture. I have not checked this recently and the primatives may be now converted to macros and hence work. Any one from Xilinx listening care to comment or check the detail in the latest Libraries Guide? The init values should be used on an individual basis so the one that you use on bit0 the string is made up of all you bit0's out together as zero. You may find using the alternative components RAM32X8S or RAM16X8S easier as they are working in bytes. These components can be considered as re-writeable ROMs (just don't write to get a normal ROM operation) as they can have loaded values at power-up unlike a conventional stand-alone SRAM. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost High Performance Spartan-3 Development Board. http://www.enterpoint.co.uk <bachimanchi@gmail.com> wrote in message news:1133656231.227983.325300@g44g2000cwa.googlegroups.com... > Hi all, > i got a problem in building 32X32 LUT ROM from 32X1 ROM which is there > in unisim library > i am not able to figure the thing how we have to use 32 "init" values > when using for generate > the 32X32 ROM using 32X1 ROM > can anyone help me in understanding the usage of INIT for the ROM > > thanks > > > Regards > Ramakrishna Bachimanchi >Article: 92673
Greetings All, For the OS X readers out there, I found this article to be very usefull for enabling Spotlight indexing of source files - it needs to be repeated for each extension (.vhdl, .vhd, etc.) http://www.macosxhints.com/article.php?story=2005052015041510 Cue Intel and XST on DarWine?... --- cdsArticle: 92674
> I'm currently doing some tests on an ML461 board, using IDELAY to > shift in some DDR signals. I am shifting 80 signals in groups of 8. > Unfortunately, some signals do not get shifted, i.e. some of the > IDELAY module do not seem to respond to INC & CE. I'm seeing this > in chipscope. I have tried (1) instantiating a single IDELAYCTRL, then > let the tool replicate the rest and (2) instantiating all IDELAYCTRL > and manually assigning them to the > appropriate regions. It didn't help. > > Has anyone encountered such behaviour? > > I also found this on the xilinx website: > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=20125 > > Does this mean that I have to invert the clock going into the IDELAY > block? This is one solution. The other solution is to constrain the design so that the IDELAY control signals meet the half clock period timing. Either way, you need to use separate timing contraints on the IDELAY control signals so the timing analyzer will correctly analyze the timing on those paths. HTH, Jim
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