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TôF wrote:
> I'm learning two ways of describing a system .... Either by using
> systemC and the other way, VHDL !
> What are the differences, the real advantages of one compared to the
> other ?
Heres a code comparison.
http://www.cs.ucr.edu/~ksewell/research/systemc/comparison.htm
If you already know C++ systemC might be easier
to learn for simulation models.
If you are interested in synthesis,
or if you don't know either language
vhdl might be a better choice.
SystemC synthesis does a conversion
to vhdl (or verilog) in any case,
so it might be a good idea to learn both.
-Mike Treseler
Article: 92501Hi, >It's an asynchronous signal going into your state machine. >All the classic things can go wrong. The complicated one is >metastability. The simple one is that it meets setup for >some parts of your FSM but not for others. Ah ok, I forgot that the signal can be used at some different places with different setup times. Thanks, I hope everything is clear now. MichaelArticle: 92502
thanks a lot for the comparaison sheet, it's very interesting ! I'm also interested in synthesis because I use vhdl essentially for system synthesis. So my question is : what the interest in learning SystemC ? In the industrial world, which one is the most used ?Article: 92503
PeteS posted: >Newsgroups: comp.arch.fpga, sci.electronics.design >From: "PeteS" <p...@fleetwoodmobile.com> - Find messages by this >author >Date: 30 Nov 2005 07:18:19 -0800 >Local: Wed, Nov 30 2005 8:18 am >Subject: Re: Q-bus or Unibus bus transactions in FPGA? >Reply | Reply to Author | Forward | Print | Individual Message | Show >original | Report Abuse Richard wrote: > [Please do not mail me a copy of your followup] > Jon Elson <jmel...@artsci.wustl.edu> spake the secret code > <438CE854.8010...@artsci.wustl.edu> thusly: > >Richard wrote: > >>Has anyone implemented a Q-bus or Unibus bus interface logic in an > >>FPGA that is freely available or documented? [...] > >Not on an FPGA (PDP-11 was before their time) but the bus protocol > >is quite simple. [...] > Well, I didn't mean to imply that the FPGA was concurrent with the > PDP-11 :-), I was more hoping that another retro computing hobbyist > would have made something I could bootleg! > I suppose I'll have to do my own bus handshake implementation from the > Q-bus docs (I think my processor or peripheral handbook that came with > the 11/03 has one in there somewhere). > I wonder how hard it would be to get a PCB fabbed with the bus edge > connector? PeteS wrote: >There was a discussion of this on S.E.D. quite recently with one of >it's denizens successfully getting a board with gold fingers >fabricated at a very reasonable price. >X-Posted to s.e.d. for comments >Cheers >PeteS I designed a Q-bus interface card about 16 years ago using a CPLD for decoding logic and another CPLD for board functions -- both written in ABEL. I used DEC's ChipKit for logic buffering to the bus itself. The physical dimensions of the board fingers came from one of DEC's manuals. Alas, it was 16 years ago and 2 companies ago, so I don't have much to offer in the way of code. But, it has been done before, so it can be done again! As for the logic interface, there are so many logic families that modern FPGA's I/O can be programmed for, I'm sure something will match the characteristics of the Q-bus (Unibus), then you don't need the ChipKit. Cheers TomArticle: 92504
Antti Lukats wrote: > "al99999" <alastairlynch@gmail.com> schrieb im Newsbeitrag > news:1133348095.999307.101310@o13g2000cwo.googlegroups.com... > >>Peter Alfke wrote: >> >>>After some thinking: >>>1. >>>You can divide the input load by using "zero-delay buffer chips" with >>>up to 8 outputs and very little skew betrween them. And you can even >>>compensate for the (assumed constant) skew between the outputs.(see >>>below) >>>2. >>>You can drive all IDELAYs from the fabric, using internal fan-out. >>>Again, you an compensate away the routing delay differences. >>> >>>The compensation is done by setting all IDELAY values be to the same, >>>and then observing the parallel captured word. It should always be >>>either all zeros or all ones. If it's different, change the responsible >>>IDELAY accordingly. >>> >>>Obviously, this compensation deos not cover drift with temperature and >>>Vcc. >>> >>>Peter Alfke, Xilinx Applications >> >>Hi, >> >>Is this two different approaches or two steps of one process? For 2) >>above, I connected the input pin to 16 IDELAY blocks but got this >>error: >> >>FATAL_ERROR:Pack:pktv4iob.c:737:1.24.2.1 - Input buffer CH1_IBUF drives >>multiple >> DELAYCHAIN symbols. The implementation tools can not pack the >>design. >> Process will terminate. To resolve this error, please consult the >>Answers >> Database and other online resources at http://support.xilinx.com. If >>you need >> further assistance, please open a Webcase by clicking on the >>"WebCase" link >> at http://support.xilinx.com >> >>How can I fan out the one input without getting this!! >> >>Thanks >> >>Al >> > > > Hi Al, > > I think Peter did suggest the impossible, there is no connections in the > FPGA that would allow single signal to be routed to multiply IDELAY > elements. The only possibility would be to use unbonded IOBs as route > through, but I have not found an option that allows the use of unbonded IOBs > in user design :( Don't you just love "SW that knows best", and tries to outhink the user ! :( This should be allowed, with a warning - but I can think on one caveat - possibly Xilinx do not have test coverage on unbonded IOs, and so gives no guarantee they actually work ? Peter/Austin ? - comments on user access to unbonded IO resource ? -jgArticle: 92505
Nanditha - I was able to use the Aurora core using the Virtex-2 device. However I get errors when using a Virtex-4 device. 1)What line rate and data width did you choose. I am using the default line rate of 3.125 and lane width of 4. 2)Is this a single lane design? Yes. 3)Which simulator are you using? Model Sim 6.0c SE 4)Are you running the example simulation provided(sample_test.do)? The instructions for running this simulation are provided in the Getting started Guide. Yes I am. I was able to simulate it using a Virtex-2 device but I get the following errors with a virtex-4: # ** Error: (vsim-3733) ../src/mgt_wrapper.vhd(748): No default binding for component at 'gt11_custom_inst'. # (Generic 'rx_los_threshold' is not on the entity.) # Region: /sample_tb/aurora_sample_2_i/aurora_module_i/mgt_wrapper_i/gt11_custom_inst # ** Error: (vsim-3733) ../src/mgt_wrapper.vhd(748): No default binding for component at 'gt11_custom_inst'. # (Generic 'rx_los_invalid_incr' is not on the entity.) # Region: /sample_tb/aurora_sample_2_i/aurora_module_i/mgt_wrapper_i/gt11_custom_inst # ** Error: (vsim-3733) C:/Xilinx/vhdl/src/unisims/unisim_SMODEL.vhd(25803): No default binding for component at 'gt11_swift_bw_1'. # (Generic 'rx_los_threshold' is not on the entity.) # Region: /sample_tb/aurora_sample_2_i/aurora_module_i/mgt_wrapper_i/gt11_custom_inst/gt11_swift_bw_1 # ** Error: (vsim-3733) C:/Xilinx/vhdl/src/unisims/unisim_SMODEL.vhd(25803): No default binding for component at 'gt11_swift_bw_1'. # (Generic 'rx_los_invalid_incr' is not on the entity.) # Region: /sample_tb/aurora_sample_2_i/aurora_module_i/mgt_wrapper_i/gt11_custom_inst/gt11_swift_bw_1 I'm sure I am doing something wrong because I recall a Xilinx Tech Support person telling me that the Aurora Core has work for the Virtex-4. I was working with the gt11_custom but quit using it once the support person told me that it does not work (which seemed like a funny thing to admit to your customer) and have moved onto the Aurora Core. I am trying to modify some re-use code from a previous project that used the Virtex-2pro's RocketIO for SL240 interface. However the MGT on the Virtex-4 has not been very compliant. Thanks for your reply and any help would be much appreciated. JPArticle: 92506
Nevermind, I figured out why I was getting that error. Seems my modelsim.ini was changed from another project. Any comments you still have will grateful. I doubt if solving this error is going to push me over the edge in getting it to work the way I want it to. Thanks, JPArticle: 92507
TôF wrote:
> thanks a lot for the comparaison sheet, it's very interesting !
> I'm also interested in synthesis because I use vhdl essentially for
> system synthesis. So my question is : what the interest in learning
> SystemC ?
The attraction is that you can run simulations
using only a C++ compiler.
The downside is no direct synthesis
and immature tools.
The systemC standard is at version 1.0
> In the industrial world, which one is the most used ?
vhdl and verilog.
-- Mike Treseler
Article: 92508Frank wrote: > <electronics_designer@hotmail.com> wrote in message > news:1133256655.320119.255470@f14g2000cwb.googlegroups.com... > >>Frank schreef: >> >> >>>The machine is 16702B Logic analyzer, but the module inside >>>is 16750A 400MHz State 2GHz Timing zoom 4MSa Analyzer. >>>I am pretty new to this machine, where can I download the >>>operating manuals? >> >>Seach the agilent website: >>http://www.agilent.com/ >> >>Beste Regards, >>Roel >> > > Thank you. I have got the manual for 16750A. > > While you're at it, you should order (for free) a CD with the latest SW: http://software.cos.agilent.com/LogicAnalyzerSW/ Al P.S. You'll probably want to install it after you get it :-)Article: 92509
Dear all, I place a timing constraint on a pair of registers (from, to) either side of some logic. After I run the ISE 6.3 toolchain, I look at the actual delays for the constraint in Timing Analyzer. The constraint seems to have been applied from the source register which I specified as my destination, to a register or pad elsewhere in the design. The constraint is applied to logic other than specified. Any suggestions? Cheers, Dave.Article: 92510
I think these parts may be obsolete. I can't find any suppliers in the USA. I need package type FG456. Does anyone know where I can buy them? Thanks, Dave.Article: 92511
Gabor wrote: >GPE wrote: > > >>I did one in a Xilinx XC3064... many, many years ago. >>Unfortunately, I ditched all the documentation a few years ago... and have >>done a complete brain purge. Might still have the DEC documentation, >>though. I'll check on Wednesday. >> >>It wasn't too hard of a bus to interface to and is quite slow. >> >>Good luck, >>Ed >> >> >> > >I did interfaces many years ago for both buses using PAL's for logic >and >74F-series parts for bus drive. Probably 5V 74FCT parts would also >work. >If you're serious about Unibus, you'll need to know that the connector >pin-out >in the DEC documentation is for the bus extender cable and not where a >board plugs in. A and B connectors are not used for plug-in cards, >only >C, D, E and F. I got a copy of the magic document from someone who >got it from someone who did PC board work for DEC. > > Not absolutely true, for Unibus. There were "quad" boards, and "hex" boards. Usually the hex boards just used the extra space for circuitry, and not the A&B connector pins. You have to know how the backplane section is wired, because there are a bunch of different ones for different types of interface boards. > > JonArticle: 92512
Richard wrote: >[Please do not mail me a copy of your followup] > >hmurray@suespammers.org (Hal Murray) spake the secret code ><vaadnSJVHo9ezBDeRVn-hQ@megapath.net> thusly: > > > >>>I suppose I'll have to do my own bus handshake implementation from the >>>Q-bus docs (I think my processor or peripheral handbook that came with >>>the 11/03 has one in there somewhere). >>> >>> >>Does it have the specs for the bus transcievers? I remember using >>some special DEC chip. >> >> > >I do recall seeing the specs for the DEC bus trainceiver chip in the >handbook, yes. > > I remember one was the SP380. One of the features is it wouldn't drag down the bus if the interface was powered down. Of course, that would break the bus grant continuity, so it was a pretty useless feature, at least for Unibus. JonArticle: 92513
Dave Roberts <anon@anon.com> wrote: > I think these parts may be obsolete. I can't find any suppliers > in the USA. I need package type FG456. Does anyone know where > I can buy them? Look at www.nuhorizons.com. They list 53 pcs XC2V250-6FG456C in stock. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 92514
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:438e0c5c$1@clear.net.nz... > > Don't you just love "SW that knows best", and tries to outhink the user ! > :( > This should be allowed, with a warning - but I can think on one caveat - > possibly Xilinx do not have test coverage on unbonded IOs, and so > gives no guarantee they actually work ? > > Peter/Austin ? - comments on user access to unbonded IO resource ? > So, to use unbonded IOBs in my V2PRO design I use something like:- NET "all_your_base" LOC="UNB700"; in my UCF file. You need to turn off the DRC check in the "Generate Programming File" properties. Anyone able to try this in V4? FPGA editor is a good way to get the names of the unbonded IOBs. Cheers, Syms.Article: 92515
GaLaKtIkUs™ wrote: > Ok ... So what simulator to use? > -I bought the "MicroBlaze & PowerPC Development Kit" (with ML403 > Board). > -I'm using Linux as OS. > -I'm a PHD Student who decided to make a sacrifice by buying that > kit. I can't afford ModelSim PE/SE (since it seems that XE is not > available on Linux). > I'm really confused and unhappy with that :( > > Mehdi > Maybe you can ask ModelSim for a university license or maybe your university has a license server ... SylvainArticle: 92516
Hi JP, Please refer to Answer Record # 21577(http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryI D=1&getPagePath=21577) on the Xilinx website for info on how to resolve the problem you are seeing. Basically, what has happened is, the RX_LOS_THRESHOLD_INCR and RX_LOS_THRESHOLD attributes were removed from the smartmodel in 7.1i Service Pack 3. Hence the error that you are seeing about these attributes not being present in the entity. What you will need to do is delete all mentions of these attributes from the MGT wrapper file (src/mgt_wrapper.v). Doing this should get the simulation running. Let me know how it goes or if you have any other issues/questions. Thanks, Nanditha "JarJarJP12" <jpnguyenk@gmail.com> wrote in message news:1133384165.916823.300170@g47g2000cwa.googlegroups.com... > Nanditha - > > I was able to use the Aurora core using the Virtex-2 device. However I > get errors when using a Virtex-4 device. > > 1)What line rate and data width did you choose. > I am using the default line rate of 3.125 and lane width of 4. > > 2)Is this a single lane design? > Yes. > > 3)Which simulator are you using? > Model Sim 6.0c SE > > 4)Are you running the example simulation provided(sample_test.do)? The > instructions > for running this simulation are provided in the Getting started Guide. > Yes I am. I was able to simulate it using a Virtex-2 device but I get > the following errors with a virtex-4: > > # ** Error: (vsim-3733) ../src/mgt_wrapper.vhd(748): No default binding > for component at 'gt11_custom_inst'. > # (Generic 'rx_los_threshold' is not on the entity.) > # Region: > /sample_tb/aurora_sample_2_i/aurora_module_i/mgt_wrapper_i/gt11_custom_inst > # ** Error: (vsim-3733) ../src/mgt_wrapper.vhd(748): No default binding > for component at 'gt11_custom_inst'. > # (Generic 'rx_los_invalid_incr' is not on the entity.) > # Region: > /sample_tb/aurora_sample_2_i/aurora_module_i/mgt_wrapper_i/gt11_custom_inst > # ** Error: (vsim-3733) > C:/Xilinx/vhdl/src/unisims/unisim_SMODEL.vhd(25803): No default binding > for component at 'gt11_swift_bw_1'. > # (Generic 'rx_los_threshold' is not on the entity.) > # Region: > /sample_tb/aurora_sample_2_i/aurora_module_i/mgt_wrapper_i/gt11_custom_inst/ gt11_swift_bw_1 > # ** Error: (vsim-3733) > C:/Xilinx/vhdl/src/unisims/unisim_SMODEL.vhd(25803): No default binding > for component at 'gt11_swift_bw_1'. > # (Generic 'rx_los_invalid_incr' is not on the entity.) > # Region: > /sample_tb/aurora_sample_2_i/aurora_module_i/mgt_wrapper_i/gt11_custom_inst/ gt11_swift_bw_1 > > I'm sure I am doing something wrong because I recall a Xilinx Tech > Support person telling me that the Aurora Core has work for the > Virtex-4. I was working with the gt11_custom but quit using it once > the support person told me that it does not work (which seemed like a > funny thing to admit to your customer) and have moved onto the Aurora > Core. I am trying to modify some re-use code from a previous project > that used the Virtex-2pro's RocketIO for SL240 interface. However the > MGT on the Virtex-4 has not been very compliant. > > Thanks for your reply and any help would be much appreciated. > > JP >Article: 92517
If I change one input to a LUT, and leave the other three inputs unchanged, such that both the original and new output will be the same (e.g., both '1'), can there be a glitch in the output?Article: 92518
"Gabor" <gabor@alacron.com> writes:
> If you're serious about Unibus, you'll need to know that the connector
> pin-out in the DEC documentation is for the bus extender cable and not
> where a board plugs in. A and B connectors are not used for plug-in
> cards, only C, D, E and F.
The AB slots at the ends of a backplane are the Unibus proper.
Single-board peripherals plug into "SPC" (Small Peripheral Controller)
slots which are the CDEF slots. The AB slots that are not at the ends
of a backplane may be MUD (Modified Unibus Device) or Extended Unibus
(22-bit addressing) slots, and should generally be avoided.
Some peripheral modules are hex size and go into an SPC slot. They
plug into the AB slots, but don't use any signals from those slots
(with the possible exception of power).
For the Unibus electrical spec and pinout (AB only) see the PDP-11
Unibus Design Description and the PDP-11 Bus Handbook:
http://bitsavers.org/pdf/dec/unibus/UnibusSpec1979.pdf
http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_BusHandbook1979.pdf
SPC and MUD generally are electrically the same as Unibus, but with
different pinouts. For the pinouts you have to refer to some of the
processor manuals. For instance, the SPC pinout is on page 3-8 of the
PDP-11/44 User Guide, or in tabular form on page 5-26:
http://bitsavers.org/pdf/dec/pdp11/1144/1144_UsersGuide.pdf
That manual has the standard Unibus and MUD slot pinouts in a tabular form
on page 5-25.
Extended Unibus (22-bit addressing), also known as "speical bus" is only
used on a few of the AB slots of the processor backplane of the 11/24
and 11/44. I haven't seen any docs on it other than in the field
maintenance print sets for those processors, and the maintenance manuals
and prints for the memory that supports it (MS11-Lx, MS11-M, MS11-Px):
http://bitsavers.org/pdf/dec/pdp11/memory/EK-MS11L-UG-001.pdf
http://bitsavers.org/pdf/dec/pdp11/memory/EK-MS11P-TM-001_Tech_Oct82.pdf
http://bitsavers.org/pdf/dec/pdp11/memory/MP00672_MS11L_engDrw.pdf
http://bitsavers.org/pdf/dec/pdp11/memory/MP01477_MS11P_Sep82.pdf
Briefly, address lines A18L through A21L are present on pins BE2, BE1, AP1,
and AN1 of Extended Unibus slots, but are used for other purposes on normal
Unibus slots.
For the Qbus electrical specs and pinout, see the PDP-11 Bus Handbook
listed above. But that doesn't cover some of the later Qbus extensions
such as 22-bit addressing. For that, see Appendix F of the KDF11-B manual:
http://bitsavers.org/pdf/dec/pdp11/1123/KDF11BA_UsersManual.pdf
Implementing the Qbus or Unibus protocols in an FPGA is not too difficult.
More of a challenge now is implementing bus drivers and receivers that
meet the electrical specifications. I've previously posted some notes
on interface chips to Usenet, but I can't find it right now. My notes
are at:
http://www.brouhaha.com/~eric/retrocomputing/dec/interfacing/chips.html
Article: 92519"GaLaKtIkUs™" <taileb.mehdi@gmail.com> writes: > I just succesfully installed ISE BaseX on Linux. All is OK. > BUT the ISE simulator is not present in the list of available > simulators in project properties. Xilinx only offers the ISE Simulator in the Windows version of ISE 7.1i. You can see that in the ISE feature table on the web site. It is rumored (but unconfirmed) that ISE Simulator will be available on Linux in the 8.1i release, expected "Real Soon Now".Article: 92520
My experience has shown that new releases of Quartus do not prevent older designs from loading. Quartus has always made the transition painless. I've been able to take designs done in 4.1 right up to the latest 5.1. Keep in mind that I'm using the full licensed version; maybe the web edition is different, but that would surprise me. You mention in your post the word "allegedly"; have you actually tried to open up the design using the latest 5.1 web edition? <cs_posting@hotmail.com> wrote in message news:1133367914.170415.268980@g47g2000cwa.googlegroups.com... > Does anyone know if it's possible to download older versions of the > Quartus web edition, such as 4.0 or 4.1? I'm inheriting a design which > allegedly doesn't work in the current version... >Article: 92521
If your design does not compile for any reason in 5.1 and it did compile in an earlier version, in all proabability it is a bug that we would fix. First try compiling with Quartus II 5.1. If it fails, please open a Service Request using mysupport. Subroto Datta Altera Corp. <cs_posting@hotmail.com> wrote in message news:1133367914.170415.268980@g47g2000cwa.googlegroups.com... > Does anyone know if it's possible to download older versions of the > Quartus web edition, such as 4.0 or 4.1? I'm inheriting a design which > allegedly doesn't work in the current version... >Article: 92522
Good question, often asked: No glitch, and that behavior is guaranteed by the decoding structure. Further, if you change two pins, and you know that the output is identical for all 4 permutations of these 2 bits, there also is no glitch. And you can stretch that to 3 pins, where all 8 permutations must give identical results to avoid a glitch, although this last one may be an unrealisticl situation. I have answered this particular question many times over the past 15 years. Peter Alfke, Xilinx ApplicationsArticle: 92523
The Virtex-2 family that you are referring to is very much alive, and is the best-selling family in Xilinx history. Remember, the newly introduced families are "better", more capable, and faster, but the bulk of our shipments is obviously into systems that have reached production status and were designed a few years ago. For today's design-starts, the designers must carefully evaluate whether the older families are "good enough" or whether the better features and sometimes lower price of the newer family are more important. These are general statements, not Xilinx specific. Peter AlfkeArticle: 92524
On Wed, 30 Nov 2005 13:45:03 -0800, Mike Treseler <mike_treseler@comcast.net> wrote: >The systemC standard is at version 1.0 SystemC is at version 2.1 with a free library: http://www.systemc.org
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