Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi Kedar, If you are using Quartus Integrated Synthesis, there is no need (or ability in the tool) to black box the altgxb megafunction, since Quartus has the complete implementation available to it. If you are using Synplify or Precision Synthesis, then you can and should black box this megafunction, and Quartus will fill in the implementation later. If you are using Quartus Integrated Synthesis and your goal is to make synthesis fast by partitioning up your design so you can synthesize sub-components separately, I'd recommend you use the Quartus incremental compile feature to divide up your design, and then incrementally synthesis (or synthesize & fit) various parts of the design, while other parts are left unchanged. See Chapter 1 of the Quartus handbook at http://www.altera.com/literature/quartus2/lit-qts-synthesis.jsp for information on how to use incremental compilation. Regards, Vaughn Betz Altera v b e t z (at) altera.com <kedarpapte@gmail.com> wrote in message news:1132905627.298382.157520@g49g2000cwa.googlegroups.com... > Hi All, > > I am working on a design targeted to Altera Stratix Gx > I am using high speed macro (gxb macro) in the design. > > while doing implementation I want to elaborate the hierarchy by using > "Maintain Hierarchy" option in Synthesis. > but I don't want to elaborate "gxb macro" part > how do I do it...? > can I declare that instance as black box...? > how to do that in Quartus II...? > > Thanks > Regards > Kedar >Article: 92676
Hi all, I will be giving a NetSeminar this coming Wednesday on Power Optimization for FPGA designs. I'll go over three main topics: - Automatic Power Optimization via CAD: how the Quartus II power optimization algorithms (new in version 5.1) work, how you control them, and how much power they save for various designs. - Design techniques that can further lower power. - How to use the Power Optimization Advisor and Design Space Explorer tools to search for the best power CAD settings and power design tips for your design. See http://www.altera.com/education/net_seminars/all/ns-power-optimize.html for more details and the registration link. I think anyone interested in power will find this interesting -- we're seeing a dynamic power reduction of 20% for the average design, just by moving from Quartus II 5.0 to Quartus II 5.1 and turning on the power optimization features. More savings are possible with the design techniques we'll go over. I hope to see you there, and to get some good questions from the regulars on this newsgroup. Regards, Vaughn Altera [v b e t z (at) altera.com]Article: 92677
On Fri, 02 Dec 2005 11:53:05 -0500, Jerry Avins wrote: > You can make Fred's solution more practical by adding an operational > amplifier that can deliver the difference between +5 and -5 currents. > > +------+-------------------------------------------->+5v > | | > | | +--------------->+3.3v > +----+ | +----+ > | 10v| | |3.3v| +---------+3v > +----+ ++-+ +-+--+ +----+ > | |R1| +----------+ | |3.0v| > | ++-+ | |\ | | +-+--+ > | | +---|-\ | | | > | | | +---+----------+------+---------> 0v > | +--------|+/ > | +--+ |/ > | |R1| > | ++-+ > | | > +------+----------------------->-5v > The main problem with this scheme is that if either of +5 or -5 volt rails tries to draw more than a few mA, the opamp won't be able to source or sink that much current, so that rail will droop. (The other rails will just follow whatever they've been grounded to.) This isn't too bad, but it'll cause the _other_ rail to suddenly spike by the same amount in the opposite direction. So, a 5A spike on the +5 rail might cause the -5 rail to go to -10V, possibly smoking something funny (like components.) I'd say you need some kind of beefy totem pole output to drive it, meaning a couple of power transistors in addition to the circuit above. Now, is it worth it? Particularly when you can buy a +-5V regulated supply that will source 20A for $50. --- Regards, Bob Monsen Music is the pleasure the human soul experiences from counting without being aware that it is counting. - Gottfried LeibnizArticle: 92678
Vaughn Betz wrote: > Hi all, > > I will be giving a NetSeminar this coming Wednesday on Power Optimization > for FPGA designs. I'll go over three main topics: > > - Automatic Power Optimization via CAD: how the Quartus II power > optimization algorithms (new in version 5.1) work, how you control them, and > how much power they save for various designs. > - Design techniques that can further lower power. > - How to use the Power Optimization Advisor and Design Space Explorer tools > to search for the best power CAD settings and power design tips for your > design. > > See http://www.altera.com/education/net_seminars/all/ns-power-optimize.html > for more details and the registration link. > > I think anyone interested in power will find this interesting -- we're > seeing a dynamic power reduction of 20% for the average design, just by > moving from Quartus II 5.0 to Quartus II 5.1 and turning on the power > optimization features. More savings are possible with the design techniques > we'll go over. I hope to see you there, and to get some good questions from > the regulars on this newsgroup. Here's a question: Are those power savings speed-agnostic, or do you also get a small improvement in speed (lower CL = Lower power ) or a small degrade in speed ( lower Drive = slower, but less power .. ) -jgArticle: 92679
Hi Vaughn Betz , Thank you very much for replying me I got only 1 responce for my Q.. wondering why...? Any ways actually as you are from Altera corporation I think I can discuss the problem in detail with you...? First thing is I am stuck with one problem not in Synthesis or Implementation but in Post Implementation simulations. I have already posted my queries on Altera my support but still unsolved. Let me discuss my problem now. 1. I am simulating my design using highspeed gxb macros to check actual internal delays of my design. I am using Quartus II 5.0 and Modelsim AE 6.0c 2. I am instanciating my design entity more than once in the RTL and I want to check the the interface and glue logic combo delays between the two instances. 3. My design has a parrallel interface but to check it at high speed I have used gxb SERDES. Similarly in test bench I am using one more gxb component to parallelise the design output and check it. 4. for this set up when I use a flat netlist and .sdo file the simulation runs fine, but when I use"maintain hierarchy" option for the netlist the siimulation give me wrong library format error for all the stratix GX specific internal components in the net-list. In this case it give an error for "altgxb". 5. Altera support suggested me to remove SERDES gxb macro instanciated in test bench. this thing works and my purpose got solved of checking internal delays. but the Q remains that by using "maintain hierarchy" option I am changing the design netlist then why I need to remove components from test bench and that removed the library format error...? Please help me if you can Regards KedarArticle: 92680
You are asking the wrong people.. you need to ask a patent attorney. They are better at filling in the grey areas which is what you want... After all.. if what you were doing was smart.. it would already be done.. and if it is.. you had better have a better attorney then they do :-) besides.. you are asking a public domain news group.. therefore anything you try to patent later and have describe here has been released into the public domain before the patent has been applied for :-) Simon "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1133550146.547748.109980@g14g2000cwa.googlegroups.com... > Hi Brad, > Thank you for your response. > > 1. Yes, the 'legal' should change to 'acceptable'. > > 2. I agree with your opinion: "If you want a simpler and easy to follow > explanation using the > equation notation, you can put it in the preferred embodiment section. > " > The question arises when the logic equation in LUT is described in the > preferred embodiment section, but their correspondent logical circuits > are not described in a provisional patent application. When I file for > regular patent application later, claims would be invalid because the > appropriate circuits are not described in provisional patent > application. > > So I want to know if there is an approved patent with logical equation > in its claims or if there is someone having experienced similar > scenario, but was declined by USPTO. > > Thank you. > > Weng >Article: 92681
'...' is a pause as opposed to '.' a stop. Even text to speech recognises this. I will try to refrain... maybe But reverse engineering can be done to anything. A copyright message is all you need to 'stop' it but that isn't usually enough. I myself have been designing for 20+ years and have purposefully released things as GPL so they can be public. Other stuff (hardware and software) is most defiantly not public. I have some rather flash UARTS, Ethernet Interfaces and E1 units. These add value to both my pay-packet each month and to my companies standing. They also make sure that each company review, there is a reason to keep me employed. I've also started studying towards a BE-Tech and possibly a Masters. So why do I think its not OK to copy? There are multiple reasons above. The only time I would recommend breaking a copyright is when the company is defunct and you need to do an update but even then someone might have walked away with the copyright/patent. Simon "Symon" <symon_brewer@hotmail.com> wrote in message news:4390a9a6_3@x-privat.org... > Hi Simon, > He could well have a legitimate reason for reverse-engineering the core. > Perhaps he wants to see if anyone is infringing his own patent? Although, > from his post, I guess not. Also, I believe it's lawful to reverse-engineer > something which is protected by trade secrets rather than a patent. That is, > unless you stole the thing you're reverse-engineering. > Still, as you say, best not to advertise it whatever the reasons. > Cheers, Syms. > > p...s... I think there's something wrong with your full stop key... In a lot > of your posts it keeps coming out in duplicate or triplicate... ;;;---))) > > "Simon Peacock" <simon$actrix.co.nz> wrote in message > news:439019ae$1@news2.actrix.gen.nz... > > For starters.. you shouldn't mention "reverse-engineer" and "Xilinx core > > generator" in here.. this is a monitored group by both Altera and > > Xilinx... > > both will not appreciate it. > > (not to mention those of us who make our living from the IP business) > > > > Simon > >Article: 92682
The 32 Init values are quite simple. Each ROM has one bit, each init value holds the value for that bit. You can make a simple loop structure and procedure which will take 32 bit parameters and divide them into individual bits thereby allowing a sensible RAM/ROM structure to be created. I have done this for a 32x8 single port RAM and it works quite well. Simon <bachimanchi@gmail.com> wrote in message news:1133656231.227983.325300@g44g2000cwa.googlegroups.com... > Hi all, > i got a problem in building 32X32 LUT ROM from 32X1 ROM which is there > in unisim library > i am not able to figure the thing how we have to use 32 "init" values > when using for generate > the 32X32 ROM using 32X1 ROM > can anyone help me in understanding the usage of INIT for the ROM > > thanks > > > Regards > Ramakrishna Bachimanchi >Article: 92683
Most PAL's have security bits making copying imposable. That PAL appears to be out of something as the part number doesn't look that familiar so copying might be a tad difficult unless you have the original unsecured original. On the bright side, most PALs are rather simple and can be reverse engineered providing the company no longer exists to beat the c**p out of you. Simon "aptecelectronics" <stu@aptecelectronics-dot-com.no-spam.invalid> wrote in message news:A-mdnX_CwdFKbA3eRVn_vQ@giganews.com... > I have a 16V (PALCE16V8H-15PC/4) that has lost it's program, and need > a new copy made. Can you do it for me? Cost? The part is an HP > 08751-80130, and I have a good one that could be copied from, and I > have a new blank to be copied to. Stu Aplin 310-640-7262 > > > Oil4warwrote: > 16V* is most pupular low cost chip. from 1984, Abel 1.1 and > many DOS > > stuff. If you want, I can burn a CD for you. I block > E-mail in > > this AOL. > > > > hope your E-mail addr. is real one. >Article: 92684
I am still waiting for the Xilinx Spartan 3E demo board.. price is right and it has Ethernet Simon "Raymund Hofmann" <filter002@desinformation.de> wrote in message news:dmplia$p9o$1@online.de... > > I guess it's because of their Problems with the DCM / DFS in stepping 0 > > Raymund Hofmann > > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag > news:dmpfou$5am$03$1@news.t-online.com... > > Hiho > > > > Spartan3E status: > > > > 1) Avnet has sold 400 (maybe a few hundred more) of their 69USD > > XC3S100E based starterkit, now they have 18 in stock if that is sold > > out then leadtime for next order is: 26 weeks ! > > > > 2) All Spartan3e devices have been removed from Avnet online inventory > > search ? > > > > 3) Cesys GmbH can ship from stock 500E based boards > > http://www.cesys.com/index.php?language=en&doc=advanced&docparams=USB3FPGA&menuparams=53 > > > > 4) Xilinx Spartan3e kits are coming... at Christmas? > > > > 5) Spartan3 100e 'sample' pack pictures are online at nuhorizon! > > I assumed that this product/info remains confidential until officially > > launched by Xilinx, well here is at least the pictures > > > > http://www.nuhorizons.com/products/xilinx/spartan3e/samplepack.html > > > > 6) nuhorizon part search on XC3s return page unavailable > > > > Antti > > > >Article: 92685
OK. And have I said anything different? Tell me what I have said wrong? And why can't one core produce both signals, with overflow being meaningless for unsigned numbers?Article: 92686
<juendme@yahoo.com> schrieb im Newsbeitrag news:1133765407.097633.152550@z14g2000cwz.googlegroups.com... > OK. And have I said anything different? Tell me what I have said wrong? > And why can't one core produce both signals, with overflow being > meaningless for unsigned numbers? > yes you said something different. the best thing for you is if you would really understand why - its easy todo, just make a small addsub with coregen and then look in FPGA editor what primitives are used. you shoud be able to understand then why the coregen works as it works. if you want something else you have to handcraft it. AnttiArticle: 92687
>But, I had a strange thought: how many start-ups, consultants, etc. are >there that need prototyping quantities (1 to 3 parts)? > >Does it make sense to have a program for smaller outfits (which are no >less important to Xilinx, as CIS** was small once, too)? > >Is this the real case for web-based product availability? I think there are two issues here. Do you want to encourage the small guys? Do you want them using bleeding edge parts? I think the answers are yes, and no. My view could easily be bogus. If you are asking about a program to get bleeding edge parts out to small companies/consultants, that seems reasonable, but somebody has to do the filtering to make sure they have a reasonable upside, they can tolerate your schedule slips and/or you can supply enough chips if/when they need them. If you just want to make mainstream parts available to small companies (and hackers or hobbyists) then I think the best thing you can do is to make them available through your online store or places like Digikey. I have a perfect application for a small Coolrunner-II. (I want to power the whole thing off the input signal.) Where can I get a few? With this hat, I'm just a hobbyist. Digikey doesn't carry them. Your online store doesn't have the small ones. A while ago they had the non-A small ones and the data sheet available on the same line of the web page said "not recommended for new designs". I'm guessing they pulled the old non-A versions and haven't replaced them with the new -A ones yet. I could probably use a big one. Cost isn't significant for only a few. Shipping in 2-3 weeks is far from great, but I can wait that long. It's just a hack. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 92688
Hi all, Who has ever used the tool of EDK 7.1 "tools->programme flash memory" to fulfill the aim: put my file into the flash and then when the power of the fpga board is on, the file on the flash begin to run. Who has some documents expecially some examples, please help me! Thank you very much. LinaArticle: 92689
OK. Can someone quote the sentence where I was wrong? I would like to learn. I know I can implement overflow myself manually. And I do know how to do it. For those who don't read the whole post, I repeat the sentence from my original post: "Now I have to do it manually, which will most likely be less efficient." Just because I know how to implement something manually doesn't mean it can't be already provided for me. FolIowing the same logic, anyone who knows anything about digital logic knows how to implement the adder/subtracter manually, so why is that core provided? The reason is; because it's more efficient. Xilinx designers can take advantage of internal structure of LUTs/CLBs/routing structure (carry chains),... to produce the most efficient implementation for every FPGA architecture, so that I don't have to study each single architecture, and tweak my design for each one of them. Or am I wrong here? Why do you guys have to play smart, instead of reading my post (with understanding) and answering my questions, which were: 1. Why are both carry and overflow not available in all modes? (Altera provides it for their core, so it is obviously possible) 2. What does the width P=Q+2 mean? And why is the available width (and the availability of overflow) different when only one number is signed, as opposed to both being signed? Questions I did NOT ask: 1. How to implement overflow? (I know that; I can read books and use Google). 2. I also did not complain about "Fairchild TT Applications Handbook", but rather about lack of functionality description in Xilinx documentation. Had Xilinx people done a good job describing the table previously mentioned, i would have had fewer questions.Article: 92690
Actually, there was another question I did ask: What do signals A_SIGNED and B_SIGNED do? How do they affect the functionality of the core? Or is this also explained in some Fairchild handbook?Article: 92691
<juendme@yahoo.com> schrieb im Newsbeitrag news:1133767201.391460.43970@f14g2000cwb.googlegroups.com... > OK. Can someone quote the sentence where I was wrong? I would like to > learn. > I DID READ all your posting. And replayed based on that. if you want to learn, then what I suggested is what you should do, this way I hoped you would learn and understand. ok, if you dont wanna learn yourself then you well this was already given in an another post to you, the addsub uses carry chain and there just is not 'other' pin available. So you get the result and one additional signal - thats it. If anything else is required it can not be implemented by the addsub carry-chain built macro. and as of efficiency of the coregen - it is defenetly possible to make as efficient or better (hard)macros by hand, so if you know what you want just implemenet it in efficient way and forget the coregen. AnttiArticle: 92692
one possible problem is that if the interface type is "memory", oclk need be connected.Article: 92693
Antti Lukats wrote: > <juendme@yahoo.com> schrieb im Newsbeitrag > news:1133767201.391460.43970@f14g2000cwb.googlegroups.com... >> OK. Can someone quote the sentence where I was wrong? I would like to >> learn. >> > > I DID READ all your posting. And replayed based on that. > > if you want to learn, then what I suggested is what you should do, this way > I hoped you would learn and understand. > > ok, if you dont wanna learn yourself then you well this was already given in > an another post to you, the addsub uses carry chain and there just is not > 'other' pin available. So you get the result and one additional signal - > thats it. If anything else is required it can not be implemented by the > addsub carry-chain built macro. > > and as of efficiency of the coregen - it is defenetly possible to make as > efficient or better (hard)macros by hand, so if you know what you want just > implemenet it in efficient way and forget the coregen. > > > Antti > The Quartus tools spot many common hand-coded constructs, and implement them with cores automatically, so that writing your addsub by hand or using the ready-made cores will give the same implementation. Won't Xilinx tools do that too?Article: 92694
"David Brown" <david@westcontrol.removethisbit.com> schrieb im Newsbeitrag news:43942668$1@news.wineasy.se... > Antti Lukats wrote: >> <juendme@yahoo.com> schrieb im Newsbeitrag >> news:1133767201.391460.43970@f14g2000cwb.googlegroups.com... >>> OK. Can someone quote the sentence where I was wrong? I would like to >>> learn. >>> >> >> I DID READ all your posting. And replayed based on that. >> >> if you want to learn, then what I suggested is what you should do, this >> way I hoped you would learn and understand. >> >> ok, if you dont wanna learn yourself then you well this was already given >> in an another post to you, the addsub uses carry chain and there just is >> not 'other' pin available. So you get the result and one additional >> signal - thats it. If anything else is required it can not be implemented >> by the addsub carry-chain built macro. >> >> and as of efficiency of the coregen - it is defenetly possible to make as >> efficient or better (hard)macros by hand, so if you know what you want >> just implemenet it in efficient way and forget the coregen. >> >> >> Antti >> > > The Quartus tools spot many common hand-coded constructs, and implement > them with cores automatically, so that writing your addsub by hand or > using the ready-made cores will give the same implementation. Won't > Xilinx tools do that too? > Sure the Xilinx flow does the same, but... if you write some construct that does add and sub and provides __separate__ outputs for carry and borrow, then how should that be written in order to be recognized for core extraction and what should the coregen actually implement? For 'normal' addsub there are no problems. The OP wants carry and borrow at the same time from the same core primitive ! AnttiArticle: 92695
"Lina" <lnzhao@emails.bjut.edu.cn> schrieb im Newsbeitrag news:ee92962.-1@webx.sUN8CHnE... > Hi all, > > Who has ever used the tool of EDK 7.1 "tools->programme flash memory" to > fulfill the aim: put my file into the flash and then when the power of the > fpga board is on, the file on the flash begin to run. > > Who has some documents expecially some examples, please help me! > > Thank you very much. Lina Hi Lina, first of all Flash has no legs and can not run. The Flash is a non volatile memory that has normally no files on it. It is possible to use Flash as file-system, in that case some areas of the flash may be considered as 'files', in most cased Flash is used simpley as nonvolatile memory (no files, just some binary contents). the EDK ->program flash memory function can copy some prepared image (with any contents) to the flash memory - that is only possible if your hardware is built in proper recognized way. after you program the flash with EDK your SoC system can access the flash as some area in the memory map. if you have properly modified the linker scripts and made your software application capable to start from flash then your program would then start from the flash memory. so download the GNU linker manual and start reading :( Antti PS first time I had to get microblaze to boot from flash it took me 2 weeks. this included custom flash programmer software and time to fix the bug in the EMC IP core that preveneted CFI commands to be executed on byte wide flash memories.Article: 92696
Hi Austin, In article <dmptik$2ck5@xco-news.xilinx.com>, austin@xilinx.com says... > John, > > You bring up an interesting point. > > Yes, the squeaky wheel gets the grease (or in this case, the gorillas > get the bananas). > > But, I had a strange thought: how many start-ups, consultants, etc. are > there that need prototyping quantities (1 to 3 parts)? > > Does it make sense to have a program for smaller outfits (which are no > less important to Xilinx, as CIS** was small once, too)? > > Is this the real case for web-based product availability? First: To your thought: PLENTY OF PEOPLE! And to your question: YES YES YES YES! I work as a consultant (mostly for small companies), and in the past I've worked in small companies/start-up environments. Very frequently the small company is willing to try the bleeding edge or work with the newest parts, since the amount of legacy they have to deal with can be very small. For instance, one company I worked with recently was just getting into FPGAs, so they did not have years of dealing with brand A's, or X. Whatever suggestions or reccomendations I made were acted upon. So when the local office of brand A didn't return my calls about NIOS II, I didn't further consider their options. In the past, if I am unable to get small quantity parts, or not have my phone calls returned for a product inquiry, I'll move on to the next option ASAP. I don't have time to mess around, waiting weeks to talk with the "local rep" only to have tell me nothing useful and not really help to get my parts or information. And if the project initially seems low quantity or if I volunteer that I am a consultant, I never get followed up with (read: I don't look like a design win they can get beau coup dollars for). I am also very sensitive to giving up my e-mail address and phone number just to get in contact with a local rep. I already get enough e-mail spam and phone spam that I don't need to be listed in any more databases. Why am I made to feel like a criminal if I want to get info, let alone samples (assuming I can even get someone on the phone)? So, if I can't get the information I need, or the parts I want with minimal hassle, I will move on to the next options. And for the record, most small companies I know work this way. I'd be curious to hear if anyone else has had these experiences. Henry.Article: 92697
I want to use Chipscope under Linux, but when I try to configure the connection (I have a parallel IV Cable) I get the following messages: COMMAND: open_parallel_cable PROXYTYPE=xilinx_parallel4 FREQUENCY=5000000 PORT=LPT1 MODULENAME=libCse_CommProxyPlugin TYPE=xilinx_plugin INFO: Started ChipScope host (localhost:50001) ERROR: Socket Open Failed. localhost/127.0.0.1:50001 localhost java.net.ConnectException: Connection refused ERROR: Failed to open Xilinx Parallel Cable I use Fedora Core 4. The drivers for the cable work normally (I tested this with iMpact). Help please A+ MehdiArticle: 92698
Well, the intention of my vhdl code is to use floating numbers both positive and negative for multiplication. This is part of my entire neural computation. Seems like real variables are not synthesizable. Intresting to hear that David Bishop has a synthesizable REAL package, do u know where can i get it? Thanks.Article: 92699
Antti Lukats wrote: > "David Brown" <david@westcontrol.removethisbit.com> schrieb im Newsbeitrag > news:43942668$1@news.wineasy.se... >> Antti Lukats wrote: >>> <juendme@yahoo.com> schrieb im Newsbeitrag >>> news:1133767201.391460.43970@f14g2000cwb.googlegroups.com... >>>> OK. Can someone quote the sentence where I was wrong? I would like to >>>> learn. >>>> >>> I DID READ all your posting. And replayed based on that. >>> >>> if you want to learn, then what I suggested is what you should do, this >>> way I hoped you would learn and understand. >>> >>> ok, if you dont wanna learn yourself then you well this was already given >>> in an another post to you, the addsub uses carry chain and there just is >>> not 'other' pin available. So you get the result and one additional >>> signal - thats it. If anything else is required it can not be implemented >>> by the addsub carry-chain built macro. >>> >>> and as of efficiency of the coregen - it is defenetly possible to make as >>> efficient or better (hard)macros by hand, so if you know what you want >>> just implemenet it in efficient way and forget the coregen. >>> >>> >>> Antti >>> >> The Quartus tools spot many common hand-coded constructs, and implement >> them with cores automatically, so that writing your addsub by hand or >> using the ready-made cores will give the same implementation. Won't >> Xilinx tools do that too? >> > > Sure the Xilinx flow does the same, but... > > if you write some construct that does add and sub and provides __separate__ > outputs for carry and borrow, then how should that be written in order to be > recognized for core extraction and what should the coregen actually > implement? > > For 'normal' addsub there are no problems. The OP wants carry and borrow at > the same time from the same core primitive ! > > Antti > My point is that the OP should write the code the way he wants it to run. If the Xilinx tools can implement it using some faster or smaller mechanism than an obvious LUT implementation, then great. If not, then it's likely to be because there is no such better implementation on the particular architecture. But you let the tool do the work, rather than trying to figure out how to force the coregen into making the right construction. That's why we use these tools, rather than drawing out Karnough maps and hand-optimising everything.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z