Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Ray Andraka wrote: >> Question is that >> 1. How can we know wiring resource utilization? >> 2. Can "number of used switch box" out of "total number of switch box" >> be a metric of wiring resource utilization? If yes, are there any >> method to know that? >> >> Thankyou for remark, suggestion. >> > > Why do you need to know the wiring resource utilization? The current > crop of devices have ample wiring resources, and as long as it routes > and meets timing, why does it matter how much is used? Designs use a > very small percentage of the available routing resources. However, the > high density of wiring is present in order to increase the likelihood of > a route solution that meets timing. The actual routing resources used > wil depend heavily on the place and route solution, which can change > considerably with very small changes in the design. Because of these > facts, the routing resource utilization has little value to the user of > the devices. This is generally true... as long as device utilisation is well under 100%. I had a job with a small research group some years ago where we had one person working full-time on analyzing timing reports and write routing constraints. IIRC, the devices in questions were Virtex 4000 (two per board) and our FAE said we would never be able to route and even less meet timings beyond about 85% logic utilisation... but in the end, we managed to get nearly 95% with over 2k hand-written routing/placement constraints and 10+ hours synthesis run-time a pop. Many of the older FPGAs are not 100% routable even for nearly trivial logic. Newer devices are said to be "100% routable" but once timing is taken into account there probably is no device that can achieve 100% non-trivial logic utilisation. Given how synthesis times explode once device utilisation exceeds 70%, exceeding 90% today is still generally not recommended. As you said though, knowing how much of the routing fabric is used is of little use. What IS really important is knowing HOW it is (mis-)used - that's what the full-time constraints guy was doing. I suppose routing utilisation could still be interesting to have in the "stats that are nice to know about but have little to no relevance" category. -- Daniel Sauvageau moc.xortam@egavuasd Matrox Graphics Inc. 1155 St-Regis, Dorval, Qc, Canada 514-822-6000Article: 108026
Luhan wrote: > > The famous N.E.D. (noise emitting diode) - goes bang just one time! > > Luhan ;) > Or as my wife called it once when I hooked up a small diode backwards the "temporarily light emitting diode" the TLED I guess.Article: 108027
Kolja Sulimma wrote: > Weng Tianxiang schrieb: > > > ERROR:NgdBuild:604 - logical block > > 'MG_x_A3/bram64_8_A/BU5' with type 'RAMB16' could not > > be resolved. A pin name misspelling can cause this, > > a missing edif or ngc file, or the misspelling of a type name. > > Symbol 'RAMB16' is not supported in target 'virtex2'. > > > > I couldn't find any 'RAMB16' in my vhdl files. > > No, not in your VHDL. > But the RAM block that you generated uses it internally. > > You will not get any VHDL code for the internals of the generated core. > Just a netlist (edif or ngc) and a simulation model. > > Kolja Sulimma Hi Kolja, Thank you very much for your help. The problem seems resolved. Now it is compiling and everything works well. The free download WebPack is at fault. What I have done to correct the errors are as follows: 1. Re-download the latest WebPack version with their service pack; 2. Re-generate all Block RAM modules; 3. It fails with Virtex 2 chips; 4. It suceeds with Virtex 4 chips, what I have used is: 4vlx25sf363-12. The block RAM generated code can be used with the above chip. That is all I have done. If it had been a paid version of Xilinx ISE, the above errors would have never happend before. Thank you. WengArticle: 108028
PeteS wrote: > Re: Please help me with (insert task here) Even worse is when they DON'T include the task in the subject. Eg. "Need help, URGENT!!!" MarkArticle: 108029
Mark P wrote: > Weng Tianxiang wrote: > > Hi, > > I want to buy some books on algoirthms in graph. > > > > Of the following 5 books, which one is best on descriptions algorithms > > in graph: > > > > [...] > > I don't know any of the books but perhaps you could be more specific > about what you want to know about graph algorithms. If it's only basic > algorithms (shortest path, min. spanning tree, network flows, etc.) then > there are many general algorithm texts that would cover these. For more > specialized applications we need to know more about your intentions. Hi Mark, I am a hardware FPGA designer. What I want to do is to try to design a new hardware circuit to tackle the most difficult and very famous algorithms in graph. 1. The algorithms in graph are very commonly used; 2. The algorithms computing complexity is high, for example, O(N**m), m >= 2; I would like to learn the algorithms, then try to find a hardware solution for them. I found the maximum matching problem for bipartite in graph is an interesting problem: it has computing complexity of O(N**2.5) and very famous. I am doing research on it now. I would like to find more similar situations like the maximum matching problem in graphs. Thank you. WengArticle: 108030
axalay@gmail.com wrote: > Synthesise PCI ver.3.160 for XC2VP7-6FG458 in Coregen (ISE 8.2 SP 2). > When run compile, ISE genegate ERROR: > > Using target part "2vp7fg456-6". > Mapping design into LUTs... > ERROR:LIT:163 - Virtex PCILOGIC macro PCILOGIC symbol > "PCI_CORE/PCI_LC/OUT_CE/MAGICBOX" (output > signal=PCI_CORE/PCI_LC/OUT_CE/HARD_CE) is an invalid component in > Virtex2 > architecture. > Errors found during logical drc. > > How to solve this problem? And why it appears? > > Thanks, Vasiliy Zamyatin Your PCI cfg file has one bit that needs the be enabled to force the "SOFT_CE" rather than the "HARD_CE" generated by the (absent) PCILOGIC block. http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10979 or http://tinyurl.com/zrj9z As for "full license" I thought no source code *was* available for the PCI core. There's a wrapper that instantiates some of the top-level I/O and registers but the core (.ngo) is still needed since the simulation model probably won't synthesize well (I never tried).Article: 108031
Martin Thompson wrote: > Don Seglio <cbayona@cox.net> writes: > >> I bought a Spartan-3 kit about a year ago and it came with V7.1i of >> the software, I'm wondering what the kits are shipping with now? >> >> >> On a related subject I bought a copy of MatLab for use with the Xilinx >> software in creating DSP functions. I bought R14 which is compatible >> with the software I now have, but they ran out of the old copies and >> gave me a copy of the 2006a release instead, anyone have a clue if >> that will work also? > > I don't think that Matlab 2006 will work with V7.1 of Xilinx. I use > V7.1 of ISE with version 7.0.4 of Matlab. > > According to here: > http://www.xilinx.com/products/software/sysgen/sw_req.htm > MATLAB v7.1.0/Simulink v6.3 R14.3 Service Pack 3 > MATLAB v7.2/Simulink v6.4 R2006a > works with System generator 8.2 > > I assume it is Sysgen that you want to use? > > Also, note that Sysgen is not included with the S3 kit, it's a > separate purchase, so you might be better using 8.2 of everything > Xilinx, in which case it appears that your 2006a of Matlab will be > OK.... > > Or you can download an older version of Matlab from The Mathworks I > imagine... > > Does that help any? > > Cheers, > Martin > I have a funny suspicion that I was sent the wrong Xilinx software with my unit, It's been a year since I bought it and the CPU core generator and DSP software is still functional. But I don't have the proper version of MatLab. At least the DSP software does not complain when I fire it up, the core software is still functional, it let's me generate cores still with no limits as to what to generate. but all this software came with 7.1i which is rather old. Maybe I should be happy and quit worrying about upgrading. I've been offered a refund if my package of MatLab stays sealed that why I'm asking, if I open it to try it out I'm stuck with it. -- Cecil KD5NWA www.qrpradio.com www.hpsdr.com "Sacred Cows make the best Hamburger!" Don Seglio BatunaArticle: 108032
John_H wrote: > > As for "full license" I thought no source code *was* available for the > PCI core. There's a wrapper that instantiates some of the top-level I/O > and registers but the core (.ngo) is still needed since the simulation > model probably won't synthesize well (I never tried). I've always found those caveats somewhat amusing. Does Xilinx write one piece of code to generate the PCI core, and then another piece of code for the simulation model? How do they make sure the simulation code matches the synthesis version? Somehow I doubt there are two separate pieces of code ;)Article: 108033
Torsten Alt <talt@kip.uni-heidelberg.de> wrote: >Hello, > >i'm designing a onchip bus on a Virtex4 FPGA with one master and several >slave modules located in different asynchronous clock domains. The bus >consists of address, data and control signals. For synchronization i'm >using a full hanshake with a "Request" and "Acknowledge" signals. Now >it would be interessting to know if it's enough to synchronize only the > handshake signals as long as i make sure that the other bus signals >are stable for a certain amount of time or if i have to synchronize the >address and control signals as well. To illustrate the problem lets >assume the following situation: Synchronizing the handshake signals is enough. However, you may run into trouble with the constraints in the address and data signals. This may overconstrain your design and eat away more fast routing resources than necessary. You could design a high speed to low speed bridge module which also seperates the high speed and low speed modules. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 108034
"Boudewijn Dijkstra" <boudewijn@indes.com> wrote in message news:op.tfcf4mtly6p7a2@ragnarok.lan... > For people with the aforementioned skill level, that wouldn't matter > much. It will probably say "poof!" and start to smell. Noobs who can > learn from this experience, gradually build the skill to make the diode do > absolutely nothing at all. Reminds me of the electrician test. You give the new guy a 5 tube ACDC radio and a power plug to connect to it. If he does it right and the radio runs he becomes an electrician. If he blows a fuse he becomes a radio repairman. If he takes the power out in a city block he becomes an electrical engineer.Article: 108035
fl wrote: > Hi, > I am new to VHDL. I write the following simple counter program in ISE > webpack 8.2. Both two can be behavior simulated. But, the simulation of > the second (without Reset control) is not correct after synthesis. This > example is just an exercise to me. What I care is: Is there other > pitfalls I have to know in order to avoid it cannot synthesis? > > > Thank you very much. > > > -- First > architecture Behavioral1 of smallComp is > --signal clk: clk in std_logic; > signal count : INTEGER range 0 to 15; > begin > cp1: process (clk, RESET) > begin > if RESET='1' then > count <= 0; > elsif (clk='1' and clk'event) then > if count >= 15 then > count <= 0; > else > count <= count + 2; > end if; > end if; > end process; > cnt <= CONV_STD_LOGIC_VECTOR(count,4); > end Behavioral1; > > > > --Second > architecture Behavioral2 of smallComp is > --signal clk: clk in std_logic; > signal count : INTEGER range 0 to 15; > begin > cp2: process (clk) > begin > if (clk='1' and clk'event) then > if count >= 15 then > count <= 0; > else > count <= count + 2; > end if; > end if; > end process; > cnt <= CONV_STD_LOGIC_VECTOR(count,4); > end Behavioral2; > Hei, i checked your design with the ISE 8.2 and simulated both versions. I did not get any undefined values but with a post-synthesis simulation you should not get an undefined value since the flip-flops are all initialized. This one can see in the netlist created by netgen. If you see an X then it could be a timing problem since. Also KJ was right that you'll run into error during simulation if you try to compile the design directly in Modelsim or another simulator. Your design will never reach the 15 and 16 is out of range. The post-synthesis model works cause the synthesizer is smart enough to limit your counter to 4 bit (3 bit since the last bit is stuck to 0) and what happens is that you'll get a wrap-around. So 16 will be "10000" and since your counter has only 4 bit you'll get a "0000". This result you can also see in the RTL viewer of the ISE software. There are a few pitfalls in doing VHDL design and one is not to initialize counters or FSMs. So there should always be a reset. Some devices have the ability to "wake-up" with a default value which can normally be specified by generics or attributes. This you'll have to look up in the documentation of the target device. Another thing is that i would try to avoid to compare values with "greater " or "lower" than a value. This can increase your logic since the synthesizer has to synthesize all this cases. In your case i would just compare my value to "14" and then do the wrap-around. There is no need to compare values larger than 14 since the result of the counter should always be well defined. If you'll get a number greater than 14 than something in your design is very fishy... Good luck! TorstenArticle: 108036
Homer J Simpson wrote: > "Boudewijn Dijkstra" <boudewijn@indes.com> wrote in message > news:op.tfcf4mtly6p7a2@ragnarok.lan... > > >>For people with the aforementioned skill level, that wouldn't matter >>much. It will probably say "poof!" and start to smell. Noobs who can >>learn from this experience, gradually build the skill to make the diode do >>absolutely nothing at all. > > > Reminds me of the electrician test. You give the new guy a 5 tube ACDC radio > and a power plug to connect to it. > > If he does it right and the radio runs he becomes an electrician. > > If he blows a fuse he becomes a radio repairman. > > If he takes the power out in a city block he becomes an electrical engineer. > > > If (s)he takes the radio to pieces and never gets around to putting the plug on, but holds the wires in the socket with a couple of matchsticks, (s)he becomes an engineering academic... ;) -- SueArticle: 108037
"Duane Clark" <junkmail@junkmail.com> schrieb im Newsbeitrag news:YlYKg.5530$tU.5133@newssvr21.news.prodigy.com... > John_H wrote: >> >> As for "full license" I thought no source code *was* available for the >> PCI core. There's a wrapper that instantiates some of the top-level I/O >> and registers but the core (.ngo) is still needed since the simulation >> model probably won't synthesize well (I never tried). > > I've always found those caveats somewhat amusing. Does Xilinx write one > piece of code to generate the PCI core, and then another piece of code for > the simulation model? How do they make sure the simulation code matches > the synthesis version? Somehow I doubt there are two separate pieces of > code ;) actually i think there are, the simulation code is generated from edif with special non synthesis primitives. AnttiArticle: 108038
"Antti Lukats" <antti@openchip.org> wrote in message news:edf7iq$o6d$1@online.de... > > Now if you want to wire some GPIO pins from the EDK into ISE toplevel and > not to IOBs you may need to look into the EDK toplevel wrapper (usually > system.vhd) you may need to remove the IOB prim instances there in order to > connect them succesfully in the ISE toplevel. You don't need to remove anything. Simply instantiate system instead of system_stub in your top level. /MikhailArticle: 108039
"Palindr?me" <me9@privacy.net> wrote in message news:12fooallooa1523@corp.supernews.com... > If (s)he takes the radio to pieces and never gets around to putting the > plug on, but holds the wires in the socket with a couple of matchsticks, > (s)he becomes an engineering academic... That was my favorite technique - on 240 VAC!Article: 108040
Dennis wrote: > Luhan wrote: > >> >> The famous N.E.D. (noise emitting diode) - goes bang just one time! >> >> Luhan ;) >> > Or as my wife called it once when I hooked up a small diode backwards > the "temporarily light emitting diode" the TLED I guess. VSC = Voltage to Smoke Converter -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108041
"MM" <mbmsv@yahoo.com> schrieb im Newsbeitrag news:4m377bF49q27U1@individual.net... > "Antti Lukats" <antti@openchip.org> wrote in message > news:edf7iq$o6d$1@online.de... >> >> Now if you want to wire some GPIO pins from the EDK into ISE toplevel and >> not to IOBs you may need to look into the EDK toplevel wrapper (usually >> system.vhd) you may need to remove the IOB prim instances there in order > to >> connect them succesfully in the ISE toplevel. > > You don't need to remove anything. Simply instantiate system instead of > system_stub in your top level. > > /Mikhail > well in that case you need to duplicate the IOB primitives, so its hand-work so or so AnttiArticle: 108042
In article <op.tfcf4mtly6p7a2@ragnarok.lan>, "Boudewijn Dijkstra" <boudewijn@indes.com> wrote: > Op Mon, 04 Sep 2006 06:15:02 +0200 schreef Michael A. Terrell > <mike.terrell@earthlink.net>: > > Luhan wrote: > >> Jonathan Bromley wrote: > >> > On 3 Sep 2006 13:41:01 -0700, "PeteS" <PeterSmith1954@googlemail.com> > >> > wrote: > >> > >Bob Ferapples wrote: > >> > >To save time and bandwidth, I have boiled down the vast majority of > >> > >postings to this newsgroup into a quick and dirty little format that > >> > >can speed things up. > >> > >> I get irritated by those who post serious replies when the very content > >> of the question shows that the person has not a clue. "Hi, I need to > >> design a control system for a nuclear reactor. Can someone tell me > >> what a diode does?" > >> > >> Aaaarrrrggg! > >> > >> Luhan > > > > > > It depends on which way you hook it up. ;-) > > For people with the aforementioned skill level, that wouldn't matter > much. It will probably say "poof!" and start to smell. Noobs who can > learn from this experience, gradually build the skill to make the diode do > absolutely nothing at all. Ahhhh, the zen of mastery... How does one know when one has become a master? When the diode does nothing. -- Don Bruder - dakidd@sonic.net - If your "From:" address isn't on my whitelist, or the subject of the message doesn't contain the exact text "PopperAndShadow" somewhere, any message sent to this address will go in the garbage without my ever knowing it arrived. Sorry... <http://www.sonic.net/~dakidd> for more infoArticle: 108043
On 4 Sep 2006 20:07:18 +0200, the renowned David Ashley <dash@nowhere.net.dont.email.me> wrote: >Dennis wrote: >> Luhan wrote: >> >>> >>> The famous N.E.D. (noise emitting diode) - goes bang just one time! >>> >>> Luhan ;) >>> >> Or as my wife called it once when I hooked up a small diode backwards >> the "temporarily light emitting diode" the TLED I guess. > >VSC = Voltage to Smoke Converter > >-Dave A heating coil stuck in some spices from the spice cupboard. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 108044
On 2006-08-27 20:33:55 -0700, "Nevo" <nevo_n@hotmail.com> said: > Hm... I found http://direct.xilinx.com/bvdocs/appnotes/xapp179.pdf, > which lists the 5V tolerant SelectIO standards for the Spartan 2 family > (and implicitly says none of the standards are 5V tolerant in the > Spartan 2E family), but I'm unable to find a simlar reference for the > Spartan 3 family. Hmm indeed. I'm glad you mentioned this, because I'd assumed the 2E and the 2 had the same 5v-tolerance characteristics... Having read ds077.pdf (Spartan-2E) as *well* as ds001.pdf (Spartan-2), I now realise my error... Looks like I'll be using a -2 rather than a -2E for my interface-to-ancient-bus-logic :-) Cheers, SimonArticle: 108045
Hello Michael, >>The other things he told us probably dates back to the 18th century: "As >>civilians you came, as men you will leave" and "Anything that doesn't >>immediately lead to your death will make you tougher". >> > And your DI wants you to believe that they know every trick in the > book. ;-) > But the older ones do know a lot of tricks that aren't in the book. Like never to wear freshly washed socks when 15 miles of hiking in full gear was required. Gets you blisters in no time. They told us to wear the socks from yesterday plus some thinner ones over them. It worked. No blisters anymore. -- Regards, Joerg http://www.analogconsultants.comArticle: 108046
Hi Yifei Ray and Dave have already mentioned some apps. Alternatively, If you want coeffs and VHDL for your filter, try Tyd-IP Code Generator. Bob Yifei Luo wrote: > I am a newer of System Generator. I designed an FIR with system generator, > only using the Delay, Cmult, Addsub, upsampler, downsampler and Gateway > In/Out block. Then I made it into a subsystem and masked it. > > Question are : > Do I need to set the filter coefficient? > What does filter coefficient stands for? > And what value should I give to the coefficient? > > Thank you very much for your kindly help!Article: 108047
Homer J Simpson wrote: > Reminds me of the electrician test. You give the new guy a 5 tube ACDC radio > and a power plug to connect to it. (snip) > If he takes the power out in a city block he becomes an electrical engineer. If this happens, the D.O.D. whisks him or her away in the dead of night.Article: 108048
Luhan wrote: > > The famous N.E.D. (noise emitting diode) - goes bang just one time! Install a 1N34 across a light switch with the power off an d the switch is on. Turn the power back on and wait for someone to shut it off. Then there is a loud bang, but the light still works when they turn it back on. I used to have 5000 spares. ;-) -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 108049
Palindr?me wrote:
>
> If (s)he takes the radio to pieces and never gets around to putting the
> plug on, but holds the wires in the socket with a couple of matchsticks,
> (s)he becomes an engineering academic...
Then what do you call an eight year old who takes a box of loose
parts and builds a radio?
--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.
Michael A. Terrell
Central Florida
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z