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Symon wrote: > Martin, > You can only use certain I/O standards with specific Vccos. If you want to > change voltage, you must change both the I/O standard and Vcco. Read the > manual about the I/O banking rules. > HTH, Syms. To expand a little, if you have an output buffer powered by 2.5 volts, how do you expect the FPGA to get up to 3.3V?Article: 108701
Thanks Peter. My only problem is that I can reset (hold down the reset button!) the whole thing and STILL get a 300 MHz clock on the output. Asserting reset should reset the DCM that bumps the 100 MHz to 300 MHz. Actually, in reset, there should be no clocks in the FPGA except for the input 100 MHz clock from the XO. According to DCM documentation, the reset will force all outputs to 0. I have traced the rest signal to the DCm in the technology schematic, the floorplanner, and the FPGA editor to cover all bases. It is connected properly. thanks again!Article: 108702
Ed Coombs wrote: > rickman wrote: > > Ben Jackson wrote: > >> On 2006-09-11, David Ashley <dash@nowhere.net.dont.email.me> wrote: > >>> I want to create a 1152 by 6 bit rom and I want to use > >>> a bram. It can be clocked or not clocked, but I'd prefer > >>> not clocked. Can someone point me to a template? > >> There's a whole PDF of them called "xst.pdf" which you can google. > > > > I was not aware of this document. It looks very useful, but it seems > > to be a bit out of date. It does not mention a number of newer > > families including Spartan 3. I guess the information applies as > > appropriate depending on the feature. > > > > Will Xilinx be updating this document anytime soon? > > > > I was also suprised at the number and ages of this file on the web. Then I > looked in my webpack install, here: > > .../Xilinx/doc/usenglish/books/docs/xst/xst.pdf > > This one is much newer, and bigger. Yes, many of the sources for different versions are found on the Xilinx web site. A google search turned up several and I figured out this link which is likely to be the latest, with a (likely incorrect) copyright date of 2005. http://toolbox.xilinx.com/docsan/xilinx8/books/docs/xst/xst.pdfArticle: 108703
Use an other FET as FDV301 ... in sot23 too ! The Vgs of this one is much better than your one. Laurent http://www.amontec.com John Larkin wrote: > I've got some DACs that I'd like to switch gain ranges on, and it > turns out I can do it nicely using a single 2N7002 (sot23 n-channel > mosfet) to switch a resistor to ground in each reference circuit. So > I'd like to turn each 7002 on and off from a pin on an XC3S400. But > 3.3 volts is a marginal high for this fet... 4 volts looks safe. > > So, how about running Vccio a bit high, 3.5 maybe, and adding an > external pullup resistor to +5. If I tristate the pin, I should > forward-bias the upper esd diode and get 4.2 roughly, right? I'm > thinking maybe a half milliampere or so pullup current. Doing this 8 > times only dumps 4 mA into the Vccio rail, no hazard there. > > I could use a lower-threshold fet, I guess, but the 7002's are in > stock and cost 3 cents each. > > John > > >Article: 108704
hi i have a problem getting the lwip to work. my c code is pretty
simple:
#include "xmk.h"
#include "stdio.h"
#include "lwip/api.h"
#include "xparameters.h"
int main()
{
xil_printf("Entering main \r\n");
xilkernel_main();
return 0;
}
void* system_setup(void* arg)
{
xil_printf("Initializing lwIP .");
lwip_init();
xil_printf(" done. \n");
return 0;
}
the mms file is:
BEGIN OS
PARAMETER OS_NAME = xilkernel
PARAMETER OS_VER = 3.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER sysintc_spec = opb_intc_0
PARAMETER stdout = RS232_DCE
PARAMETER stdin = RS232_DCE
PARAMETER config_debug_support = true
PARAMETER debug_mon = true
PARAMETER verbose = true
PARAMETER config_sema = true
PARAMETER config_msgq = true
PARAMETER msgq_capacity = 2
PARAMETER sched_type = SCHED_PRIO
PARAMETER systmr_interval = 5
PARAMETER systmr_freq = 50000000
PARAMETER systmr_dev = opb_timer_1
PARAMETER use_xil_malloc = true
PARAMETER static_pthread_table = ((system_setup,1))
END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = lwip
PARAMETER LIBRARY_VER = 2.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER api_mode = SOCKETS_API
PARAMETER lwip_debug = true
PARAMETER emaclite_instances =
((Ethernet_MAC,0x01,0x02,0x03,0x04,0x05))
END
As linker options i use : -lxilkernel -llwip4
when i build the projet i get the following error message:
Building target: ethernet.elf
mb-gcc -o ethernet.elf main.o
-LC:/CodeGeeks/test_edk3/microblaze_0/lib -Wl,-T
-Wl,"C:\CodeGeeks\test_edk3\TestApp_Memory\src\TestApp_Memory_LinkScr.ld"
-lxilkernel -llwip4
C:/CodeGeeks/test_edk3/microblaze_0/lib/liblwip4.a(sys_arch.o): In
function `sys_arch_sem_wait':
/cygdrive/c/CodeGeeks/test_edk3/microblaze_0/libsrc/lwip_v2_00_a/src/contrib/ports/v2pro/sys_arch.c(.text+0x148):
undefined reference to `sem_timedwait'
C:/CodeGeeks/test_edk3/microblaze_0/lib/liblwip4.a(sys_arch.o): In
function `sys_arch_mbox_fetch':
/cygdrive/c/CodeGeeks/test_edk3/microblaze_0/libsrc/lwip_v2_00_a/src/contrib/ports/v2pro/sys_arch.c(.text+0x594):
undefined reference to `sem_timedwait'
collect2: ld returned 1 exit status
make: *** [ethernet.elf] Error 1
Build complete for project ethernet
Could somebody help me here please?
thanks
Urban
Article: 108705Hi guys, Now my recursive mutex stopped to work. I guess I will have to patch the patch? :-) Yuri Vasanth Asokan wrote: > Yuri, > > The patch is against the file Andreas referred to in his previous posts. To > avoid touching the EDK installation area, you should ideally create and use > a local copy of the kernel. Here are the steps, > > 1. Copy <edk_install>/sw/lib/bsp/xilkernel_v3_00_a into <your edk > project>/bsp/xilkernel_v3_00_a. This becomes your local copy of the kernel. > 2. In an EDK bash shell, cd to <your edk project>/bsp/xilkernel_v3_00_a > 3. Run, "patch -p0 < mutex.c.patch" > 4. Regenerate libraries from within XPS > > Step 3 assumes you have "patch" utility installed. If you don't, you can > make the change referred to in the patch file yourself. It is just a one > word change in xilkernel_v3_00_a/src/src/ipc/mutex.c. > > Vasanth > "Yuri" <shteinman@squarepeg.ca> wrote in message > news:1158179842.784063.280080@p79g2000cwp.googlegroups.com... > > Vasanth, > > Can you please tell how do I apply this patch in Windows environment? > > > > Thank you, > > Yuri Shteinman > > > > Vasanth Asokan wrote: > >> Andreas, > >> > >> It is indeed a bug. Thanks for taking the time to track this. I have > >> attached a naive fix (which will not avoid starvation). > >> The fix should appear in EDK 9.1i. > >> > >> thanks, > >> Vasanth > >> > >Article: 108706
False Rumor, We still require signal integrity to be correct, and have no plans to try to deal with bad engineering. Austin John Larkin wrote: > On 13 Sep 2006 17:25:18 -0700, Ben.Nader@gmail.com wrote: > >> Hi >> >> I am trying to programm a XC2S300E through a microcontroller using the >> Slave p mode. >> I make a ufp file ( which is just a hex file) of my program using >> xilinx ISE 8.1 and then using the microcontroller and and slave mode >> signals I send it to the fpga. >> I have all this working for another design, which is exactly the same >> micro but Xc2S150E FPGA. but I can not get this to work on XC2S300E. >> >> here is what happens: >> >> 1. I pulsed the ~prog line low and then high. ( to start the clearing >> configuration memory) >> 2. I see FPGA lowers INIT line ( it shows it is busy clearning the >> memory) >> 3. INIT goes high >> 4. I am sending Clock along with 8bit data on D[7:0] and CCLK. >> 5. I see INIT stays high ( so I thought CRC check was okay) >> 6. DONE stays low, I never see it coming up. >> >> after extensive search on the Xilinx website I read something that I >> could have a timing problem and I should keep sending CCLK till DONE >> goes high. so I tried just running CCLK for like a full SECOND after I >> was done sending my real data, and I still never saw DONE going high. >> >> I purposly changed my hex file to see if I the CRC error happens and >> INIT goes low. but I never saw this. INIT was high the entire time >> after the initial memory clearning process( FPGA pulled it low then) >> so this means I am not as far as CRC test on the flow chart. I am >> wondering If FPGA thinks that it is not at the end of the file yet or >> if it is reading anything at all. >> I also checked the number of bits on hex file and it matches the number >> on the Xilinx Datasheet. so I know I build the correct hex file. >> >> I have 3 different boards with XC2S300E that I have this problem with. >> so I doubt I have a connectivity issue or anything like that. >> >> I also double checked my pull up and downs like 100 times by now. they >> all makes sense and match my board with XC2S150E( which I can configure >> with no problem) >> >> Do you guys have any ideas where the problem coming from?.. what other >> things I should look at? >> >> I appreciate you taking the time and reading my long email and helping >> me >> >> Ben > > Check for ringing on the CCLK signal at the fpga... that has nailed us > a couple of times. Try adding 33 pF to ground, just to see if that's > the problem. Sometimes just probing CCLK at the chip will allow a > config to complete. > > Rumor has it that some future Xilinx parts will add schmitt triggers > to CCLK and maybe some other config pins. Lately, we're adding > TinyLogic schmitt buffers right at the pin, unless the trace is *very* > short. > > CCLK signal integrity requirements are right up there with all the > other clocks on the board. > > John >Article: 108707
Mike, Heavens No! The S3 family is very alive, and doing very well. Now that the Spartan Business Group is well into providing a large part of the consumer electronics programmable logic, and because of their previous business models, and their original customers, they plan on having a longer product life than the Virtex group. Spartan still has its original family member, based on the 4KXLA device family, as well as a 5V 4K device! Still shipping. Even with the new Spartan 3E, and perhaps more new Spartan parts, there is no plan to stop selling what is probably the most successful FPGA out there (>>10 million shipped, and still shipping strong). Xilinx in general obsoletes very few products. The 2000 family was available for 20 years. The 3000 family is still available (some family members). Selected members of the 4, 4E, 4X, 4XL, 4XLA families are discontinued, but not all. 4XV was completely discontinued, as Virtex was a better solution, and cost less (so 4XV never 'took off' anyway). Virtex, Virtex E, Virtex II, Virtex II Pro, Virtex II Pro-X, Virtex 4 are all doing very well, and we have no plans to obsolete any of them. Old version of software are archived so that people with old parts may continue to support those products. Of course, we recommend only those parts for new designs which are prominently displayed on the documentation web pages, and those that are not recommended are also so indicated. AustinArticle: 108708
Have a look at out TechiTip http://www.enterpoint.co.uk/techitips/Previous_TechiTips/5p_charge_pump.html for a charge pump style solution that does not cost much. We did this bus switch (FET) gate driving. John Adair Enterpoint Ltd. - Home of Tarfessock1. The Spartan-3E Cardbus Development Board. http://www.enterpoint.co.uk "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:fhojg2l323ts6bvpqompi3flcj5fcphlbv@4ax.com... > I've got some DACs that I'd like to switch gain ranges on, and it > turns out I can do it nicely using a single 2N7002 (sot23 n-channel > mosfet) to switch a resistor to ground in each reference circuit. So > I'd like to turn each 7002 on and off from a pin on an XC3S400. But > 3.3 volts is a marginal high for this fet... 4 volts looks safe. > > So, how about running Vccio a bit high, 3.5 maybe, and adding an > external pullup resistor to +5. If I tristate the pin, I should > forward-bias the upper esd diode and get 4.2 roughly, right? I'm > thinking maybe a half milliampere or so pullup current. Doing this 8 > times only dumps 4 mA into the Vccio rail, no hazard there. > > I could use a lower-threshold fet, I guess, but the 7002's are in > stock and cost 3 cents each. > > John > > >Article: 108709
Joseph, I was worried that FPGA_Editor was also not in webpack, but, the worry was unfounded. My only other comment on your post, is that remember that FPGA_Editor is a software fictional view of the hardware. For example, there are no "switch-boxes" in the actual hardware, and there are no "pips". It is just a convenient fantasy so you can visualize what the design is doing. If you saw the real hardware, you would be lost in it, while trying to use it. That is what software is for. AustinArticle: 108710
So, having bought the V4FX-12 kit from NuHorizons, it arrived with a parallel-port JTAG cable. Normally I'd be just *fine* with this, but today my new quad-xeon Mac-pro arrives, and I bought that specifically to get some oomph in P&R (running linux using "parallels", of course). The mac doesn't have a parallel port. Ahhh. Is there a USB programming cable suitable for the FX-12 ? A fallback plan is to do most of the work on the Mac, but have a mini-itx machine next to it just for programming - the itx machine *does* have a // port, but it's woefully underpowered for any serious work on it... Ideas gratefully received :-) SimonArticle: 108711
Antti wrote: > Eli Hughes schrieb: > > >>Does anyone know if ANY of the Actel fusion devices are available for >>purchase? >> >>-Eli > > > I received some PQ208 fusion chips over 6 weeks ago already. > so I assume the answer is yes. > > Antti > Where did you order? I just called avnet and they said 6-month lead time. You want to sell any of yours?? -EliArticle: 108712
John Larkin wrote: > I've got some DACs that I'd like to switch gain ranges on, and it > turns out I can do it nicely using a single 2N7002 (sot23 n-channel > mosfet) to switch a resistor to ground in each reference circuit. So > I'd like to turn each 7002 on and off from a pin on an XC3S400. But > 3.3 volts is a marginal high for this fet... 4 volts looks safe. > > So, how about running Vccio a bit high, 3.5 maybe, and adding an > external pullup resistor to +5. If I tristate the pin, I should > forward-bias the upper esd diode and get 4.2 roughly, right? I'm > thinking maybe a half milliampere or so pullup current. Doing this 8 > times only dumps 4 mA into the Vccio rail, no hazard there. > > I could use a lower-threshold fet, I guess, but the 7002's are in > stock and cost 3 cents each. Does a FET work better in this app than a bipolar would? I guess it is better to have a resistance (FET) in the path than a low constant voltage (saturated NPN). Personally, I would find a FET with a lower Vgsth. They are not hard to find. I seem to recall the only thing you give up is a higher Vdss rating.Article: 108713
I've been using the Xilinx Platform Cable USB for some time. They now have a second generation out there with lower power *and* is lead free. I only wish I could have multiple USBs connected at once since my Xilinx Spartan3E starter kit board has a "built-in" platform USB cable that just needs a standard USB cable to connect to my system. So nice. "Simon" <news@gornall.net> wrote in message news:2006091508283364440-news@gornallnet... > So, having bought the V4FX-12 kit from NuHorizons, it arrived with a > parallel-port JTAG cable. Normally I'd be just *fine* with this, but today > my new quad-xeon Mac-pro arrives, and I bought that specifically to get > some oomph in P&R (running linux using "parallels", of course). > > The mac doesn't have a parallel port. Ahhh. Is there a USB programming > cable suitable for the FX-12 ? A fallback plan is to do most of the work > on the Mac, but have a mini-itx machine next to it just for programming - > the itx machine *does* have a // port, but it's woefully underpowered for > any serious work on it... > > Ideas gratefully received :-) > > Simon >Article: 108714
u_stadler@yahoo.de wrote: > As linker options i use : -lxilkernel -llwip4 > > when i build the projet i get the following error message: > > Building target: ethernet.elf > mb-gcc -o ethernet.elf main.o > -LC:/CodeGeeks/test_edk3/microblaze_0/lib -Wl,-T > -Wl,"C:\CodeGeeks\test_edk3\TestApp_Memory\src\TestApp_Memory_LinkScr.ld" > -lxilkernel -llwip4 > C:/CodeGeeks/test_edk3/microblaze_0/lib/liblwip4.a(sys_arch.o): In > function `sys_arch_sem_wait': > /cygdrive/c/CodeGeeks/test_edk3/microblaze_0/libsrc/lwip_v2_00_a/src/contrib/ports/v2pro/sys_arch.c(.text+0x148): > undefined reference to `sem_timedwait' > C:/CodeGeeks/test_edk3/microblaze_0/lib/liblwip4.a(sys_arch.o): In > function `sys_arch_mbox_fetch': > /cygdrive/c/CodeGeeks/test_edk3/microblaze_0/libsrc/lwip_v2_00_a/src/contrib/ports/v2pro/sys_arch.c(.text+0x594): > undefined reference to `sem_timedwait' > collect2: ld returned 1 exit status > make: *** [ethernet.elf] Error 1 > Build complete for project ethernet Have you tried changing the order of -l libraries (since lwip4 calls xilkernel functions)? -llwip4 -lxilkernel Alan NishiokaArticle: 108715
I am writing a firmware application that allows the verilog hardware on the stratix 2 board to communicate via rs232 to a C# application. I would like to add the functionality into the C# app to upgrade the firmware on the board, as new functions become available. I'd like to be able to send a flash file from PC to the board, store it to flash and have the new version load on reset. ANY INFORMATION is GOOD INFORMATION JeffArticle: 108716
just tried that. no doesn't work.Article: 108717
Austin Lesea wrote: > I was recently asked to do a course, which involves actually showing > folks real hardware, with real software. > > So, like a good teacher, I went and personally purchased the Digilent > pcb (this is not for work!), the USB programming cable, and went at it. > > I also downloaded 8.2 webpack, and the service pack. ... > Find the zipped projects for this board, and have at it. Start with > something small that already works (like the simple seconds/minutes > "clock" -- really a stopwatch), and play around and get more exotic. Hi Austin, I'm glad you had a nice experience. I finally got a round to unpacking my very nice ML401 board and fired up the latest ISE WebPack 8.2. First freeze came within a few minutes while in the text editor. ISE simply displayed an hour glass and didn't respond. I had to terminate it and start over. Finally got a to compile. Double clicked on one of the ERROR links (*) - followed by an ISE crash. Sigh. Start over. Five minutes more and it hung again. How can people use this? Tommy PS: My PC is stable and up to date. WinXP Pro SP2. (*): The error was: NgdBuild:756 - Line 661 in 'B:/..../system.ucf': Could not find net(s) 'gpio_char_lcd<*>' in the design. To suppress this error specify the correct net name or remove the constraint. Does that really mean that I can't have a master .ucf file without using every single pin in every design? (I do have "Allow Unmatched LOC Constaints" checked.)Article: 108718
The signals getting to the pio and the edge capture register responds to the inputs. I really don't have any idea why the interrupt doesn't work.Article: 108719
Dave wrote: > Ben.Nader@gmail.com wrote: > > Hi > > > > I am trying to programm a XC2S300E through a microcontroller using the > > Slave p mode. > > I make a ufp file ( which is just a hex file) of my program using > > xilinx ISE 8.1 and then using the microcontroller and and slave mode > > signals I send it to the fpga. > > I have all this working for another design, which is exactly the same > > micro but Xc2S150E FPGA. but I can not get this to work on XC2S300E. > > > > here is what happens: > > > > 1. I pulsed the ~prog line low and then high. ( to start the clearing > > configuration memory) > > 2. I see FPGA lowers INIT line ( it shows it is busy clearning the > > memory) > > 3. INIT goes high > > 4. I am sending Clock along with 8bit data on D[7:0] and CCLK. > > 5. I see INIT stays high ( so I thought CRC check was okay) > > 6. DONE stays low, I never see it coming up. > > > > after extensive search on the Xilinx website I read something that I > > could have a timing problem and I should keep sending CCLK till DONE > > goes high. so I tried just running CCLK for like a full SECOND after I > > was done sending my real data, and I still never saw DONE going high. > > > > I purposly changed my hex file to see if I the CRC error happens and > > INIT goes low. but I never saw this. INIT was high the entire time > > after the initial memory clearning process( FPGA pulled it low then) > > so this means I am not as far as CRC test on the flow chart. I am > > wondering If FPGA thinks that it is not at the end of the file yet or > > if it is reading anything at all. > > I also checked the number of bits on hex file and it matches the > > number on the Xilinx Datasheet. so I know I build the correct hex > > file. > > > > I have 3 different boards with XC2S300E that I have this problem with. > > so I doubt I have a connectivity issue or anything like that. > > > > I also double checked my pull up and downs like 100 times by now. they > > all makes sense and match my board with XC2S150E( which I can > > configure with no problem) > > > > Do you guys have any ideas where the problem coming from?.. what other > > things I should look at? > > > > I appreciate you taking the time and reading my long email and helping > > me > > > > Ben > > I use a similar scheme for an XC2S200E and a '50E, except that I use a > single bit wide data path. Initially I had similar problems. I found that > the power supply rise was not monotonic, and this seemed to upset things. I > also found that sometimes if the configuration process failed then the fpga > needed to be power cycled before it would behave - so I implemented a series > fet to do precisely that :-] The whole system is in a distributed noisy > environment, and now I basically turn on the main power with the fpgas > powered off, wait for everything to settle, then turn on and configure fpgas > in a staggered sequence. Crude it may be, but it works in the field ... The XC2S parts are notorious for being difficult to power. They went so far as to recommend that you use an LDO and large caps to generate the core voltage to make sure the voltage ramp is monotonic in spite of the the high surge current that the chips produce. I never was bitten by this one, but if you missed the spec on power-on surge requirments, you could be a victim. The Spartan 3 devices don't have this problem, so sometimes Xilinx does deal with bad engineering, if it is their own!Article: 108720
Tommy Thorn schrieb: > Austin Lesea wrote: > > I was recently asked to do a course, which involves actually showing > > folks real hardware, with real software. > > > > So, like a good teacher, I went and personally purchased the Digilent > > pcb (this is not for work!), the USB programming cable, and went at it. > > > > I also downloaded 8.2 webpack, and the service pack. > ... > > Find the zipped projects for this board, and have at it. Start with > > something small that already works (like the simple seconds/minutes > > "clock" -- really a stopwatch), and play around and get more exotic. > > Hi Austin, > > I'm glad you had a nice experience. I finally got a round to unpacking > my very nice ML401 board and fired up the latest ISE WebPack 8.2. First > freeze came within a few minutes while in the text editor. ISE simply > displayed an hour glass and didn't respond. I had to terminate it and > start over. Finally got a to compile. Double clicked on one of the ERROR > links (*) - followed by an ISE crash. Sigh. Start > over. Five minutes more and it hung again. > > How can people use this? > > Tommy > PS: My PC is stable and up to date. WinXP Pro SP2. > > (*): The error was: > > NgdBuild:756 - Line 661 in 'B:/..../system.ucf': Could not find > net(s) 'gpio_char_lcd<*>' in the design. To suppress this error > specify the correct net name or remove the constraint. > > Does that really mean that I can't have a master .ucf file without using > every single pin in every design? (I do have "Allow Unmatched LOC > Constaints" checked.) the allow unmatched LOC doesnt always do the trick :( NET MYPIN<*> PULLUP; is nice to have, but if the net doesnt exist then it will complain. its real pain sometimes AnttiArticle: 108721
Antti wrote: > the allow unmatched LOC doesnt always do the trick :( > > NET MYPIN<*> PULLUP; > > is nice to have, but if the net doesnt exist then it will complain. > its real pain sometimes Thanks Antti. FWIW, it appears that ISE have major issues with mapped network drives. I moved my directory to the local disk and now everything works much better. Cheers, TommyArticle: 108722
u_stadler@yahoo.de wrote: > hi i have a problem getting the lwip to work. my c code is pretty > simple: > when i build the projet i get the following error message: > > Building target: ethernet.elf > mb-gcc -o ethernet.elf main.o > -LC:/CodeGeeks/test_edk3/microblaze_0/lib -Wl,-T > -Wl,"C:\CodeGeeks\test_edk3\TestApp_Memory\src\TestApp_Memory_LinkScr.ld" > -lxilkernel -llwip4 > C:/CodeGeeks/test_edk3/microblaze_0/lib/liblwip4.a(sys_arch.o): In > function `sys_arch_sem_wait': > /cygdrive/c/CodeGeeks/test_edk3/microblaze_0/libsrc/lwip_v2_00_a/src/contrib/ports/v2pro/sys_arch.c(.text+0x148): > undefined reference to `sem_timedwait' > C:/CodeGeeks/test_edk3/microblaze_0/lib/liblwip4.a(sys_arch.o): In > function `sys_arch_mbox_fetch': > /cygdrive/c/CodeGeeks/test_edk3/microblaze_0/libsrc/lwip_v2_00_a/src/contrib/ports/v2pro/sys_arch.c(.text+0x594): > undefined reference to `sem_timedwait' > collect2: ld returned 1 exit status > make: *** [ethernet.elf] Error 1 > Build complete for project ethernet gcc is complaining that it can't find sem_timedwait which is part of the xilkernel semaphore library. As it turns out, this library is optional. Try: Software Platform Settings/OS and Libraries/config_sema = true (see EDK/docs/oslib_rm.pdf) Alan NishiokaArticle: 108723
horst wrote: > The signals getting to the pio and the edge capture register responds > to the inputs. > I really don't have any idea why the interrupt doesn't work. > Do you have the interrupt assigned to the PIO in SOPC builder? MarkArticle: 108724
u_stadler@yahoo.de wrote:
> hi i have a problem getting the lwip to work. my c code is pretty
> simple:
>
> #include "xmk.h"
> #include "stdio.h"
> #include "lwip/api.h"
> #include "xparameters.h"
>
> int main()
> {
> xil_printf("Entering main \r\n");
>
> xilkernel_main();
> return 0;
> }
>
> void* system_setup(void* arg)
> {
> xil_printf("Initializing lwIP .");
> lwip_init();
> xil_printf(" done. \n");
>
> return 0;
> }
>
>
>
> the mms file is:
>
> BEGIN OS
> PARAMETER OS_NAME = xilkernel
> PARAMETER OS_VER = 3.00.a
> PARAMETER PROC_INSTANCE = microblaze_0
> PARAMETER sysintc_spec = opb_intc_0
> PARAMETER stdout = RS232_DCE
> PARAMETER stdin = RS232_DCE
> PARAMETER config_debug_support = true
> PARAMETER debug_mon = true
> PARAMETER verbose = true
> PARAMETER config_sema = true
> PARAMETER config_msgq = true
> PARAMETER msgq_capacity = 2
> PARAMETER sched_type = SCHED_PRIO
> PARAMETER systmr_interval = 5
> PARAMETER systmr_freq = 50000000
> PARAMETER systmr_dev = opb_timer_1
> PARAMETER use_xil_malloc = true
> PARAMETER static_pthread_table = ((system_setup,1))
> END
>
> BEGIN LIBRARY
> PARAMETER LIBRARY_NAME = lwip
> PARAMETER LIBRARY_VER = 2.00.a
> PARAMETER PROC_INSTANCE = microblaze_0
> PARAMETER api_mode = SOCKETS_API
> PARAMETER lwip_debug = true
> PARAMETER emaclite_instances =
> ((Ethernet_MAC,0x01,0x02,0x03,0x04,0x05))
> END
>
>
>
> As linker options i use : -lxilkernel -llwip4
>
> when i build the projet i get the following error message:
>
> Building target: ethernet.elf
> mb-gcc -o ethernet.elf main.o
> -LC:/CodeGeeks/test_edk3/microblaze_0/lib -Wl,-T
> -Wl,"C:\CodeGeeks\test_edk3\TestApp_Memory\src\TestApp_Memory_LinkScr.ld"
> -lxilkernel -llwip4
> C:/CodeGeeks/test_edk3/microblaze_0/lib/liblwip4.a(sys_arch.o): In
> function `sys_arch_sem_wait':
> /cygdrive/c/CodeGeeks/test_edk3/microblaze_0/libsrc/lwip_v2_00_a/src/contrib/ports/v2pro/sys_arch.c(.text+0x148):
> undefined reference to `sem_timedwait'
> C:/CodeGeeks/test_edk3/microblaze_0/lib/liblwip4.a(sys_arch.o): In
> function `sys_arch_mbox_fetch':
> /cygdrive/c/CodeGeeks/test_edk3/microblaze_0/libsrc/lwip_v2_00_a/src/contrib/ports/v2pro/sys_arch.c(.text+0x594):
> undefined reference to `sem_timedwait'
Well, you're missing the 'sem_timedwait' function call. I'm not familiar
with the Xilinx development environment, so I can't tell you where to look
for it.
Mark
> collect2: ld returned 1 exit status
> make: *** [ethernet.elf] Error 1
> Build complete for project ethernet
>
>
> Could somebody help me here please?
>
> thanks
> Urban
>
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