Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
John_H wrote: > As for Windows... ? > <google@gornall.net> wrote in message > news:1158350290.111061.285470@m73g2000cwd.googlegroups.com... > > Anyone know if the P&R tools are multi-threaded ?> > Simon Our FAE mentioned that multi-thread (multi-core) support is slated for a future release, I think he said sometime in 2007.Article: 108751
Austin Lesea wrote: > False Rumor, > > We still require signal integrity to be correct, and have no plans to > try to deal with bad engineering. Is that really what you meant to say ?! -jgArticle: 108752
John Larkin wrote: > > Grumble, snarl, I guess I'll use an FDV301 like Larry suggests... > somebody else down the hall has just selected that same part for > another board. Damned things cost 9 cents! > > Roger the Maxim parts; they're expensive, but the good news is that > you can't get them, so you save a lot of money. The FDV301's has esd protection, and is a tigher spec than the 7002. I see digikey have them for 5.4c/10K - and you are making >10K, to be worried about single digit cents, right ? :) You gan get the Transistor+Resistor I mentioned in a single package, look for PDTC11xx, these are ~1.7c each. -jgArticle: 108753
John Larkin wrote:
> Rumor has it that some future Xilinx parts will add schmitt triggers
> to CCLK and maybe some other config pins.
and Austin Lesea replied:
> False Rumor,
>
> We still require signal integrity to be correct, and have
> no plans to try to deal with bad engineering.
>
Oddly enough, that particular Schmitt CCLK rumor was
confirmed by Steve Knapp last spring [1] :
>
> Fortunately, this is already a planned enhancement on future families.
>
Fortunately, those nice GPD guys don't seem to pay any
attention to Austin's newsgroup prevarications.
Which gives us such improvements as Schmitt triggered
CCLKs, and S3E's simplified, DCI-free I/O buffers, having
a quarter the input capacitance of a V4.
Brian
[1] Steve Knapp's post about forthcoming Schmitt CCLK pins
http://groups.google.com/group/comp.arch.fpga/msg/e7a5680ff3675cca
Article: 108754Brian, I see Steve at lunch, so I will have to ask him who he talked to. 100 mV of hysterisis is pretty much part of all input buffers, but that won't do it. Austin Brian Davis wrote: > John Larkin wrote: > >>Rumor has it that some future Xilinx parts will add schmitt triggers >>to CCLK and maybe some other config pins. > > > and Austin Lesea replied: > >>False Rumor, >> >>We still require signal integrity to be correct, and have >>no plans to try to deal with bad engineering. >> > > > Oddly enough, that particular Schmitt CCLK rumor was > confirmed by Steve Knapp last spring [1] : > >>Fortunately, this is already a planned enhancement on future families. >> > > > Fortunately, those nice GPD guys don't seem to pay any > attention to Austin's newsgroup prevarications. > > Which gives us such improvements as Schmitt triggered > CCLKs, and S3E's simplified, DCI-free I/O buffers, having > a quarter the input capacitance of a V4. > > Brian > > [1] Steve Knapp's post about forthcoming Schmitt CCLK pins > http://groups.google.com/group/comp.arch.fpga/msg/e7a5680ff3675cca >Article: 108755
Jim, Not sure what you mean. If you mean that Xilinx should encourage bad engineering, well, no, we don't. Austin Jim Granville wrote: > Austin Lesea wrote: > >> False Rumor, >> >> We still require signal integrity to be correct, and have no plans to >> try to deal with bad engineering. > > > Is that really what you meant to say ?! > -jg >Article: 108756
John Larkin wrote: > On 15 Sep 2006 15:56:47 -0700, "PeteS" <PeterSmith1954@googlemail.com> > wrote: > >But amongst all this John faces the standard hardware design issue: > >cost. A 2N7002 is 3 cents and thus easy to drop in by the 10s of units > >(layout costs aside). As to a voltage divider, I don't trust a FET to > >be off unless it's pulled to ground (it's actually in a sub-threshold > >region otherwise with a very undefined [generally] drain-source > >resistance) so I would not personally countenance that. > > > >Much depends on the cost sensitivity of John's product. In some cases, > >one can justify a full solution, in others one can not (and some > >vendors would do well to learn that lesson). > > > >Amusingly, on the subject of vendors and cost, I was comparing a MAX > >device against it's second source at TI today: MAX wants $3.11, TI > >wants $0.74. Hmm. > > > >Cheers > > > >PeteS > > Grumble, snarl, I guess I'll use an FDV301 like Larry suggests... > somebody else down the hall has just selected that same part for > another board. Damned things cost 9 cents! I don't see how 9 cents vs. 3 cents can make a difference when you are interfacing to a $20+ chip! If you really need to save the $0.06 per on a few pins, just beat on Xilinx a little harder and I am sure you can get them to drop their price another $0.50. Dammed things costs >$20!!! Or you could just spend another couple of hours to locate a lower threshold FET that is just as cheap as the 7002!Article: 108757
John said: > Check for ringing on the CCLK signal at the fpga... that has nailed us > a couple of times. Try adding 33 pF to ground, just to see if that's > the problem. Sometimes just probing CCLK at the chip will allow a > config to complete. > > Rumor has it that some future Xilinx parts will add schmitt triggers > to CCLK and maybe some other config pins. Lately, we're adding > TinyLogic schmitt buffers right at the pin, unless the trace is *very* > short. > > CCLK signal integrity requirements are right up there with all the > other clocks on the board. > > John Austin said: > We still require signal integrity to be correct, and have no plans to > try to deal with bad engineering. Since John described a problem that required additional parts, and is thus an oversight in the FPGA design, that to me fitted the "bad engineering" descriptor quite nicely. However, your reply suggests Xilinx have a very different way of measuring "bad engineering" ? and I was left bemused... -jgArticle: 108758
"ziggy" <ziggy@fakedaddress.com> schrieb im Newsbeitrag news:ziggy-E12AF3.19422315092006@news.isp.giganews.com... > Ok, so a link to these people came across my mail box today. and its > supposedly a Open Source 64bit sparc core.. > > Anyone that has seen this before want to comment? > > Oh, and the little piece of hardware they show on their pages, anyone > know what that is and where it came from? yes it s OpenSparc I tried with ISE but only got portability error, so you possible need synplify if targetting Xilinx the piece of hardware pictured is ir-relavant, it is I think what the authors think a picture of something that is understood as hardware AnttiArticle: 108759
Hello, I'm trying to compile the JOP core for my Xilinx Spartan3 Starter Kit (ISE webpack 8.2i), but I get stuck because the following components cannot be found: rom.vhd xram_block.vhd jtbl.vhd offtbl.vhd Anyone who had the same issue, or knows how to find/create the missing components ? I'm following the document 'An introduction to the Design Flow for JOP', section 1.3... and I'm already stuck at the first step. I hope it will go better once this step has been overcome... :-) Thanx, StefanArticle: 108760
John Woodgate wrote: > In message <hn%Jg.4654$tU.648@newssvr21.news.prodigy.com>, dated Fri, 1 > Sep 2006, Joerg <notthisjoergsch@removethispacbell.net> writes > >>Has limits though: A neighbor told me that a guy showed up for an >>interview with a T-shirt that read "People Suck". The interview ended >>after about one second. > > Not sensible. You can get T-shirts with Schroedinger's Equation on them. > They don't make you a physicist. > > You explore the 'inappropriate behaviour' only after you find that the > guy knows what a Gilbert cell is and is used for. If s/he doesn't, you > don't need to explore it. I disagree, the appearance upon entering the interview stated clearly that the candidate was not in the least interested in working for a suit bound, mature hierarchy and had reasonable desire to minimize the amount of time lost to both parties. I am wildly extrapolating that said candidate would not have presented the same way at your company. -- JosephKK Gegen dummheit kampfen die Gotter Selbst, vergebens. --SchillerArticle: 108761
On 15 Sep 2006 14:38:26 +0200, "Symon" <symon_brewer@hotmail.com> wrote: >Martin, >You can only use certain I/O standards with specific Vccos. If you want to >change voltage, you must change both the I/O standard and Vcco. Read the >manual about the I/O banking rules. >HTH, Syms. > There are quite a lot of manuals, and quite a lot of reading... sometimes even finding what you want in all the available literature is quite an achievement. where would you suggest the reader should start for a good outline of the I/O banking rules? I don't know if the OP wuold appreciate such a hint, but I confess I would. - BrianArticle: 108762
Charlie Edmondson wrote: > Michael A. Terrell wrote: >> >> >> >> Ernie wasn't very happy by the time it was over, then was forced to >> quit or be fired a few months later at a time when my word could have >> let him keep his job. On top of that, I got ten times what he did for >> my Christmas bonus that year. I made almost twice what he got that >> year, then he was looking for another job with the company telling his >> prospective new employers that they couldn't comment till the lawsuit >> was settled. :) >> >> >> >> > Had a similiar situation when I worked on the 91 Express lanes toll > road. My boss was a real A-hole, who would do things like, pull out a > knife and shave his arms, commenting on how sharp it was, while asking > for the status of your assignments. The threat was very thinly veiled... > > Then, about 9 months later, I was working for the other toll road > company and he came in for an interview. For some reason, he wasn't > hired... 8-) > > Charlie And what locale would that have been in? -- JosephKK Gegen dummheit kampfen die Gotter Selbst, vergebens. --SchillerArticle: 108763
Michael A. Terrell wrote: > David Ashley wrote: >> >> Michael A. Terrell wrote: >> > It was either do the work or be fired. I didn't do it to help him, >> > in any way. I needed the job, because there was nothing else available >> > in my field at the time. The only open job I could find was chief >> > engineer at WRGT TV, Ch 45 in Dayton, Ohio which was an even longer >> > drive. They were only offering minimum wage for a 40 hour a week >> > salary, and you would be on call 24/7. They also demanded that I live >> > no more than 2 miles from the studio and transmitter sites which didn't >> > have any reasonably priced homes. Would you take a loss on the sale of >> > your home and buy one at five times the price, while taking a 70% cut >> > in >> > pay? I couldn't, and I didn't. I just suffered though another of his >> > messes, and made a lot in overtime. >> >> Hopefully it'll even out. The higher ups will probably be aware of the >> extra overtime they needed to spend to solve this problem. Ideally >> they'll know who to blame for the problem. >> >> Often if you care for the overall health of the company, you need to >> solve a crisis and in so doing bail out some incompetent. >> C'est la vie. >> >> -Dave >> >> -- >> David Ashley http://www.xdr.com/dash >> Embedded linux, device drivers, system architecture > > > That was 20 years ago, and Ernie was forced to quit over sexual > harassment charges, filed by then current and former female employees. > > I always worked my ass off at any job. The big bosses weren't > stupid. When major problems go away right after someone new is hired, > they know it's not a long term employee who suddenly started working > harder, smarter, or both. After the sudden changes the owner came for a > visit to see what had happened. Of course, Ernie tried to take the > credit. The owner turned to me and said, Great! Now tell me exactly > what you did to fix the problems Ernie couldn't. I described what I had > done to take us from the lowest customer service rated CATV system in > the area, to the number one in under six months. Ernie was quite > pissed! > > And if i have followed the story aright, Ernie reaped the "full benefit" of what he had sown. -- JosephKK Gegen dummheit kampfen die Gotter Selbst, vergebens. --SchillerArticle: 108764
In article <eeg5tm$49e$1@online.de>, "Antti Lukats" <antti@openchip.org> wrote: > "ziggy" <ziggy@fakedaddress.com> schrieb im Newsbeitrag > news:ziggy-E12AF3.19422315092006@news.isp.giganews.com... > > Ok, so a link to these people came across my mail box today. and its > > supposedly a Open Source 64bit sparc core.. > > > > Anyone that has seen this before want to comment? > > > > Oh, and the little piece of hardware they show on their pages, anyone > > know what that is and where it came from? > > yes it s OpenSparc > > I tried with ISE but only got portability error, so you possible need > synplify if targetting Xilinx > > the piece of hardware pictured is ir-relavant, it is I think what the > authors think a picture of something that is understood as hardware > > Antti That is what i thought, but with a lot of wackos out there you never know. On the hardware, shoot, i was hoping it was some new really inexpensive deve board or something.Article: 108765
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:3fong21thj450qaqdharsmgkcjv7oiedhk@4ax.com... > On 15 Sep 2006 14:38:26 +0200, "Symon" <symon_brewer@hotmail.com> wrote: > >>Martin, >>You can only use certain I/O standards with specific Vccos. If you want to >>change voltage, you must change both the I/O standard and Vcco. Read the >>manual about the I/O banking rules. >>HTH, Syms. >> > > There are quite a lot of manuals, and quite a lot of reading... > sometimes even finding what you want in all the available literature is > quite an achievement. > > where would you suggest the reader should start for a good outline of > the I/O banking rules? > > I don't know if the OP wuold appreciate such a hint, but I confess I > would. > > - Brian Hi Brian, You're right, the Xilinx literature can be an insomniac's delight! In this case however, the data is right where you'd expect it. Get DS083, the VII-Pro datasheet, under functional description, FPGA, IOBs, there's a table called 'Supported Single-Ended I/O Standards.'. A little below that is a whole section called 'I/O Banking'. HTH, Syms.Article: 108766
Homer J Simpson wrote: > > "PeteS" <PeterSmith1954@googlemail.com> wrote in message > news:1157987644.057824.253860@b28g2000cwb.googlegroups.com... > > And besides, all work and no play makes a dull person (and a dull > employee too ;) > > Is there any other sort of employee? Yes, the kind that makes the both of you well off to wealthy. -- JosephKK Gegen dummheit kampfen die Gotter Selbst, vergebens. --SchillerArticle: 108767
John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote: ... > Grumble, snarl, I guess I'll use an FDV301 like Larry suggests... > somebody else down the hall has just selected that same part for > another board. Damned things cost 9 cents! > Roger the Maxim parts; they're expensive, but the good news is that > you can't get them, so you save a lot of money. Check for availabilty of the FDV301 too. Neither Digikey nor Farnell has stock. So perhaps you save on the FDV3012 too, like on the Maxim parts ;-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 108768
Antti Lukats <antti@openchip.org> wrote: > "ziggy" <ziggy@fakedaddress.com> schrieb im Newsbeitrag > news:ziggy-E12AF3.19422315092006@news.isp.giganews.com... > > Ok, so a link to these people came across my mail box today. and its > > supposedly a Open Source 64bit sparc core.. > > > > Anyone that has seen this before want to comment? > > > > Oh, and the little piece of hardware they show on their pages, anyone > > know what that is and where it came from? > yes it s OpenSparc > I tried with ISE but only got portability error, so you possible need > synplify if targetting Xilinx > the piece of hardware pictured is ir-relavant, it is I think what the > authors think a picture of something that is understood as hardware Any idea at what FPGA class this design is targeted? Anything available PQ208 package? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 108769
Antti <Antti.Lukats@xilant.com> wrote: > I am trying it right now - seems like lot of fun, when trying it with > Xilinx ISE it has already managed to make 3 different kinds of fatal > crashes !! > so it would be good test case for Xilinx to test their software > against. Well, do you have the impression that the ISE programmers test their software and have a regression test suite? For example they claimed the Impact crash on Linux when reloading a bitstream/jedec file fixed, obvious it wasn't, as easy test showed (Xilinx Answer #23745). Or if you look at the still unsilved VLGINCDIR problem Answer Record # 17027. It worked in some ISE 6 version, but was broken in ISE 7 again. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 108770
In message <09ROg.1689$6S3.769@newssvr25.news.prodigy.net>, dated Sat, 16 Sep 2006, joseph2k <quiettechblue@yahoo.com> writes >I disagree, the appearance upon entering the interview stated clearly >that the candidate was not in the least interested in working for a >suit bound, mature hierarchy and had reasonable desire to minimize the >amount of time lost to both parties. I am wildly extrapolating that >said candidate would not have presented the same way at your company. I don't employ anyone, but a friend of mine recruited a guy, against his initial judgement, who had, and has, multicoloured hair. He's GOOD, but I suppose software artists are allowed to be bohemian. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk There are benefits from being irrational - just ask the square root of 2. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 108771
How do other people handle this problem. The UCF file assemble requirements form two different areas: Things like timing and things like Pin assignments. Pin assignment needs to be generated from layout files and may change often. As I don't know of a way to include something in the UCF file, the UCF file needs to be carefully edited each time the pin assignment changes. If there would be a possiblity to include something in the UCF file, the pin assignment could be generated in a seperate file, the include in the UCF could point to that file and changes would get picked up automatically. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 108772
Hi I need to interface a coolrunner II using SSTL. This is all quite straightforward and fully documented. However I would allso like to do boundary scan testing on this bus using SSTL voltage levels and I can find no mention that when an IOB is doing boundary scan it can reference a vref pin. The documented IOB does not show where the IOB boundary scan cell is. If anyone can shed some light on this I would appreciate it as I'm otherwise ready to have the board laid out. Regards all ColinArticle: 108773
Austin Lesea wrote: > Ahh, > > http://en.wikipedia.org/wiki/Newton_polynomial > > Austin > > eziggurat@gmail.com wrote: >> The link is >> http://doi.ieeecomputersociety.org/10.1109/ICICIC.2006.226#search=%22adaptive%20newton%20FPGA%22 >> for the algorithm. >> >> >> >> yttrium wrote: >>> eziggurat@gmail.com wrote: >>>> Hi, >>>> >>>> I was wondering what is most fast and efficient intepolation algorithm >>>> that easily adaptable in a Spartan 3 and able to process more than 60 >>>> frames per seconds? >>>> >>>> I have read a paper about an adaptive Newton interpolation algorithm >>>> that suppose to use less resources than the Bicubic and comparable with >>>> the image quality of the Bicubic. >>>> >>>> The algorithm will be used to scale the output of a LCD driver IC that >>>> outputs 18 to 24 bits RGB and FPGA will scale the image less than 18 >>>> bits and use on a smaller LCD screen. >>>> >>>> Any tips will be very helpful. >>>> >>>> Regards >>>> P >>>> >>> That is interesting, i will start with an interpolation algorithm next >>> week ... >>> >>> where can i find that paper about the adaptive Newton interpolation >>> algorithm? >>> >>> Thanks in advance, >>> >>> Kind regards, >>> >>> Y Thanks for both links ... i am looking for the best algorithm tradeoff for performance/quality/fpga implementation ... so i found this site: http://www.geovista.psu.edu/sites/geocomp99/Gc99/082/gc_082.htm I will need about 7*3*4 interpolations so it needs to be quite a efficient implementation for space ... that's why the linear intepolation seems the easiest but not the most exact ... that's why i'm looking into some other algo's as well ... kind regards, yArticle: 108774
that was the problem. thanks
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z