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Hi John, your idea might work for awhile, but not for the 20 years of lifetime that is our criterion. I would pay a little more for a proper level converter... Hope to see you some time again! Peter Alfke, Xilinx =========================== John Larkin wrote: > I've got some DACs that I'd like to switch gain ranges on, and it > turns out I can do it nicely using a single 2N7002 (sot23 n-channel > mosfet) to switch a resistor to ground in each reference circuit. So > I'd like to turn each 7002 on and off from a pin on an XC3S400. But > 3.3 volts is a marginal high for this fet... 4 volts looks safe. > > So, how about running Vccio a bit high, 3.5 maybe, and adding an > external pullup resistor to +5. If I tristate the pin, I should > forward-bias the upper esd diode and get 4.2 roughly, right? I'm > thinking maybe a half milliampere or so pullup current. Doing this 8 > times only dumps 4 mA into the Vccio rail, no hazard there. > > I could use a lower-threshold fet, I guess, but the 7002's are in > stock and cost 3 cents each. > > JohnArticle: 108676
A more constructive idea: connect the cathode of a simple diode to each FPGA output, and pull the anode through 470 Ohm to 5 V. Then use the diode-resistor node to drive your FET. This means you have shifted the voltage up by 0.7 V. Pool Low voltage of ~0.9 V,but fairly good High voltage, 3.3 V + two diodes = 4.7V Peter Alfke ============ John Larkin wrote: > I've got some DACs that I'd like to switch gain ranges on, and it > turns out I can do it nicely using a single 2N7002 (sot23 n-channel > mosfet) to switch a resistor to ground in each reference circuit. So > I'd like to turn each 7002 on and off from a pin on an XC3S400. But > 3.3 volts is a marginal high for this fet... 4 volts looks safe. > > So, how about running Vccio a bit high, 3.5 maybe, and adding an > external pullup resistor to +5. If I tristate the pin, I should > forward-bias the upper esd diode and get 4.2 roughly, right? I'm > thinking maybe a half milliampere or so pullup current. Doing this 8 > times only dumps 4 mA into the Vccio rail, no hazard there. > > I could use a lower-threshold fet, I guess, but the 7002's are in > stock and cost 3 cents each. > > JohnArticle: 108677
On 14 Sep 2006 19:09:58 -0700, "Peter Alfke" <alfke@sbcglobal.net> wrote: >Hi John, >your idea might work for awhile, but not for the 20 years of lifetime >that is our criterion. Is there a failure mechanism? JohnArticle: 108678
On Fri, 15 Sep 2006 12:40:54 +1200, Jim Granville <no.spam@designtools.maps.co.nz> wrote: >John Larkin wrote: >> I've got some DACs that I'd like to switch gain ranges on, and it >> turns out I can do it nicely using a single 2N7002 (sot23 n-channel >> mosfet) to switch a resistor to ground in each reference circuit. So >> I'd like to turn each 7002 on and off from a pin on an XC3S400. But >> 3.3 volts is a marginal high for this fet... 4 volts looks safe. >> >> So, how about running Vccio a bit high, 3.5 maybe, and adding an >> external pullup resistor to +5. If I tristate the pin, I should >> forward-bias the upper esd diode and get 4.2 roughly, right? I'm >> thinking maybe a half milliampere or so pullup current. Doing this 8 >> times only dumps 4 mA into the Vccio rail, no hazard there. >> >> I could use a lower-threshold fet, I guess, but the 7002's are in >> stock and cost 3 cents each. > > You can also switch with NPN transistor + resistor, and a reverse >connected one has lower saturation voltage ( and lower beta too ). > Once I start adding parts, I may as well go with an octal level shifter and get all the way to 5 volts. The pcb would route nicer if I could use just the pullups. > What resistance do you expect of the on devices ? The 2N7002's go to about 2 ohms with 4 volts or so on the gates, and that 2 ohms will have a roughly +6000 PPM/K tc, net 12 mohm/K, which is good enough here... that will cause just a few PPM/K dac gain error. John > > -jgArticle: 108679
Folks, Is ispDesignExpert available for download anywhere these days ? Thanks for any help ! -rajeev-Article: 108680
Motty, so you have an LVDS input pair not driven by anything, and when you check its internally propagated signal it shows a certain frequency (300 MHz) that exists inside the chip. The flip answer is "don't do that!". An un-driven LVDS input is a high-gain amplifier that is prone to pick up anything. In your case it somehow picks up a clock signal. You might play around with the un-driven pins, load them with a capacitor, pull them apart with two resistors, etc to get a feel for the sensitivity, Since this is an abnormal situation, I would not lose sleep over it. Peter Alfke ======== motty wrote: > I am using the ML401 board to build up some test logic. The 100MHz XO > on the baord is fed into a DCM via a global buffer. I am using the FX > output (x3) to bump the clock up to 300MHz. There is no feedback > source on this DCM b/c I don't care about its input/output phase > relationship. That FX output is fed to another DCM. The CLK0, CLK90, > CLK180, CLK270, and CLKDIV outputs are all used. > > I am using a data generator to input an LVDS signal. The two signals > (data_p and data_n) are fed into the FPGA and connected to an > instantiated differential buffer with an LVDS_25 attibute. The output > of the buffer is fed to both an external IO and internal logic. I just > want to check to make sure the LVDS signal is being transmitted and > buffered correctly. > > I am scoping the output IO (buffered LVDS - single-ended signal at this > point) and see some odd behavior. With the LVDS signal ON, the output > of the pin looks good. It is the single-ended data I would expect. > However, if I turn the data generator off, I get a 300 MHz clock on the > output. It is at the IO voltage too - 2.5V...and clean! Now, I can > turn the OUTPUT channels of the data generator off. That removes the > DC bias on the data_p and data_n signals. The output on the IO pin at > that point is garbage...no signal, but it is ugly...not 0 output. > > If I reset the board...really just resets the DCM and internal logic of > the FPGA, the output IO is a 100MHz clock! Remember, this is with the > data generator output channels OFF. If I turn them ON (channles are DC > biased but no activity on them) and THEN reset the board, I will get > the 300MHz clock output. The weird thing is, is that I can HOLD the > reset to the board and the 300MHz clock never goes away! I would think > that the reset to the DCM's would disable all clock signals. I have > checked the data generator to make sure that it wasn't introducing a > rogue clock. It isn't. I have moved its output frequency around and > never seen it on the output. > > I really haven't looked into this much, but wanted to throw it out here > to see if I am missing something obvious. > > Thanks.Article: 108681
Hi, Can you please tell me where I can see the critical path in Xilinx ISE tool? I am using XST as synthesis tool. RegardsArticle: 108682
Rajeev, I'm afraid this product is no longer available for download, but maybe someone still has it on his/her PC. I assume this version is needed to compile an old project, with a mature device. You can use ispLEVER in this case (I have to maintain old projects). Therefore, click on the device selector (or double click on a device in a project), on bottom right you can check 'show obsolete devices'. Now you will be able to maintain an older project. Success, Luc On 14 Sep 2006 20:30:02 -0700, "Rajeev" <rrr@ieee.org> wrote: >Folks, > >Is ispDesignExpert available for download anywhere these days ? > >Thanks for any help ! > >-rajeev-Article: 108683
Peter Alfke schrieb: > Motty, so you have an LVDS input pair not driven by anything, and when > you check its internally propagated signal it shows a certain frequency > (300 MHz) that exists inside the chip. > The flip answer is "don't do that!". > An un-driven LVDS input is a high-gain amplifier that is prone to pick > up anything. In your case it somehow picks up a clock signal. You might > play around with the un-driven pins, load them with a capacitor, pull > them apart with two resistors, etc to get a feel for the sensitivity, > Since this is an abnormal situation, I would not lose sleep over it. > Peter Alfke > ======== Hi Peter, thanks for the explanation - I was struggling with something similar, I was experimenting on on-chip oscillators, so I also tried a IOB oscillator with LVDS the funny thing is that if an LVDS output is driven, but the traces are short circuit outside the chip the input LVDS buffer still receives the signal as if ther is no short circuit at all! ah this was actually an attempt to use LVDS as short circuit tester, eg tester that senses short circuit but not silicon mounted on boards, it requires voltage below 0.5V so LVDS seems ok, but -- as the input readback is so sensitive it will see the external short circuit not short enough and still sense the signal. if you have LVDS based ring oscillator then making a short circuit on the LVDS pins (no matter how close to the chip!) will not make the oscillator stop, the frequency if I so recall just goes a bit higher with outputs shorted. This sounds a bit strange as the LVDS outputs should not be abel to drive over the treshold with output shorted, but so it is as of experiments. failed attempt - but was fun experiment AnttiArticle: 108684
Austin Lesea wrote: > > So, like a good teacher, I went and personally purchased the Digilent > pcb (this is not for work!), the USB programming cable, and went at it. > > I also downloaded 8.2 webpack, and the service pack. > I am sure you are not having as much fun as some of us do ! :-) >... >... > > I also took a while to find FPGA_Editor, as most people don't care about > it anymore, it is relegated to a sub-bullet in the tree of tools. Most > of what I do at work involves FPGA_Editor, as I am usually verifying > hardware functions, and I do not want the software to "get in my way." I care about FPGA_Editor, as it is the only tool that lets you see the internals of the FPGA, and lets you see how your code translates to the FPGA. I thought it was not included in the Webpack. Since when is Xilinx including the FPGA-Editor in the Webpack ? Time to upgrade my software. Regards Josep DuranArticle: 108685
Hi I have a design that I am having trouble routing. When I look at the clock signals the net skew for one is about 0.8ns were the other are less than 0.1ns. Could this be my problem and if so does anyone have any surgestions. Thanks JonArticle: 108686
Hi have used FFT core from Xilinx. Do you have any particular queries?Article: 108687
Hi Make shure that udev/hotplug starts fxload. Use the newest windriver from jungo.com in the redist directory. If this still doesn't help try the following procedure (works with XUP board): connect cable wait till fxload is finished wait till bus reconnect of device (dmesg is your friend) unplug cable reconnect cable start impact The firmware update has to be finished once. ST PS: Your mail system is broken (alice-dsl).Article: 108688
"James Morrison" <spam1@emorrison.ca> wrote in message news:1158283978.4061.39.camel@spice.emorrison.ca... > uing. So it was using the unsigned library! Needless to say, that > didn't work too well. I changed to using the signed library and it > worked fine. > > Cheers, > > James. > > Hi James, Only a multiplier madman would use other than numeric.std ! :-) You might find Jim Lewis's excellent paper useful, I know I do. http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf HTH, Syms.Article: 108689
John Larkin wrote: > On Fri, 15 Sep 2006 12:40:54 +1200, Jim Granville > <no.spam@designtools.maps.co.nz> wrote: > > >John Larkin wrote: > >> I've got some DACs that I'd like to switch gain ranges on, and it > >> turns out I can do it nicely using a single 2N7002 (sot23 n-channel > >> mosfet) to switch a resistor to ground in each reference circuit. So > >> I'd like to turn each 7002 on and off from a pin on an XC3S400. But > >> 3.3 volts is a marginal high for this fet... 4 volts looks safe. > >> > >> So, how about running Vccio a bit high, 3.5 maybe, and adding an > >> external pullup resistor to +5. If I tristate the pin, I should > >> forward-bias the upper esd diode and get 4.2 roughly, right? I'm > >> thinking maybe a half milliampere or so pullup current. Doing this 8 > >> times only dumps 4 mA into the Vccio rail, no hazard there. > >> > >> I could use a lower-threshold fet, I guess, but the 7002's are in > >> stock and cost 3 cents each. > > > > You can also switch with NPN transistor + resistor, and a reverse > >connected one has lower saturation voltage ( and lower beta too ). > > > > Once I start adding parts, I may as well go with an octal level > shifter and get all the way to 5 volts. The pcb would route nicer if I > could use just the pullups. > > > What resistance do you expect of the on devices ? > > The 2N7002's go to about 2 ohms with 4 volts or so on the gates, and > that 2 ohms will have a roughly +6000 PPM/K tc, net 12 mohm/K, which > is good enough here... that will cause just a few PPM/K dac gain > error. > > John > > > > > > > > -jg You could always use something like a 74AC05 open drain buffer - the device has about 4 ohms of resistance to ground (at 12mA sink). If a couple more ohms isn't an issue, you can dispense with the FETs entirely, but it would add more error than the typical 2 ohms of a 7002 in full drive. Of course, the output FET in a logic gate isn't usually characterised 'thoroughly' :) Cheers PeteSArticle: 108690
Hi everyone, after I have imported my custom peripheral into XPS 8.2i, I added the Design to my System (XC2VP30). The custom peripheral should be attached to the PowerPC using the Onchip peripheral Bus, which is created using the Create/Import Custom Peripheral Wizard. I download my Design to the board with no errors. When I now try to run a C++ File in XPS SDK by pressing the run Button, the XMD exits with the error: "Failed Loading Project, Check if MHS/MSS files are correct (Errors ocurred while creating Hardware System) Initialization Failed: E02 Failed to load XMP file" When I use the "manual" way: open XMD in Command Shell, connect ppc hw -> dow file.elf -> con. The xmd tells me the processor is running, but I get not the results that I expect to see (outputs on RS232). I open the XMD Debugger and the program rests in the first line of the code with no further debugging possible. I get this error when I connect my custom peripheral to PPC, when I use the MicroBlaze, I get no errors. I assume this might have something to do with the address space of the custom peripheral. In the address tab on the right hand side of the XPS Gui I tried to set a address space manually, for example from 0x4200000 to 0x4200ffff. I also tried the "generate address" button, I get the message that "address generation is only supported for single processor desings". But I need both processors in a next step and I just tried to delete one of the ppcs in the design, which leads to more errors. At last I tried to simply leave my custom peripheral without address space, as some of the components in the address tab also do not seem to have one. So has anybody a solution for my problem? How do I succesfully connect my custom peripheral to the PPC? Thanks and Regards, PeterArticle: 108691
Hi to all, I'm trying to set the output voltage level of a Virtex 2 pro using the IOSTANDARD constraint, but it doesn't work. More exactly, I'm using the XUP Virtex-II Pro Development System (an evaluation board) by Xilinx. For an application, I need the FPGA to output 3.3 V signals on the left low-speed expansion connector. I have tried to achieve this by placing the following lines in my UCF file (using one of the signals as an example): NET "camera_sio_d" LOC = "U3"; NET "camera_sio_d" IOSTANDARD = LVTTL; However, the FPGA outputs 2.5 V for digital 1 (0 V for digital 0), measured with no load on the signal. I have tried different values for IOSTANDARD as an experiment (LVTTL, LVCMOS33, LVCMOS15, and omitting the constaint altogether), but nothing happens - I still get 2.5 V. The scope is fast enough, and by tweaking the timing a bit I can say that these voltage levels are stable (no capacity being charged anymore). The voltage supply for the whole board also seems to be okay. Note that even LVCMOS15 (which should give me 1.5 V) doesn't work, so I don't think it's an electrical problem. To avoid problems with banking rules for the pins, I have set all pins on the relevant bank to the levels described above. The implementation tools do complain if the IOSTANDARD of different pins on the same bank mismatch, so I think I'm not doing this anymore. To be sure, I have looked at the pad report, and also viewd the placed and routed configuration in the FPGA editor. Both tell me that the IOSTANDARD is indeed set to the value I want. Still I get 2.5 V when programming the real FPGA. Thanks in advance for any ideas. Martin GeisseArticle: 108692
Luc, Thanks for your response. lb.edc@telenet.be wrote: > Rajeev, > > I'm afraid this product is no longer available for download, but maybe > someone still has it on his/her PC. > I assume this version is needed to compile an old project, with a > mature device. Believe it or not, it's for a new design. I need a small amount of logic to implement a simple state machine (2 machines, 4 states each). Since there is no programmable logic anywhere else in the system, I'm reluctant to install learn and maintain heavyweight tools such as ISE Webpack. Also I have 5V but not yet 3.3V so using an older device makes sense. I'm also strapped for cash at the moment, and ispDesignExpert would as I understand be no charge. > You can use ispLEVER in this case (I have to maintain old projects). I will look into this. (I'm also considering resurrecting PALASM). > Therefore, click on the device selector (or double click on a device > in a project), on bottom right you can check 'show obsolete devices'. > Now you will be able to maintain an older project. > > Success, > > Luc > > On 14 Sep 2006 20:30:02 -0700, "Rajeev" <rrr@ieee.org> wrote: > > >Folks, > > > >Is ispDesignExpert available for download anywhere these days ? > > > >Thanks for any help ! > > > >-rajeev- Thanks ! -rajeev-Article: 108693
Martin, You can only use certain I/O standards with specific Vccos. If you want to change voltage, you must change both the I/O standard and Vcco. Read the manual about the I/O banking rules. HTH, Syms.Article: 108694
Does anyone know if ANY of the Actel fusion devices are available for purchase? -EliArticle: 108695
I think the best way to understand a piece of code it's to run simulation on it and check the waveforms. Also a good simulator with shematic view of the source code will be helpful. HTH, Jim http://home.comcast.net/~jimwu88/tools/ Davy wrote: > Hi all, > > Is there any general tips of reading Verilog code. I want to collect > these tips to accelerate code reading speed. > > For example, shall I read the input signal first and trace them until > output? > And shall I read from top to bottom or from bottom to top? > And shall I read the 'always' block first? > > Any questions and comments are welcome :) > > Best regards, > DavyArticle: 108696
Eli Hughes schrieb: > Does anyone know if ANY of the Actel fusion devices are available for > purchase? > > -Eli I received some PQ208 fusion chips over 6 weeks ago already. so I assume the answer is yes. AnttiArticle: 108697
On Fri, 15 Sep 2006 00:46:08 +0200, Ben Twijnstra <btwijnstra@gmail.com> wrote: > this smells of a power-sequencing issue. No, it *smells* of hot epoxy... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 108698
Hi Rajeev, ispLEVER starter version is also free of charge - so no problem there. As for the 5V tolerance, you can use the MACH4A5. This family starts from 32MC's up to 256MC's. Maybe an ispGAL22V10 can do the job for you as well. Gives you isp, so no need for a programmer! Regards, Luc On 15 Sep 2006 05:14:56 -0700, "Rajeev" <rrr@ieee.org> wrote: >Luc, > >Thanks for your response. > >lb.edc@telenet.be wrote: >> Rajeev, >> >> I'm afraid this product is no longer available for download, but maybe >> someone still has it on his/her PC. >> I assume this version is needed to compile an old project, with a >> mature device. > >Believe it or not, it's for a new design. I need a small amount of >logic to implement a simple state machine (2 machines, 4 states each). >Since there is no programmable logic anywhere else in the system, I'm >reluctant to install learn and maintain heavyweight tools such as ISE >Webpack. Also I have 5V but not yet 3.3V so using an older device >makes sense. I'm also strapped for cash at the moment, and >ispDesignExpert would as I understand be no charge. > >> You can use ispLEVER in this case (I have to maintain old projects). > >I will look into this. (I'm also considering resurrecting PALASM). > >> Therefore, click on the device selector (or double click on a device >> in a project), on bottom right you can check 'show obsolete devices'. >> Now you will be able to maintain an older project. >> >> Success, >> >> Luc >> >> On 14 Sep 2006 20:30:02 -0700, "Rajeev" <rrr@ieee.org> wrote: >> >> >Folks, >> > >> >Is ispDesignExpert available for download anywhere these days ? >> > >> >Thanks for any help ! >> > >> >-rajeev- > >Thanks ! > >-rajeev-Article: 108699
On a sunny day (Fri, 15 Sep 2006 00:27:10 +0200) it happened Kolja Sulimma <news@sulimma.de> wrote in <4509d743$0$5146$9b4e6d93@newsspool1.arcor-online.net>: >panteltje@yahoo.com schrieb: >> eziggurat@gmail.com schreef: >> If you are going to 'resize' to a different number of pixels, then make >> sure >> you do a lowpass _before_ the rescaling, to avoid aliasing. >> Here, on my site you can see the difference: >> http://panteltje.com/panteltje/subtitles/lowpass.html >> I do not suggest you use fft and reverse fft,[...] >> But you will perhaps want the lowpass to avoid the aliasing effects. > >A few comments to your web page: >1. >It is not uncommon that you get amplitudes after filtering that are >higher than the original amplitude. That is no shortcoming of the >implementation but inherent in the math. >A square wave of amplitude 1 has a sine component of f with an amplitude >way above 1. While you subtract energy from the signal the amplitude can >rise. Yes, I did ask about this long time ago in sci.math, because of 'ripples' in the output. >2. >Most image resampling algorithms actually are FIR filters, most of these >are low order low pass filters. Even linear interpolation is a low pass, >albeit not a very good one. >A perfekt low pass equivalent to your fft approach would be sin(x)/x >interpolation which is computationally quite expensive but a lot faster >than the FFT and gives exactly the same results. As I mentioned I used the FFT for other reasons, the main point is realizing that the normally used open source packages do NOT prevent aliasing, and you can fix that with a lowpass below half the new sample frequency before the resizing, you in fact 're-sample' the signal after all. >3. >Scaling and filtering can folded and performed in one step. This is true >for both approaches: FIR-filters and FFT. I would appreciate if you have a simple C or Verilog or whatever piece of code that I could look at. It is a very old webpage, but some people may still be using 1/2 D CVD, and for those it would be nice to have a fast alias free resizer. CVD (China Video Disk) is widely spread in the east. Regards Jan >Kolja Sulimma > >
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