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Hi all.
I'm more or less a beginner in using Xilinx tools and System.
Now I'm working with a Spartan 3E Evaluation Board to check the
feature and to start developing FW code.
Enviroment is EDK, I mean XPS, version 8.1.02i.
ISE 8.1.03i.
My questions:
1) In case of big application it is not possible just use
only BRAM. Anyway the ONLY way to fit the big application
into DDR RAM is just use a bootloader which, for esxample,
get the big applic. binary via UART (DCE port) and copy it
into RAM and then bootloader jump to RAM itself ?
I have notice it's possible set linker options for applications,
in particulary to decide about linker zone for every code type
are (.text, .data, and so on). Moreover it's possible seto linker
to DDR RAM area for each or all of these sections.
This feature is just useful only to create the application to be
linked
into RAM or there is a tip "to link & loading in automatic" our
big application in RAM? (Avoiding avery time the copy step into
RAM via UART port)
2) How much is really a "good performance cache" the which one created
inside BRAM block versus the other one possible created into DDR
RAM
via "cache linked Otion" in BSB wizard ?
Thanks in advance for any answers.
Cheers,
Alfre.
Article: 107776Alfre schrieb: > Hi all. > > I'm more or less a beginner in using Xilinx tools and System. > Now I'm working with a Spartan 3E Evaluation Board to check the > feature and to start developing FW code. > > Enviroment is EDK, I mean XPS, version 8.1.02i. > ISE 8.1.03i. > > My questions: > 1) In case of big application it is not possible just use > only BRAM. Anyway the ONLY way to fit the big application > into DDR RAM is just use a bootloader which, for esxample, > get the big applic. binary via UART (DCE port) and copy it > into RAM and then bootloader jump to RAM itself ? > I have notice it's possible set linker options for applications, > in particulary to decide about linker zone for every code type > are (.text, .data, and so on). Moreover it's possible seto linker > to DDR RAM area for each or all of these sections. > This feature is just useful only to create the application to be > linked into RAM or there is a tip "to link & loading in automatic" our > big application in RAM? (Avoiding avery time the copy step into > RAM via UART port) > > 2) How much is really a "good performance cache" the which one created > inside BRAM block versus the other one possible created into DDR > RAM > via "cache linked Otion" in BSB wizard ? > > Thanks in advance for any answers. > > Cheers, > > Alfre. 1) if your application is to be executed from any external memory then it is really obvious that the external memory can be loaded or programmed by some means. The only memory that is initialized when FPGA is configured is the BRAM block. you choices: a) use some sort of bootloader, to load over serial port, or maybe u-boot loading over network automatically b) use XMD to download the image(uses jtag and MDM), good for development c) have the application code strored in some sort of nonvolatile memory(ser or par flash mmc-sd card, CF card, etc), good when development is done and you need to always boot the same image d) you can convert the .BIT and .ELF to ACE and use ACE Player to load both the FPGA and external memory over jtag cable 2) the cache gives real performace hit. depends on application but can defenetly be more than 5 times the faster Antti http://xilant.comArticle: 107777
Mak schrieb: > Hi, > Can I use Block RAM for data storage in a system involving > micro-controller which writes into Block RAM as a buffer? I am bothered > about the timing as 8051 does not have data clock combination as is > required by block RAM. > Or Block RAM is just for local FPGA starage? yes, you can. I assume you are considering the BRAM to be used memory for an external 8051 MCU? You need to create some clock for the BRAM through and see that the timings are met. For first testing you can just use some onchip oscillator to supply some free running clock over 100Mhz to the BRAMs, so they would become sort of synched pseudo RAMs. The BRAMs would make multiply read and writes each 8051 cycle but should not bather as long as the addr-data are valid for writes, and the 8051 read is slow enough for at least 1 BRAM read to happen always before the 8051 latches read data. AnttiArticle: 107778
Joerg wrote: > fpga_toys@yahoo.com wrote: > > > > > >>Know what? What really bad typos indicate? Pretty clear, if someone > >>affords his or her resume that little attention to detail I assume it'll > >>be the same for a design. Can't use that. > > > > Or the person is dyslexic with a foriegn native tounge, language > > impaired, but with experience and genuis in design that can easily be > > offset by using good clerical assistant to help the designer with > > writing, editing, and other written language issues. > > > > Wouldn't you then expect that genius to be smart enough to have a friend > critique and correct their resume? Or at least click Tools -> Spell > Check? That ain't rocket science... We had one very bright but dyslexic engieer at Cambridge Instruments, who never really got the idea that it mattered how you spelled a word as long as what you wrote sounded right, so he used "their", "there" and "they're" as if they were interchangeable, and - while he appreciated the theory behind our complaints about his spelling, he never took us really seriously, because he couldn't imagine that we didn't hear the words printed on the page. I offered to spell check his written output on a number of occasions, but he never took me up on it. -- Bill Sloman, NijmegenArticle: 107779
jacko schrieb: > Frank Buss wrote: > > jacko wrote: > > > > > > > > http://indi.joox.net link to quartus II files > > > > This looks like a net list or something like this. I have only ISE WebPack > > installed and I don't know how to display it. Do you have a picture of it? > > i think ahdl custom to altera. there tool is web downloaded. could > notget the xilinx tool to download after 5 attempts. > > website more specific. > > the zip file is current project design files in quartus II version 6, > but still have to design instruction sequencing unit. thought of using > an 8 cycle simple instruction execution, for a very compact IP core. > also decided that modular forth in instancable blocks would be most > flexible. > > it is going to evolve as a 16n design, as all carry can happen along > multiple instances to make any 16*n word size, but i have to decide how > the program word width may or may not expand to the word size. > > i hope to get wishbone and avalon bus interfaces too, but this is not > my immediate priority. > > i intend a serial bus standard to allow connected multicore designs, > each core having 128KB memory. > > does anyone know how to export a quartus project as VHDL? > > cheesr > > jacko Jacko, you possible have to handconvert the AHDL to VHDL :( thats the reason I suggested using non-vendor HDL in the first place. AnttiArticle: 107780
zcsizmadia@gmail.com schrieb: > I've reversed engineer the CableServer communication with Impact and > written from scratch a brand new CableServer. Currently only Parallel > III cable is implemented, but new cables can be added very easily. I > will post the project on sourceforge.net next week. > > Antti wasn't really helpful to come up with a name for the project, so > it will be called "cblsrv" :) > > I've uninstalled windriver from Win32 and Impact seems to work without > it if only "cblsrv" is used. I guess the same is true for Linux as > well. > > Zoltan Sorry Zoltan, I didnt realize such help was expected from me :) AnttiArticle: 107781
"Joerg" <notthisjoergsch@removethispacbell.net> schreef in bericht news:D4LJg.5081$yO7.4612@newssvr14.news.prodigy.com... > Hello Martin, > >>> >>>>Know what? What really bad typos indicate? Pretty clear, if someone >>>>affords his or her resume that little attention to detail I assume it'll >>>>be the same for a design. Can't use that. >>> >>>Or the person is dyslexic with a foriegn native tounge, language >>>impaired, but with experience and genuis in design that can easily be >>>offset by using good clerical assistant to help the designer with >>>writing, editing, and other written language issues. >> >> hehe, I walked into the local language school, here in spain, having >> problems translating my CV. The average tranlator cannot comprehend >> technical terms like "Video Post Production facility engineer" >> > > That's a common misconception even among professional translators. They > think that you don't need to be an engineer to translate technical stuff. > The result is often close to the manuals that come with some Asian > consumer products, between funny and largely incomprehensible. I doubt if many of the Asian manuals are the work of professional translators at all. Not only are they funny/incomprehensible, but also full of spelling mistakes. Asian websites have the same problems. Always a flash intro to tell you have finally found the pot of gold, a large jpg as background that gives the impression there are all sorts of clickable menus which there aren't, a bible text about their company mission that makes them look better than Mother Theresa, and a shopping cart button that only pops up an email form. All that they do is cut & paste and change some pictures. -- Thanks, Frank. (remove 'q' and '.invalid' when replying by email) > > Ask one of your engineer friends to do it. Afterwards you could still have > it polished to top-notch Castellano but chances are they put some mistakes > back in. Happened to me when I did my own translation into Dutch (many > moons ago when I could properly speak it). The boss corrected some of the > not so well worded parts. Then the company gave it to an in-house pro who > is Dutch. Whoops, nearly all my not so well worded parts were back in :-) > > -- > Regards, Joerg > > http://www.analogconsultants.comArticle: 107782
Hello, I am using an Altera MAX3000A CPLD to make level conversion from 5V-TTL to 3.3V-TTL (and further jobs...). My problem is - I can't connect two bidirectional ports directly to get a bidirectional connection. I'm using Altera Quartus II, a direct connection produces an error message and a simple VHDL-block doesn't solve the problem, too. my VHDL-code is like: ENTITY ... port1 : INOUT STD_LOGIC; port2 : INOUT STD_LOGIC; ARCHITECTURE... port1 <= port2; port2 <= port1; How can I make a bidirectional connection between two bidirectional ports??? thanks, ManfredArticle: 107783
Manfred Balik schrieb: > Hello, > I am using an Altera MAX3000A CPLD to make level conversion from 5V-TTL to > 3.3V-TTL (and further jobs...). > My problem is - I can't connect two bidirectional ports directly to get a > bidirectional connection. > I'm using Altera Quartus II, a direct connection produces an error message > and a simple VHDL-block doesn't solve the problem, too. > my VHDL-code is like: > ENTITY ... > port1 : INOUT STD_LOGIC; > port2 : INOUT STD_LOGIC; > ARCHITECTURE... > port1 <= port2; > port2 <= port1; > > How can I make a bidirectional connection between two bidirectional ports??? > thanks, Manfred it's not possible. it would require an analog switching element being used to connect those 2 io pins. depending on the protocol that is used there may or may not be a solution that can be implemented in full digitial domain. AnttiArticle: 107784
Coregen report me: DEBUG[cmsg] - EJava Unzip Failure on v3.0.160.zip for D:\Xilinx\testCOREGEN\tmp\_cg\_bbxjava.util.zip.ZipException: Not enough disk space in path, D:\Xilinx\testCOREGEN\tmp\_cg\_bbx, to uncompress all files in ZIP/JAR file: c:\Xilinx\coregen\ip\xilinx\network\com\xilinx\ip\pci32_v3_160\fileset\v3.0.160.zip. DEBUG[cmsg] - CopyFilesetZip:: srcFileDir: v3.0.160 ERROR:coreutil - Failure to generate output products In D disk 35Gega free spase!!! What Coregen whant?Article: 107785
axa...@gmail.com schrieb: > Coregen report me: > > DEBUG[cmsg] - EJava Unzip Failure on v3.0.160.zip for > D:\Xilinx\testCOREGEN\tmp\_cg\_bbxjava.util.zip.ZipException: Not > enough disk space in path, D:\Xilinx\testCOREGEN\tmp\_cg\_bbx, to > uncompress all files in ZIP/JAR file: > c:\Xilinx\coregen\ip\xilinx\network\com\xilinx\ip\pci32_v3_160\fileset\v3.0.160.zip. > DEBUG[cmsg] - CopyFilesetZip:: srcFileDir: v3.0.160 > ERROR:coreutil - Failure to generate output products > > In D disk 35Gega free spase!!! What Coregen whant? make sure drive C has enough free space as well. the archives are sometimes uncompressed into default temp dir on C: AnttiArticle: 107786
I do it, but coregen report the same Antti =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0): > axa...@gmail.com schrieb: > > > Coregen report me: > > > > DEBUG[cmsg] - EJava Unzip Failure on v3.0.160.zip for > > D:\Xilinx\testCOREGEN\tmp\_cg\_bbxjava.util.zip.ZipException: Not > > enough disk space in path, D:\Xilinx\testCOREGEN\tmp\_cg\_bbx, to > > uncompress all files in ZIP/JAR file: > > c:\Xilinx\coregen\ip\xilinx\network\com\xilinx\ip\pci32_v3_160\fileset\= v3.0.160.zip. > > DEBUG[cmsg] - CopyFilesetZip:: srcFileDir: v3.0.160 > > ERROR:coreutil - Failure to generate output products > > > > In D disk 35Gega free spase!!! What Coregen whant? > > make sure drive C has enough free space as well. > the archives are sometimes uncompressed into default temp dir on C: >=20 > AnttiArticle: 107787
"Rick Lyons" <R.Lyons@_BOGUS_ieee.org> wrote in message news:44f77c53.25483000@news.sf.sbcglobal.net... > In my experience, HR people were like > Govt employees (I worked for the Fed > Govt for 15 years). One person out of five > does the useful work, and 4 people out of 5 > screw around for 6 hours a day playing on the > computer and gossiping on the phone to their > sister. IF ONLY they would bluddy well stick to that then all would be well (only the shareholders have a problem, but we did not get any options ... so - who cares). The above goes for government too BTW: The more they "work" the more the taxpayers will suffer!Article: 107788
and still: I has loocked the properties of file "c:\Xilinx\coregen\ip\xilinx\network\com\xilinx\ip\pci32_v3_160\fileset\v3.= 0=AD.160.zip" and see in bookmark "archive" Host OS - UNIX !!! But I use WindowsArticle: 107789
Thank you Antti, The faster clock from FPGA will decode the WR logic repetatively, which may cause multiple data writes to the BRAM. I could not understand what you meant by "The BRAMs would make multiply read and writes each 8051 cycle, but should not bather as long as the addr-data are valid for writes" My application involves writing the data block to memory and reading the RAM back using it for transmission. Antti wrote: > Mak schrieb: > > > Hi, > > Can I use Block RAM for data storage in a system involving > > micro-controller which writes into Block RAM as a buffer? I am bothered > > about the timing as 8051 does not have data clock combination as is > > required by block RAM. > > Or Block RAM is just for local FPGA starage? > > yes, you can. I assume you are considering the BRAM to be used memory > for an external 8051 MCU? You need to create some clock for the BRAM > through and see that the timings are met. For first testing you can > just use some onchip oscillator to supply some free running clock over > 100Mhz to the BRAMs, so they would become sort of synched pseudo RAMs. > The BRAMs would make multiply read and writes each 8051 cycle but > should not bather as long as the addr-data are valid for writes, and > the 8051 read is slow enough for at least 1 BRAM read to happen always > before the 8051 latches read data. > > AnttiArticle: 107790
Mak schrieb: > Thank you Antti, > The faster clock from FPGA will decode the WR logic repetatively, which > may cause multiple data writes to the BRAM. I could not understand what > you meant by "The BRAMs would make multiply read and writes each 8051 > cycle, but should not bather as long as the addr-data are valid for > writes" > > My application involves writing the data block to memory and reading > the RAM back using it for transmission. > > > > Antti wrote: > > Mak schrieb: > > > > > Hi, > > > Can I use Block RAM for data storage in a system involving > > > micro-controller which writes into Block RAM as a buffer? I am bothered > > > about the timing as 8051 does not have data clock combination as is > > > required by block RAM. > > > Or Block RAM is just for local FPGA starage? > > > > yes, you can. I assume you are considering the BRAM to be used memory > > for an external 8051 MCU? You need to create some clock for the BRAM > > through and see that the timings are met. For first testing you can > > just use some onchip oscillator to supply some free running clock over > > 100Mhz to the BRAMs, so they would become sort of synched pseudo RAMs. > > The BRAMs would make multiply read and writes each 8051 cycle but > > should not bather as long as the addr-data are valid for writes, and > > the 8051 read is slow enough for at least 1 BRAM read to happen always > > before the 8051 latches read data. > > > > Antti well as long as address and data are valid during all the time the WR is active then the multiply writes of the same data to same address would not matter. AnttiArticle: 107791
Oh that's right! Memory will be overwritten. Thank you. Antti wrote: > Mak schrieb: > > > Thank you Antti, > > The faster clock from FPGA will decode the WR logic repetatively, which > > may cause multiple data writes to the BRAM. I could not understand what > > you meant by "The BRAMs would make multiply read and writes each 8051 > > cycle, but should not bather as long as the addr-data are valid for > > writes" > > > > My application involves writing the data block to memory and reading > > the RAM back using it for transmission. > > > > > > > > Antti wrote: > > > Mak schrieb: > > > > > > > Hi, > > > > Can I use Block RAM for data storage in a system involving > > > > micro-controller which writes into Block RAM as a buffer? I am bothered > > > > about the timing as 8051 does not have data clock combination as is > > > > required by block RAM. > > > > Or Block RAM is just for local FPGA starage? > > > > > > yes, you can. I assume you are considering the BRAM to be used memory > > > for an external 8051 MCU? You need to create some clock for the BRAM > > > through and see that the timings are met. For first testing you can > > > just use some onchip oscillator to supply some free running clock over > > > 100Mhz to the BRAMs, so they would become sort of synched pseudo RAMs. > > > The BRAMs would make multiply read and writes each 8051 cycle but > > > should not bather as long as the addr-data are valid for writes, and > > > the 8051 read is slow enough for at least 1 BRAM read to happen always > > > before the 8051 latches read data. > > > > > > Antti > > well as long as address and data are valid during all the time the WR > is active then the multiply writes of the same data to same address > would not matter. > AnttiArticle: 107792
"Symon" <symon_brewer@hotmail.com> writes: > I'm not suggesting that decoupling at 3GHz is useful. In my opinion, any > decoupling at frequencies above a few hundred MHz is useless because of the > package impedance at these frequencies. and > To repeat myself, I don't care what the impedance is above a few hundred > MHz. This 'threadlet' starting with Martin's post is addressing mini-plane > resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz > now! :-) As I understand it, the reason you don't care above a few hundred MHz is because you are doing mini-planes? If you were doing whole board planes, then there may be problems above the "package frequency" due to the PCB radiating at a frequency which is not "well-decoupled" even at several hundred MHz. With a bigger plane, this is more likely. Or have I misunderstood? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 107793
I found a similar behaviour in the stand alone Xilinx Modelsim. There obviously is a window update problem. But the window has a right mouse function giving you the opportunity to update the window manually. Then the files are visible again.Article: 107794
Hi everyone, has anybody successfully synthesized the IEEE 1076-2006 libary, which includes a fixed-point implementation? As there is also a VHDL 93 compliant package and according to some Forum-Threads (http://www.velocityreviews.com/forums/t23681-xilinx-ise-type-real.html), especially the fixed-point part should compile with ISE 8.2i. Did anybody get it work? Thanks and Regards, PeterArticle: 107795
Manfred Balik wrote:
> Hello,
> I am using an Altera MAX3000A CPLD to make level conversion from 5V-TTL to
> 3.3V-TTL (and further jobs...).
> My problem is - I can't connect two bidirectional ports directly to get a
> bidirectional connection.
> I'm using Altera Quartus II, a direct connection produces an error message
> and a simple VHDL-block doesn't solve the problem, too.
> my VHDL-code is like:
> ENTITY ...
> port1 : INOUT STD_LOGIC;
> port2 : INOUT STD_LOGIC;
> ARCHITECTURE...
> port1 <= port2;
> port2 <= port1;
>
> How can I make a bidirectional connection between two bidirectional ports???
> thanks, Manfred
You need to put a bit more thought into what it is that you're really
trying to do. Let's say your code compiled and you now wanted to
instantate the component somewhere. That code would look like this...
U1 : entity work.Mans_Entity port map(
port1 => Sig1,
port2 => Sig2);
Where 'Sig1' and 'Sig2' are the 'two' busses or signals that you're
trying to connect. But in your code you implied (to me) that you'd
like to take whatever comes in on either port and map it over to the
other....which would then mean that logically 'Sig1' and 'Sig2' are the
same thing and not separate things (i.e. one is the 5V side, the other
is the 3.3V side)....which is a contradiction...which fundamentally is
why what you have isn't working.
What you probably need to add is the concept of an output enable for
both port1 and port2 and only drive the outputs when that output is
enabled...
port1 <= port2 when (port1_output_enable = '1') else 'Z';
KJ
Article: 107796I have long been irritated that some of the tools in ISE are quite sluggish in Linux. For example, suppose I run a synthesis job in the background with a nice value of 19. In theory, I should barely notice that program (unless I run out of memory) if I'm looking at the current design in the floorplanner or whatever. Unfortunately, that is not the case. This is caused by the fact that the tools call sched_yield() very often. I have been aware of this for quite some time but never bothered to do something about it. But it is actually quite simple to remedy this problem, just create a shared library containing a sched_yield that does nothing and use LD_PRELOAD to make sure that fpga_editor loads your shared library before libc is loaded. Now I can run fpga_editor with a synthesis in the background without any sluggishnes at all. Of course, I cannot guarantee that this will work for you, but it seems to work just fine for me :) /AndreasArticle: 107797
KJ schrieb: > Manfred Balik wrote: > > Hello, > > I am using an Altera MAX3000A CPLD to make level conversion from 5V-TTL to > > 3.3V-TTL (and further jobs...). > > My problem is - I can't connect two bidirectional ports directly to get a > > bidirectional connection. > > I'm using Altera Quartus II, a direct connection produces an error message > > and a simple VHDL-block doesn't solve the problem, too. > > my VHDL-code is like: > > ENTITY ... > > port1 : INOUT STD_LOGIC; > > port2 : INOUT STD_LOGIC; > > ARCHITECTURE... > > port1 <= port2; > > port2 <= port1; > > > > How can I make a bidirectional connection between two bidirectional ports??? > > thanks, Manfred > You need to put a bit more thought into what it is that you're really > trying to do. Let's say your code compiled and you now wanted to > instantate the component somewhere. That code would look like this... > > U1 : entity work.Mans_Entity port map( > port1 => Sig1, > port2 => Sig2); > > Where 'Sig1' and 'Sig2' are the 'two' busses or signals that you're > trying to connect. But in your code you implied (to me) that you'd > like to take whatever comes in on either port and map it over to the > other....which would then mean that logically 'Sig1' and 'Sig2' are the > same thing and not separate things (i.e. one is the 5V side, the other > is the 3.3V side)....which is a contradiction...which fundamentally is > why what you have isn't working. > > What you probably need to add is the concept of an output enable for > both port1 and port2 and only drive the outputs when that output is > enabled... > > port1 <= port2 when (port1_output_enable = '1') else 'Z'; > > KJ KJ bidir connections between to io's are sometimes possible also when no enable signal exists, see NXP's I2C extender as one example http://www.nxp.com/pip/PCA9515DP.html AnttiArticle: 107798
Hi while waiting for the www.lynuxworks.com V4Fx linux 2.6.x release I wonder if there is a quick fix to get shared libraries to work properly on ppc-2.4 I am using the 'simple' ppc linux build environment from the university queensland website and with that we are always getting SIGSEGV when attempting to unload an shared library with dlclose() AnttiArticle: 107799
Antti wrote: > > > > What you probably need to add is the concept of an output enable for > > both port1 and port2 and only drive the outputs when that output is > > enabled... > > > > port1 <= port2 when (port1_output_enable = '1') else 'Z'; > > > > KJ > > KJ > > bidir connections between to io's are sometimes possible also when > no enable signal exists, see NXP's I2C extender as one example > > http://www.nxp.com/pip/PCA9515DP.html Yes, and an even simpler example of a bi-directional connection between two I/Os with no enable or direction signal is a resistor. Since I wasn't quite sure exactly what the original poster was trying to do, I mentioned "What you probably need...." on the assumption that he is trying to come up with synthesizable code targetting some FPGA/CPLD or such (in which case I believe he will be needing the enable). If instead the poster was interested in a non-synthesizable simulation model that connects two things bi-directionally without a 'direction' or 'enable' signal (i.e. like a resistor or the part you linked) than he will be wanting a different code entirely. KJ
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