Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Frank Buss wrote: > Thanks. Looks like most of the time an arithmetic operation is executed > before "pop A", so I've used one bit for all instructions, which specifies > that a "pop A" is executed after the command to compress the code even > more: That sounds like a very good idea. > [example snipped] > Now it is 16 bytes long, just 1 byte more than the shortest code so far, > the 6502 code (it needed 15 bytes, not 13 as I wrote). I haven't actually written it down, but my impression is that in a 16 bit RISC processor like Jan Gray's gr0040 you could do it in 7 instructions (14 bytes). -- JecelArticle: 108001
Jecel wrote: > Frank Buss wrote: > > Thanks. Looks like most of the time an arithmetic operation is executed > > before "pop A", so I've used one bit for all instructions, which specifies > > that a "pop A" is executed after the command to compress the code even > > more: > > That sounds like a very good idea. > > > [example snipped] > > Now it is 16 bytes long, just 1 byte more than the shortest code so far, > > the 6502 code (it needed 15 bytes, not 13 as I wrote). > > I haven't actually written it down, but my impression is that in a 16 > bit RISC processor like Jan Gray's gr0040 you could do it in 7 > instructions (14 bytes). I am curious, what exactly is this code segment you are using as a benchmark? I saw the code earlier in this thread, but I don't understand the notation enough to know what it is doing. Is there some other code or a description so that I can see how other Forth CPUs might compare?Article: 108002
Luhan wrote: > > Jonathan Bromley wrote: > > On 3 Sep 2006 13:41:01 -0700, "PeteS" <PeterSmith1954@googlemail.com> > > wrote: > > > > >Bob Ferapples wrote: > > >To save time and bandwidth, I have boiled down the vast majority of > > >postings to this newsgroup into a quick and dirty little format that > > >can speed things up. > > > > A few years ago, someone posted a very funny take on this > > to sci.electronics.design. It listed a large number of > > spurious acronyms for use as responses to irritating > > querants - I can't find it now, but it was stuff like > > > > WWTYBYMHY - We Won't Tell You Because You Might Hurt Yourself > > > > (for use in response to people asking how to make a Tesla coil > > out of paper clips and a car battery - you know the kind of thing.) > > > > Anyone got a link to the original? > > -- > > Jonathan Bromley, Consultant > > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.bromley@MYCOMPANY.com > > http://www.MYCOMPANY.com > > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > I get irritated by those who post serious replies when the very content > of the question shows that the person has not a clue. "Hi, I need to > design a control system for a nuclear reactor. Can someone tell me > what a diode does?" > > Aaaarrrrggg! > > Luhan It depends on which way you hook it up. ;-) -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 108003
hi
not sure if looping is the best thing on a 16 bit word.
push byte 5 ; i=5
:loop dup popa ; i
@A byte ; (i) i
over ; i (i) i
push byte 6 ; 6 i (i) i
add popa ; (i) i
@A byte ; (6+i) (i) i
over ; (i) (6+i) i
!A byte ; (6+i) i
over popa ; (6+i) i
!A byte ; i
dec ; i-1
bcc byte :loop
drop ; empty stack
a similar thing in indi assembly, swapping two sets of 3*16 bit
locations with pointers on stack s would be
/.s=q /.q.r ; get 1st pointer to q
/.q.r /.q.r ; copied 3 16 bit words to r
/=q.r /.s=q ; save address for write over and get other address
/.q.s /.q.s ; get other 3 16 bit words to s
/.q.s /=q.s ; and save q on s
/.r=q /.s.r ; restore 1st address
/.s.q /.s.q ; overwrite 3 16 bit words
/.s.q /.r.s ; restore 2nd pointer in q
/.r.q /.r.q ; overwrite 2nd set
/.r.q /=p=p ; and a nop
which is 20 bytes (19 if nop not counted)
cheers
http://indi.joox.net
Article: 108004rickman wrote: > Jecel wrote: > > Frank Buss wrote: > > > Thanks. Looks like most of the time an arithmetic operation is executed > > > before "pop A", so I've used one bit for all instructions, which specifies > > > that a "pop A" is executed after the command to compress the code even > > > more: > > > > That sounds like a very good idea. > > > > > [example snipped] > > > Now it is 16 bytes long, just 1 byte more than the shortest code so far, > > > the 6502 code (it needed 15 bytes, not 13 as I wrote). > > > > I haven't actually written it down, but my impression is that in a 16 > > bit RISC processor like Jan Gray's gr0040 you could do it in 7 > > instructions (14 bytes). Ok, I found the sample program on the web page describing the instruction set. The font was so small I did not see it at first. Here is the code segment for the instruction set I came up with. I use a byte for each opcode, but LIT 6 BFLG ( set memory ops to byte ) LIT 0 ( D: ) ( R: SIZE ADDR ) LOOP: RDUP ( D: ) ( R: SIZE ADDR ADDR ) FETCH ( D: (ADDR) ) ( R: SIZE ADDR ) RDUP ( D: (ADDR) ) ( R: SIZE ADDR ADDR ) LIT 6 ( D: (ADDR) ) ( R: SIZE ADDR ADDR 6 ) RADRS ( D: (ADDR) ) ( R: SIZE ADDR ADDR+6 ) RDUP ( D: (ADDR) ) ( R: SIZE ADDR ADDR+6 ADDR+6 ) FETCH ( D: (ADDR) (ADDR+6) ) ( R: SIZE ADDR ADDR+6 ) SWAP ( D: (ADDR+6) (ADDR) ) ( R: SIZE ADDR ADDR+6 ) STORE ( D: (ADDR+6) ) ( R: SIZE ADDR ) STORP ( D: ) ( R: SIZE ADDR++ ) RCMP ( D: ) ( R: SIZE ADDR++ ) LOOP JMPC ( D: ) ( R: SIZE ADDR++ ) RDROP RDROP BFLG ( set memory ops back to word ) 19 bytes, with 6 of those outside the loop. So the loop would run 13 clock cycles in the current architecture. I have yet to port it to the newer type FPGAs which do not have an asynchronous read from the block RAMs. But I think it will still run with one clock per instruction including memory accesses. Any idea how large the new processor will be in an FPGA? I want to say mine was around 600 LUTs, IIRC. Any interest in comparing this to one of the proprietary cores such as microBlaze or NIOS2? I have wanted to see how efficient they would be implementing a Forth, but I have yet to work with one of them yet.Article: 108005
rickman wrote: > rickman wrote: > >>Jecel wrote: >> >>>Frank Buss wrote: >>> >>>>Thanks. Looks like most of the time an arithmetic operation is executed >>>>before "pop A", so I've used one bit for all instructions, which specifies >>>>that a "pop A" is executed after the command to compress the code even >>>>more: >>> >>>That sounds like a very good idea. >>> >>> >>>>[example snipped] >>>>Now it is 16 bytes long, just 1 byte more than the shortest code so far, >>>>the 6502 code (it needed 15 bytes, not 13 as I wrote). >>> >>>I haven't actually written it down, but my impression is that in a 16 >>>bit RISC processor like Jan Gray's gr0040 you could do it in 7 >>>instructions (14 bytes). > > > Ok, I found the sample program on the web page describing the > instruction set. The font was so small I did not see it at first. > > Here is the code segment for the instruction set I came up with. I use > a byte for each opcode, but > > LIT 6 > BFLG ( set memory ops to byte ) > LIT 0 ( D: ) ( R: SIZE ADDR ) > LOOP: RDUP ( D: ) ( R: SIZE ADDR ADDR ) > FETCH ( D: (ADDR) ) ( R: SIZE ADDR ) > RDUP ( D: (ADDR) ) ( R: SIZE ADDR ADDR ) > LIT 6 ( D: (ADDR) ) ( R: SIZE ADDR ADDR 6 ) > RADRS ( D: (ADDR) ) ( R: SIZE ADDR ADDR+6 ) > RDUP ( D: (ADDR) ) ( R: SIZE ADDR ADDR+6 ADDR+6 ) > FETCH ( D: (ADDR) (ADDR+6) ) ( R: SIZE ADDR ADDR+6 ) > SWAP ( D: (ADDR+6) (ADDR) ) ( R: SIZE ADDR ADDR+6 ) > STORE ( D: (ADDR+6) ) ( R: SIZE ADDR ) > STORP ( D: ) ( R: SIZE ADDR++ ) > RCMP ( D: ) ( R: SIZE ADDR++ ) > LOOP JMPC ( D: ) ( R: SIZE ADDR++ ) > RDROP > RDROP > BFLG ( set memory ops back to word ) I like the idea of mode-opcodes like this BFLG, that change the op-size. It is not common to mix opeand sizes in one function, but it is common to have to need BYTE and WORD fetches, for example. A mode change saves valuable opcode space. Main issue of such opcodes, is the interrupt-ability - they should probably have a hardware stack dedicated to 'keep track', so code like that above, can be interrupted. In a FPGA device, with 9 bit memory, that's probably easy to do: there's room to stack some mode state with return address Also, the opcode above appears to be a toggle ?, which could cause obscure bugs, if the routine has multiple exit points, and one forgets to toggle back, the next entry will be upside-down..... -jgArticle: 108006
Jim Granville wrote: > rickman wrote: > > Ok, I found the sample program on the web page describing the > > instruction set. The font was so small I did not see it at first. > > > > Here is the code segment for the instruction set I came up with. I use > > a byte for each opcode, but > > > > LIT 6 > > BFLG ( set memory ops to byte ) > > LIT 0 ( D: ) ( R: SIZE ADDR ) > > LOOP: RDUP ( D: ) ( R: SIZE ADDR ADDR ) > > FETCH ( D: (ADDR) ) ( R: SIZE ADDR ) > > RDUP ( D: (ADDR) ) ( R: SIZE ADDR ADDR ) > > LIT 6 ( D: (ADDR) ) ( R: SIZE ADDR ADDR 6 ) > > RADRS ( D: (ADDR) ) ( R: SIZE ADDR ADDR+6 ) > > RDUP ( D: (ADDR) ) ( R: SIZE ADDR ADDR+6 ADDR+6 ) > > FETCH ( D: (ADDR) (ADDR+6) ) ( R: SIZE ADDR ADDR+6 ) > > SWAP ( D: (ADDR+6) (ADDR) ) ( R: SIZE ADDR ADDR+6 ) > > STORE ( D: (ADDR+6) ) ( R: SIZE ADDR ) > > STORP ( D: ) ( R: SIZE ADDR++ ) > > RCMP ( D: ) ( R: SIZE ADDR++ ) > > LOOP JMPC ( D: ) ( R: SIZE ADDR++ ) > > RDROP > > RDROP > > BFLG ( set memory ops back to word ) > > I like the idea of mode-opcodes like this BFLG, that change the op-size. > It is not common to mix opeand sizes in one function, but it is common > to have to need BYTE and WORD fetches, for example. > A mode change saves valuable opcode space. > > Main issue of such opcodes, is the interrupt-ability - they should > probably have a hardware stack dedicated to 'keep track', so code like > that above, can be interrupted. In a FPGA device, with 9 bit memory, > that's probably easy to do: there's room to stack some mode state with > return address > > Also, the opcode above appears to be a toggle ?, which could cause > obscure bugs, if the routine has multiple exit points, and one forgets > to toggle back, the next entry will be upside-down..... Yes, it is a toggle rather than to have two instructions. But it toggles a bit in the PSW which can always be set directly using a read modify and write operations. It is 6 instructions that way. To have instructions to set and clear the Byte flag would require that I give back an instruction and I don't have anything I can spare, unless I make a significant change to the instruction set. The interrupt is not an issue for memory I/O size as long as you set the PSW bit on entry. I guess I could make that automatic on any interrupt. I hadn't thought of that, thanks. The PSW is automatically saved on the data stack while the return address is saved on the return stack. RETI restores them both while RET only does the return. I actually like my approach to the stacks. The way I handle literals and the CALL/JUMP instructions the return stack is more of an address register backed up by a stack while the data stack is pretty much just for data. It does Forth loops pretty efficiently. The overall design was a trade off between optimizing the instruction efficiency and keeping the processor size small, both to limit the resources used in an FPGA.Article: 108007
Anonymous schrieb: > I have a xilinx soc that is running 2.4 of the PPC linux fine. To run 2.6 is > it just a matter of copying the arch directory over to the 2.6 tree and > compiling? (Assuming I keep the configuration options the same.) > > Thanks, > Clark My bet is NO. you are of course welcome to try! but Xilinx has announced that www.lynuxworks.com is supposed to release 2.6.x base linux distributions soon(ppc end of August, microblaze and of 2006) , so I hope whatever there may be issues with 2.6.x are solved by then. on montavista the ppc linux is given as version 2.4.18, but there are also some comments about using the official ppc-linux tree (2.6.x) for V4 without problems. AnttiArticle: 108008
Hi, fl schrieb: > Maybe the "ability" is not correct or accurate. After synthesis, the > simulation should reflect the reality of FPGA. But, the initial value > of counter is "0000". After the first clock rising edge, its content is > "00X0". It seems the simulation does not know the correct value even it > did know the first value is "0000". I consider a design without a reset as bad for myself, but using Xilinx Fpga without a reset should be no problem. A 00X0 after the first rising edge with 0000 before the first rising edge indicates often a timing problem. Check timing analyses if your design achievs the applied clock frequency. Else check, where your X is comming from. bye ThomasArticle: 108009
Op Mon, 04 Sep 2006 06:15:02 +0200 schreef Michael A. Terrell <mike.terrell@earthlink.net>: > Luhan wrote: >> Jonathan Bromley wrote: >> > On 3 Sep 2006 13:41:01 -0700, "PeteS" <PeterSmith1954@googlemail.com> >> > wrote: >> > >Bob Ferapples wrote: >> > >To save time and bandwidth, I have boiled down the vast majority of >> > >postings to this newsgroup into a quick and dirty little format that >> > >can speed things up. >> >> I get irritated by those who post serious replies when the very content >> of the question shows that the person has not a clue. "Hi, I need to >> design a control system for a nuclear reactor. Can someone tell me >> what a diode does?" >> >> Aaaarrrrggg! >> >> Luhan > > > It depends on which way you hook it up. ;-) For people with the aforementioned skill level, that wouldn't matter much. It will probably say "poof!" and start to smell. Noobs who can learn from this experience, gradually build the skill to make the diode do absolutely nothing at all. -- Gemaakt met Opera's revolutionaire e-mailprogramma: http://www.opera.com/mail/Article: 108010
Synthesise PCI ver.3.160 for XC2VP7-6FG458 in Coregen (ISE 8.2 SP 2). When run compile, ISE genegate ERROR: Using target part "2vp7fg456-6". Mapping design into LUTs... ERROR:LIT:163 - Virtex PCILOGIC macro PCILOGIC symbol "PCI_CORE/PCI_LC/OUT_CE/MAGICBOX" (output signal=PCI_CORE/PCI_LC/OUT_CE/HARD_CE) is an invalid component in Virtex2 architecture. Errors found during logical drc. How to solve this problem? And why it appears? Thanks, Vasiliy ZamyatinArticle: 108011
And still: License status-Full (sourse available). Coregen Generate sourse files (which are including to project) in folder xxx\coregen\pci32_66\verilog\src\xpci ? Or I should including still other files? > Thanks, Vasiliy ZamyatinArticle: 108012
Weng Tianxiang schrieb: > ERROR:NgdBuild:604 - logical block > 'MG_x_A3/bram64_8_A/BU5' with type 'RAMB16' could not > be resolved. A pin name misspelling can cause this, > a missing edif or ngc file, or the misspelling of a type name. > Symbol 'RAMB16' is not supported in target 'virtex2'. > > I couldn't find any 'RAMB16' in my vhdl files. No, not in your VHDL. But the RAM block that you generated uses it internally. You will not get any VHDL code for the internals of the generated core. Just a netlist (edif or ngc) and a simulation model. Kolja SulimmaArticle: 108013
"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> wrote in message
news:8g7hf2plonk5885h87g565t08hu788srtm@4ax.com...
> On Fri, 1 Sep 2006 20:36:17 +0100, the renowned John Woodgate
> <jmw@jmwa.demon.co.uk> wrote:
>
>>In message <hsogf2tfqmq5dvchfq7qnlj6m6kcmuvs3m@4ax.com>, dated Fri, 1
>>Sep 2006, Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> writes
>>
>>>You had him executed by the Spanish Inquisition, didn't you, Mr. WOOD
>>>of GATE?
>>
>>Not me, it was one of the six other 'John Woodgate's in UK. In any case,
>>the result was unexpected.
>
> That the police actually *did* something? Yes, that would be
> unexpected.
>
>
> Best regards,
> Spehro Pefhany
_Nobody_ expects the Spanish Inquisition....
Regards
Ian
Article: 108014
"John Woodgate" <jmw@jmwa.demon.co.uk> wrote in message
news:$Otpf3X0VI+EFw8B@jmwa.demon.co.uk...
> In message <hn%Jg.4654$tU.648@newssvr21.news.prodigy.com>, dated Fri, 1
> Sep 2006, Joerg <notthisjoergsch@removethispacbell.net> writes
>
>>Has limits though: A neighbor told me that a guy showed up for an
>>interview with a T-shirt that read "People Suck". The interview ended
>>after about one second.
>
> Not sensible. You can get T-shirts with Schroedinger's Equation on them.
> They don't make you a physicist.
>
> You explore the 'inappropriate behaviour' only after you find that the guy
> knows what a Gilbert cell is and is used for. If s/he doesn't, you don't
> need to explore it.
I recall one of our engineers turned up in a thick roll-neck jersey his wife
had knitted for him, with the Fourier transform equation knitted in.
That's commitment ;-)
Regards
Ian
Article: 108015When I to "assign CFG[254:249] = 6'b001100;" instead of "assign CFG[254:249] = 6'b001000;" mapping error, and when I to "assign CFG[254:249] = 6'b001100;" instead of "assign CFG[254:249] = 6'b000100;" mapping succes. But I read in http://groups.google.ru/group/comp.arch.fpga/browse_thread/thread/fb6dbd4e603f41ae/d157626060716a3f?lnk=st&q=PCI_CORE%2FPCI_LC%2FOUT_CE%2FMAGICBOX&rnum=1#d157626060716a3f "Specifically, you need to set bit 251 (towards the end of the file) to logic one instead of logic zero." But it is a bit 252!!! Thanks, Vasiliy ZamyatinArticle: 108016
"Charlie Edmondson" <edmondson@ieee.org> wrote in message
news:44f8a24b$1@news.cadence.com...
<snip>
>>
> For my present position, I of course interviewed in a coat and tie, even
> though I knew the usual dress was casual. It is part of knowing what
> impression you need to leave. When I came back the next day for some
> follow up questions (mine, not theirs) I just wore a tie.
>
> Then, for my first day, I came in full three piece suit, mostly as a joke.
> I told my co-workers that I would dress a little more causually each day,
> so that by Friday I would be in t-shirt and cutoffs...
>
> Also on that first day was the companies annual meeting. Since I was new,
> and didn't have any other duties, the boss took me along. As we walked
> in, and sat down, several folks were wondering "Who's the new banker?"
> 8-)
>
> Charlie
One of our guys turned up in a suit on the first day. Unfortunately,
on the first day you get your photo taken for your security card.
We did warn the latest guys to join us not to wear a suit....
Regards
Ian
Article: 108017Don Seglio <cbayona@cox.net> writes: > I bought a Spartan-3 kit about a year ago and it came with V7.1i of > the software, I'm wondering what the kits are shipping with now? > > > On a related subject I bought a copy of MatLab for use with the Xilinx > software in creating DSP functions. I bought R14 which is compatible > with the software I now have, but they ran out of the old copies and > gave me a copy of the 2006a release instead, anyone have a clue if > that will work also? I don't think that Matlab 2006 will work with V7.1 of Xilinx. I use V7.1 of ISE with version 7.0.4 of Matlab. According to here: http://www.xilinx.com/products/software/sysgen/sw_req.htm MATLAB v7.1.0/Simulink v6.3 R14.3 Service Pack 3 MATLAB v7.2/Simulink v6.4 R2006a works with System generator 8.2 I assume it is Sysgen that you want to use? Also, note that Sysgen is not included with the S3 kit, it's a separate purchase, so you might be better using 8.2 of everything Xilinx, in which case it appears that your 2006a of Matlab will be OK.... Or you can download an older version of Matlab from The Mathworks I imagine... Does that help any? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 108018
Ian wrote: > I recall one of our engineers turned up in a thick roll-neck jersey his wife > had knitted for him, with the Fourier transform equation knitted in. > That's commitment ;-) No, that's just involved. In bacon and eggs, the chicken was involved but the pig was committed. Ciao, Peter K.Article: 108019
Hi, I wonder if anybody has a positive experience with Xilinx MIG1.6 (or earlier version) as a controller for DDR2 memory for Spartan3 family. Has anybody implemented successfully the controller on his project and verified it in the hardware? I would be glad to exchange any insights regarding this controller. thanks, Robert SzumowiczArticle: 108020
Manfred Balik schrieb: > Thanks to KJ and Antti for your prompt answers!!! > > I see - I will need a enable signal for each direction, because I want a > synthesizable code not a simulation (I thought this is easy, just a > connection :-( ). Actually you only need a direction signal if it is ok that one side is allways enabled. Make sure that all external drivers on a signal are enable when the CPLD is driving the signal. As a side note: You probably do not need a level converter at all. 3.3V TTL outputs are fully 5V TTL compliant because 5V TTL only requires the outputs to be driven to 2.4V. You only need protection against 5V signals damaging the 3.3V device. If the signals are driven by real TTL logic that means that in many cases you need no protection at all because TTL drivers are very week above 3.3V. In other cases a series resistor will do the job. Kolja SulimmaArticle: 108021
Boudewijn Dijkstra wrote: > Op Mon, 04 Sep 2006 06:15:02 +0200 schreef Michael A. Terrell > <mike.terrell@earthlink.net>: > > Luhan wrote: > >> Jonathan Bromley wrote: > >> > On 3 Sep 2006 13:41:01 -0700, "PeteS" <PeterSmith1954@googlemail.com> > >> > wrote: > >> > >Bob Ferapples wrote: > >> > >To save time and bandwidth, I have boiled down the vast majority of > >> > >postings to this newsgroup into a quick and dirty little format that > >> > >can speed things up. > >> > >> I get irritated by those who post serious replies when the very content > >> of the question shows that the person has not a clue. "Hi, I need to > >> design a control system for a nuclear reactor. Can someone tell me > >> what a diode does?" > >> > >> Aaaarrrrggg! > >> > >> Luhan > > > > > > It depends on which way you hook it up. ;-) > > For people with the aforementioned skill level, that wouldn't matter > much. It will probably say "poof!" and start to smell. Noobs who can > learn from this experience, gradually build the skill to make the diode do > absolutely nothing at all. The famous N.E.D. (noise emitting diode) - goes bang just one time! Luhan ;)Article: 108022
Hello,
i'm designing a onchip bus on a Virtex4 FPGA with one master and several
slave modules located in different asynchronous clock domains. The bus
consists of address, data and control signals. For synchronization i'm
using a full hanshake with a "Request" and "Acknowledge" signals. Now
it would be interessting to know if it's enough to synchronize only the
handshake signals as long as i make sure that the other bus signals
are stable for a certain amount of time or if i have to synchronize the
address and control signals as well. To illustrate the problem lets
assume the following situation:
There are 2 signals coming from the source clock domain CLK_S called
"SIG_A" and "REQUEST" and entering the destination clock domain CLK_D.
SIG_A is set a few clock cycles before REQUEST and then capt stable.
REQUEST is synchronized in the destination clock domain CLK_D with two
flip-flops. The synchronized signal is called REQUEST_SYNC. This signal
is used to decide if the signal SIG_A is stored in the clock domain
CLK_D. So the code would look like this
REG : process(CLK_D)
begin
if rising_edge(CLK_D) then
if REQUEST_SYNC='1' then
Q <= SIG_A;
end if;
end if;
end process REG;
Now what can happen if this code is implemented with a LUT and a
flip-flop? The LUT would have the following inputs "Q", "SIG_A" and
"REQUEST_SYNC" and the output goes to the flip_flop D-input. As long as
"REQUEST_SYNC" is "0" the output of the LUT should always be the "Q"
input and thereby creating a feedback with the flip-flop. This scheme is
used in Virtex4 FPGAs if one doesn't use the "Enable" input of the
flip-flops. But what happens if SIG_A switches while REQUEST_SYNC is "0"
? Will the output of the LUT alway be stable or will there be glitches?
The point is that the SIG_A will go through "illegal" signal levels when
going from a "0" to "1" or from "1" to "0". How will the LUT behave if
an input signals goes into a signal level between "0" and "1" during
switching time even if the signal is not selected active. Will "0" AND
"SIG_A" always produce a stable "0" at the output of the LUT? If not
then this scheme above can become metastable and one has to synchronize
all inputs to a module which can be very ressource consuming.
I would be glad to get some feedback!
Torsten
Article: 108023In article <1157378316.062766.317330@m79g2000cwm.googlegroups.com>, luhanis@yahoo.com says... > > Boudewijn Dijkstra wrote: > > Op Mon, 04 Sep 2006 06:15:02 +0200 schreef Michael A. Terrell > > <mike.terrell@earthlink.net>: > > > Luhan wrote: > > >> Jonathan Bromley wrote: > > >> > On 3 Sep 2006 13:41:01 -0700, "PeteS" <PeterSmith1954@googlemail.com> > > >> > wrote: > > >> > >Bob Ferapples wrote: > > >> > >To save time and bandwidth, I have boiled down the vast majority of > > >> > >postings to this newsgroup into a quick and dirty little format that > > >> > >can speed things up. > > >> > > >> I get irritated by those who post serious replies when the very content > > >> of the question shows that the person has not a clue. "Hi, I need to > > >> design a control system for a nuclear reactor. Can someone tell me > > >> what a diode does?" > > >> > > >> Aaaarrrrggg! > > >> > > >> Luhan > > > > > > > > > It depends on which way you hook it up. ;-) > > > > For people with the aforementioned skill level, that wouldn't matter > > much. It will probably say "poof!" and start to smell. Noobs who can > > learn from this experience, gradually build the skill to make the diode do > > absolutely nothing at all. > > The famous N.E.D. (noise emitting diode) - goes bang just one time! Dark Emitting Axial Diode. "It's DEAD, Jim." -- KeithArticle: 108024
>>>>> "Antti" == Antti <Antti.Lukats@xilant.com> writes: Hi, Antti> My bet is NO. you are of course welcome to try! It definately won't work. Antti> but Xilinx has announced that www.lynuxworks.com is supposed to release Antti> 2.6.x base linux distributions soon(ppc end of August, microblaze and Antti> of 2006) , so I hope whatever there may be issues with 2.6.x are solved Antti> by then. on montavista the ppc linux is given as version 2.4.18, but Antti> there are also some comments about using the official ppc-linux tree Antti> (2.6.x) for V4 without problems. Yes, V2P/V4 is nicely supported in the kernel (since Dec 2004). What is not included is device drivers for all the Xilix IP cores. -- Bye, Peter Korsgaard
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z