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aholtzma@gmail.com wrote: > Ray Andraka wrote: > >>The SRL16's are actually one of the most versatile blocks on the FPGA. >>You can use them for: >> > > *snip* > >>variable delays >>fixed delays >> >>The only one of these that is inferred by synthesis tools is the fixed >>delay, and that is also the least interesting out of all these. > > > Several years ago I managed to get Synplify 6.3 to infer SRL16s for a > variable delay. Frankly I was amazed it worked :) I can dig up the code > if anyone is interested. > > cheers, > aaron > Synplicity infers it as long as there are enough taps in the delay. It won't, for instance, infer an SRL16 for a variable delay with only 1,2,3 or 4 clocks delay, instead it infers flip-flops with a mux. Same template works fine with 9 taps.Article: 108251
Ray Andraka wrote: > Synplicity infers it as long as there are enough taps in the delay. It > won't, for instance, infer an SRL16 for a variable delay with only 1,2,3 > or 4 clocks delay, instead it infers flip-flops with a mux. Same > template works fine with 9 taps. While it's nice to have synthesis take care of all cases without concern, if you know you want to target an SRL (so you leave the reset out) why not make it longer so there's no problem inferring it "properly?" There's not a big loss in readability and the implementation is still clean. I personally think Synplify synthesis tools do an excellent job in the first 23 miles of the marathon but that last mile is where things trip up a bit. Very decent results all around but there are particular nuisances that - in my opinion - should be handled better. The overall quality is still better than other tools I've known.Article: 108252
In article <44FF7875.41BDAA86@earthlink.net>, mike.terrell@earthlink.net says... > Jim Stewart wrote: > > > > phaeton wrote: > > > > > Hi can someone please explain to me how to post to usenet? > > > > Um, you just did... > > > No, he used "Google Groups", which is spliced into usenet. Mike, it's a JOKE... Start at the beginning of the thread, and you'll get it... --Gene From blahbleh666@hotmail.com Wed Sep 06 22:10:08 2006 Path: newssvr25.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!news.glorb.com!hwmnpeer01.lga!news.highwinds-media.com!hw-filter.lga!newsfe02.lga.POSTED!53ab2750!not-for-mail From: "/dev/phaeton" <blahbleh666@hotmail.com> Subject: Re: Please help me with (insert task here) User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2006.09.07.05.10.01.908295@hotmail.com> Newsgroups: alt.engineering.electrical,sci.electronics.design,sci.electronics.basics,comp.arch.embedded,comp.arch.fpga References: <u5dmf2tsk1akel1fva3oo7gdhalcnk7cqe@4ax.com> <1157316061.131171.156790@m73g2000cwd.googlegroups.com> <1157384932.346990.260660@m73g2000cwd.googlegroups.com> <N%1Lg.21098$mY1.18604@bgtnsc05-news.ops.worldnet.att.net> <1157579221.974696.109440@e3g2000cwe.googlegroups.com> <0a-dnSqYWJwF3mLZnZ2dnUVZ_tGdnZ2d@omsoft.com> <44FF7875.41BDAA86@earthlink.net> <MPG.1f697007712a3b669897c4@newsgroups.comcast.net> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 28 X-Trace: nphhjmdkmllhpdkeijjdnojopddcmjimnohkgnejjjfmdmbpblelldckpacjmknklkmnobgmiglgpnbdcmlhjmmmhdfeahhpmofpmendkdkbjfbmhkmikhjjnhaaacflglbbcfickjagekga NNTP-Posting-Date: Wed, 06 Sep 2006 22:10:06 MST Date: Thu, 07 Sep 2006 00:10:08 -0500 Xref: prodigy.net alt.engineering.electrical:181577 sci.electronics.design:693143 sci.electronics.basics:253311 comp.arch.embedded:236241 comp.arch.fpga:119141 On Thu, 07 Sep 2006 01:54:24 -0400, Gene S. Berkowitz wrote: > In article <44FF7875.41BDAA86@earthlink.net>, mike.terrell@earthlink.net > says... >> Jim Stewart wrote: >> > >> > phaeton wrote: >> > >> > > Hi can someone please explain to me how to post to usenet? >> > >> > Um, you just did... >> >> >> No, he used "Google Groups", which is spliced into usenet. > > Mike, it's a JOKE... Start at the beginning of the thread, and you'll > get it... > > --Gene Sorry guys, I was just fooling around. Note that I'm no longer at work, and instead of using Google Groups, I'm at home using the Pan newsreader to read/post via my ISP's nntp server directly. :-) -phaetonArticle: 108253
"Gene S. Berkowitz" wrote: > > In article <44FF7875.41BDAA86@earthlink.net>, mike.terrell@earthlink.net > says... > > Jim Stewart wrote: > > > > > > phaeton wrote: > > > > > > > Hi can someone please explain to me how to post to usenet? > > > > > > Um, you just did... > > > > > > No, he used "Google Groups", which is spliced into usenet. > > Mike, it's a JOKE... Start at the beginning of the thread, and you'll > get it... > > --Gene What do you think " No, he used "Google Groups", which is spliced into usenet." is? ;-) Like WUBE radio in Cincinnati, ohio used to claim, "We're 50 KW of country music, transmitting from a splice in the high tension line!" -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 108254
"king" <frogkinger908@sina.com> wrote in message news:1157590436.111863.250840@d34g2000cwd.googlegroups.com... > hi, all > > I am developing a design with V4 LX100, and the project is large, which > usually cost me 2 hours to synthesis and PAR. It's more than I can bear > when debug it. > Is there any solutions to decrease the time cost? > Incremental design or planahead? > Can anybody with these experience figure out what should I do? > > Many thanks!! > > Regards > King > 1. Faster computer 2. Parallel Synthesis/Implementation on a cluster ---Matthew HicksArticle: 108255
Chao wrote: > I am trying to use I2C to configure TI TFP410 DVI transmitter. I put > differential clock input and VSYNC/HSYNC with the data. I suppose to get > 1600x1200 image on the monitor. Basically, I just want to show a simple > image and my hardware pins configuration is like below: > > DKEN (35) <--- GND > /PD (10) <--- GND > MSEN (11) <--- pull high > EDGE (09) <--- float with a serial resistor 1k > DE (02) <--- floating (since it should be ignored after I2C > configured it as disabled) > ISEL (13) <--- pull high > Vref (03) <--- VDD > > I believe this chip should work with only input VSYNC/HSYNC, +/-CLOCK > and 24bits DATA. Point me out if I am wrong. Thanks. Does the monitor display recognize the resolution but is all blank, or does it just display "no signal" ? What values did you write in the I2C registers ? SylvainArticle: 108256
rickman schrieb: > Each added bit toggles half as fast as the last. So the POWER for a > ripple carry counter is a POWER series Hihi, nice wording... > which is asymptotic to two bits > toggling all the time. That is not the same as independant. But it is close. Considering the error that power estimation has on sub 100nm CMOS the assumption of constant power is probably within the error bar starting from the second bit. Kolja SulimmaArticle: 108257
Hello I know what the e.g. "Fast IO" options do to the design and I have several of them constraining my ADC/DAC driving clocks as well as the input cells aquiring data from the ADCs and so on.. In the particlar case, it was a fast option of a DDR-cell. But the question ist not how to find an error in THIS design, but how one can quickly locate an error in general. As said, I found the misassignment by partly clicking on and off the options one ather the other, but this is not a fine way. Quartus should report this like "Assignment No 8 invalid", since the assignment ARE numbered. Just an Idea ...Article: 108258
Hi, Torsten Alt schrieb: > a 8 bit "=" needs at maximum 7 AND2 and 7 INV not 15 XOR2. And of course Your right, I was a bit fast in writing and slow in thinking ;). > is a compare larger 2^n-1 always for free since you only have to check > the n-bit. But this is a special case. In most cases your logic will > increase. But definitiv not all. Even a 4 bit > 9 uses less logic as 4 bit = 9 for most technologies. The logic may increase and may decrease. In most cases you don't even bother thinking about the size of your logic. And I guess you won't find 5 designers reading this news, with designs were you really had to squeeze each single gate (anyone else here with 100% resource usage? :). > SEU are a different story but if this can happen in your environment > then the counter is your smallest problem. :) Actually not. If you have to consider SEU, you usually have easy technologies to prevent Errors. But blocking counter and FSM are even worse in case of SEU, because you have to consider every possible value for each FF in case of multiple Upsets. Nevertheless, blocking counter and FSM are also thread to designs without considering SEU. > The point with complex designs and if-else paths are that i would simply > not use nested and long if-else paths cause you leave the implementation > of your design to the synthesis tools. They are pretty good if it comes > to standard design elements like comparators, counters, registers etc. > But they are pretty bad if it comes to synthesize VHDL code which is > written like C. Also your design will be prone to latches if you don't > take care about the path coverage. There are steps between C-Style code and simple designs using only straight forward code. For most of my designs I think afterwards I should have used more abstract possibilities of describing my code, instead of using relative low description levels. bye ThomasArticle: 108259
"phaeton" <blahbleh666@hotmail.com> wrote in message news:1157579221.974696.109440@e3g2000cwe.googlegroups.com... > Hi can someone please explain to me how to post to usenet? > See title. This was a joke (and quite a good one IMO)! JeezArticle: 108260
On 2006-09-07, Ray Andraka <ray@andraka.com> wrote: > It will help tremendously if the timing constraints are not pushing the > envelope for your design. For fun I just created some graphs that show this at http://www.da.isy.liu.se/~ehliar/stuff/place_and_route.html . The design is a floating point adder and the timing constraint is varied in steps of .05 ns between 1 and 10 nanoseconds. The runtime of par and the performance of the design is shown in the graphs. I do feel quite lucky that I have not yet created a design which takes 30 hours to route though :) /AndreasArticle: 108261
zcsizmadia@gmail.com <zcsizmadia@gmail.com> wrote: > Hi All, > Here is a open-source CableServer replacement,ent for Impact. Currently > Parallel III and Alter ByteBlaster are supported, but any 3rd party can > be implemented easily and can be used from Impact. > I've tested only Impact 8.2, if anybody has any problem with 7.1, > please let me know! > Impact and Xilinx CableServer communication are very pooly written. > There is no error recovery at all. If server stops, Impact GUI will > crash. To avoid this you must disconnect server from GUI using > Output/Cavble disconnect menu. > http://sourceforge.net/projects/xilprg > http://sourceforge.net/project/showfiles.php?group_id\ =175344&package_id=203209 Do you plan to merger xilprg and cblsrv? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 108262
On 6 Sep 2006 08:07:21 -0700, "Weng Tianxiang" <wtxwtx@gmail.com> wrote: > >Jozsef wrote: >> Hello, >> Try to recompile ALL sources which references to this package. I think >> about modelsim don't check & update referenced variables under >> compilation process in other sources. >> > I have some global constants shared among several modules, so I >> > set up a file to define a global package like the following: >> > >> > Package MG_x_Constant is ... >> > end MG_x_Constant; >> > This morning I found a problem: >> > when I changed DATA_BITS from 16 to 64, the ModelSim >> > sim window still shows constant DATABITS = 16 and it never changed, >> > even though I tried to delete the module from library and >> > re-compile it again. >I re-compiled every modules, but the constants in global package don't >change as if they were compiled once and never re-compiled again. > >I even deleted all work directory contents, recompile every modules, >but constants in the global package still don't change. I've just been through something similar. What happened in my case was: the package was compiled into a library, and included in my desigh via "Library/Use" statements. The library was mapped into a particular Modelsim directory, and this mapping was stored in modelsim.ini, in the directory where I was working on the package. Later, when I worked on the design, I found it using an OLD version of the package - because its mapping for that library was in a DIFFERENT modelsim.ini file (because the design was in a different place from the package). I got into this mess because this project was a combination of two older ones, and not a fresh start. This may not be your problem, but it's worth checking the library mapping paths in ALL relevant versions of modelsim.ini are what you expect. - BrianArticle: 108263
On 6 Sep 2006 09:51:29 -0700, "fl" <rxjwg98@gmail.com> wrote: > >alterauser wrote: >> Yuu must compile it, just like any other hdl file. >> >> Assuming you have a simulation wrapper for your design containing all >> IO parts of the FPGA which are not physically present, you just copy >> this wrapper into a new file and replace the complete design by the >> vho. >> >> Did you allready succed in compling and simulating the complete design, >> or parts of the design? > >In ISE, I can see tenths.xco file at the source tab. I can see >tenths.vhd and tenths.xco at the library tab. Although I cannot go on >the behavioral simulation, it can go with the post-translate >simulation. I don't know why the behavioral simulation cannot do. Thank >you. You need to compile tenths.vhd (in ModelSim) into the appropriate library (e.g. Work, unless there is an embedded configuration for Tenths in your top level design; like "For all: tenths Use mylib.tenths.myarch;" In which case, compile it into "mylib") If this still doesn't bind the component, check that the "tenths" entity in tenths.vhd matches the component declaration in your top level design. Modelsim will look for an entity with the same interface as your component declaration, e.g. number and names and types of ports. If there are any differences, it won't find a match. So fix the component declaration - or the entity, as appropriate. - BrianArticle: 108264
Hello,
in my design for a Spartan 3 4000 FG676-4 I have included a DCM that =
synthesizes a clock of 20 MHz out of external 100 MHz. I get the followi=
ng =
warning message from bitgen, version 7.1.04i -H.42
Running DRC.
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis =
performance
with the CLKFX and CLKFX180 outputs of the DCM comp
dcm_1/DCM_INST/dcm_1/DCM_INST, consult the device Interactive Data =
Sheet.
DRC detected 0 errors and 0 warnings.
Creating bit map...
WARNING:Bitgen:200 - CLKFX period 50000 ps is greater than maximum of =
41700 ps.
The minimum output frequency that is allowed according to the Spartan3 =
Datasheet and the DCM datasheet for Spartan3 are 18 MHz. Why do I get th=
is =
warning? 41700 ps are approx. 24 MHz.
I use the DCM as follows.
dcm_1 : dcm_100_20
PORT MAP (
CLKIN_IN =3D> CLK,
RST_IN =3D> reset,
CLKFX_OUT =3D> clk_20,
CLKIN_IBUFG_OUT =3D> clk_100,
CLK0_OUT =3D> OPEN,
LOCKED_OUT =3D> dcm_locked);
Thanks for your help or some hints in advance.
Ingmar Seifert
Article: 108265
Brian Drummond wrote:
> On 6 Sep 2006 08:07:21 -0700, "Weng Tianxiang" <wtxwtx@gmail.com> wrote:
>
> >
> >Jozsef wrote:
> >> Hello,
> >> Try to recompile ALL sources which references to this package. I think
> >> about modelsim don't check & update referenced variables under
> >> compilation process in other sources.
>
> >> > I have some global constants shared among several modules, so I
> >> > set up a file to define a global package like the following:
> >> >
> >> > Package MG_x_Constant is
> ...
> >> > end MG_x_Constant;
>
> >> > This morning I found a problem:
> >> > when I changed DATA_BITS from 16 to 64, the ModelSim
> >> > sim window still shows constant DATABITS = 16 and it never changed,
> >> > even though I tried to delete the module from library and
> >> > re-compile it again.
>
> >I re-compiled every modules, but the constants in global package don't
> >change as if they were compiled once and never re-compiled again.
> >
> >I even deleted all work directory contents, recompile every modules,
> >but constants in the global package still don't change.
>
> I've just been through something similar. What happened in my case was:
>
> the package was compiled into a library, and included in my desigh via
> "Library/Use" statements.
>
> The library was mapped into a particular Modelsim directory, and this
> mapping was stored in modelsim.ini, in the directory where I was working
> on the package.
>
> Later, when I worked on the design, I found it using an OLD version of
> the package - because its mapping for that library was in a DIFFERENT
> modelsim.ini file (because the design was in a different place from the
> package).
>
> I got into this mess because this project was a combination of two older
> ones, and not a fresh start.
>
> This may not be your problem, but it's worth checking the library
> mapping paths in ALL relevant versions of modelsim.ini are what you
> expect.
>
> - Brian
Hi,
Thank you everyone who gave me an answer.
The problem is resolved, I would like to share the lesson
I learned from this experience.
1. Original code:
DATABITS_16_32_64 <= 64 when DATABITS = 64 else
32 when DATABITS = 32 else
16; -- for data bits between 4-16
BlockRAM_A: for I in 0 to 2 generate
BlockRAM_0: BlockRAM
generic map (
DATABITS => DATABITS_16_32_64,
DEPTH => LEVEL_X)
port map (
...
);
end generate;
The problem is the following statement:
DATABITS_16_32_64 <= 64 when DATABITS = 64 else
32 when DATABITS = 32 else
16; -- for data bits between 4-16
I thought DATABITS_16_32_64 was assigned value before it was used
in generic map, but it is wrong.
Because block BlockRAM_A and DATABITS_16_32_64 assignment statement
are in concurrent area, DATABITS_16_32_64 in generate map (...)
doesn't use the value it is assigned to in the above statement.
When loading, ModelSim immediately reports
error for situation of DATABITS = 16 so that it seems to me that
global variable DATABITS doesn't change.
1. The answers everyone gave show unanimously that
the grammar I used in global file is right;
2. So I abandoned my original idea to search for other clues.
3. Luckyly, I found the error after one day rest about the problem.
The following is the right coding for the segment:
BlockRAM_A: for I in 0 to 2 generate
BlockRAM_64 : if DATABITS = 64 generate
BlockRAM_0: BlockRAM
generic map (
DATABITS => 64,
DEPTH => LEVEL_X)
port map (
...
);
end generate;
BlockRAM_64 : if DATABITS = 32 generate
BlockRAM_0: BlockRAM
generic map (
DATABITS => 32,
DEPTH => LEVEL_X)
port map (
...
);
end generate;
BlockRAM_64 : if(DATABITS /= 64 and DATABITS /= 32) generate
BlockRAM_0: BlockRAM
generic map (
DATABITS => 16,
DEPTH => LEVEL_X)
port map (
...
);
end generate;
end generate;
Thank you.
Weng
Article: 108266John_H wrote: > Ray Andraka wrote: > >> Synplicity infers it as long as there are enough taps in the delay. >> It won't, for instance, infer an SRL16 for a variable delay with only >> 1,2,3 or 4 clocks delay, instead it infers flip-flops with a mux. >> Same template works fine with 9 taps. > > > While it's nice to have synthesis take care of all cases without > concern, if you know you want to target an SRL (so you leave the reset > out) why not make it longer so there's no problem inferring it > "properly?" There's not a big loss in readability and the > implementation is still clean. > > I personally think Synplify synthesis tools do an excellent job in the > first 23 miles of the marathon but that last mile is where things trip > up a bit. Very decent results all around but there are particular > nuisances that - in my opinion - should be handled better. The overall > quality is still better than other tools I've known. Because the design needed a selection between 1 and 4 taps. It turned out to be considerably less work to just instantiate the SRL16 and be done with it rather than dealing with the pushing on a rope trying to get the tools to do what I wanted...at the cost of "portability" and an increase in simulation time. Instantiation of things like this gives the confidence that the tools get it right when you already have a specific design approach in mind.Article: 108267
where I can read about use PCI-core user application signals? I use this core in target mode. I whant to do standart microprocessor protocol from userside of PCI-core. thank, Vasiliy ZamyatinArticle: 108268
Andreas Ehliar wrote: > On 2006-09-07, Ray Andraka <ray@andraka.com> wrote: > >>It will help tremendously if the timing constraints are not pushing the >>envelope for your design. > > > For fun I just created some graphs that show this at > http://www.da.isy.liu.se/~ehliar/stuff/place_and_route.html . The design > is a floating point adder and the timing constraint is varied in > steps of .05 ns between 1 and 10 nanoseconds. The runtime of par and the > performance of the design is shown in the graphs. > > I do feel quite lucky that I have not yet created a design which takes > 30 hours to route though :) > > /Andreas When you get into the region where the propagation delay is getting close to the constraints, floorplanning can make a huge difference in the run time, as well as in the ability for the design to meet timing at all. A good floorplan essentially narrows the region on your second graph where the run time is greatly increased. The design I have that is running 30 hours is slowly decreasing in run time as I make adjustments to the floorplanning to improve the timing.Article: 108269
Hi, I am doing simulation with Altear FPGA Clone II. Now I need to do some multiply and fifo simulation, but I can't find the behavior model of these two functions because the .v file generated by software is only an "empty" file. Can anybody help me to find a simulation model of these two functions? thanks very much skyworldArticle: 108270
Weng Tianxiang: > 1. Original code: > DATABITS_16_32_64 <= 64 when DATABITS = 64 else > 32 when DATABITS = 32 else > 16; -- for data bits between 4-16 Why do you make DATABITS_16_32_64 a signal? All your problems derive from that. It looks like a constant to me. Something like this would evaluate before the generic maps: constant DATABITS_16_32_64: integer := (((DATABITS-1)/16)+1)*16; DATABITS 4 to 16 : DATABITS_16_32_64 is 16 DATABITS 32 : DATABITS_16_32_64 is 32 DATABITS 64 : DATABITS_16_32_64 is 64. Other cases irrelevant, I assume. -- jrArticle: 108271
Typically the Ignored Timing Assignments in the Timing Analysis report section will give you details as to which signals are generating the warning. You can also right click on a signal within this report and choose Locate / Locate In Assignment Editor. I've never had any difficulty finding a signal that had a timing parameter which Quartus was ignoring. alterauser wrote: > Hello > > I know what the e.g. "Fast IO" options do to the design and I have > several of them constraining my ADC/DAC driving clocks as well as the > input cells aquiring data from the ADCs and so on.. > > In the particlar case, it was a fast option of a DDR-cell. > > But the question ist not how to find an error in THIS design, but how > one can quickly locate an error in general. > > As said, I found the misassignment by partly clicking on and off the > options one ather the other, but this is not a fine way. Quartus should > report this like "Assignment No 8 invalid", since the assignment ARE > numbered. > > Just an Idea ...Article: 108272
jr wrote: > Weng Tianxiang: > > > > 1. Original code: > > DATABITS_16_32_64 <= 64 when DATABITS = 64 else > > 32 when DATABITS = 32 else > > 16; -- for data bits between 4-16 > > > Why do you make DATABITS_16_32_64 a signal? All your problems derive from > that. It looks like a constant to me. > > Something like this would evaluate before the generic maps: > constant DATABITS_16_32_64: integer := (((DATABITS-1)/16)+1)*16; > > DATABITS 4 to 16 : DATABITS_16_32_64 is 16 > DATABITS 32 : DATABITS_16_32_64 is 32 > DATABITS 64 : DATABITS_16_32_64 is 64. > > Other cases irrelevant, I assume. > > -- > jr Hi Jr, Wow! Wonderful !!! Your answer is very clever and absolute better than mine. I will use your code immediately without any conditions. I learned a trick from you. Thank you very much. WengArticle: 108273
I don't know yet. The CableServer protocol is really close to svf format, so to implement the different device program/erase/read functions should be easy. If people will add patches to cblsrv and will support a lots of different 3rd party cables, then probably yes. I think there could be a cblhost project with a built in cblsrv, so on alocal machine you don't have to start 2 applications, and still can connect to a remote cblsrv. But right now probably not. Unfortunately I have only 2 kinds of programmer cable (Par III, and Digilent USB JTAG), so I wait for other people to make patches for their loved cables :) Zoltan Uwe Bonnes wrote: > zcsizmadia@gmail.com <zcsizmadia@gmail.com> wrote: > > Hi All, > > > Here is a open-source CableServer replacement,ent for Impact. Currently > > Parallel III and Alter ByteBlaster are supported, but any 3rd party can > > be implemented easily and can be used from Impact. > > > I've tested only Impact 8.2, if anybody has any problem with 7.1, > > please let me know! > > > Impact and Xilinx CableServer communication are very pooly written. > > There is no error recovery at all. If server stops, Impact GUI will > > crash. To avoid this you must disconnect server from GUI using > > Output/Cavble disconnect menu. > > > http://sourceforge.net/projects/xilprg > > http://sourceforge.net/project/showfiles.php?group_id\ > =175344&package_id=203209 > > Do you plan to merger xilprg and cblsrv? > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 108274
king wrote: > I am developing a design with V4 LX100, and the project is large, which > usually cost me 2 hours to synthesis and PAR. If synthesis consumes a lot of this time, synthesise each component alone, save the results (the netlists) and read the netlists during synthesis of the complete design. Ralf
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