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"Antti Lukats" <antti@case2000.com> schrieb im Newsbeitrag news:80a3aea5.0305270412.307530aa@posting.google.com... > Hi > > latest Xilinx iMpact doesnt seem to support the old style Parallel III > cable any more, and it seems there is no way to get the bitstream > into Spartan Hello made some tests using iMPACT, version ISE 5.2.01i using Parallel cable III (DLC5), worked fine in batch mode and worked fine using Impact GUI interface - could not find a bug ... What version of iMPACT do You use ??? best regards Peter Seng, SENG digitale Systeme GmbHArticle: 56026
I am finding JTAG to be a major hassle to try to use for both debug and
production boundary scan. Seems there are conflicting requirements
which the two camps are not generally interested in dealing with.
The biggest problem is the fact that a lot of debugger tools don't like
having anything extra in the scan path. I have never gotten a clear
answer from TI about this on their DSPs. They have lots of app notes
telling you how to do it, the software has hooks for describing the
other devices, but support tells me not to try! I have not looked into
the issue with the ARM tools yet.
My design will have three separate voltage sections where the first
turns on/off the second and the second controls the third. So I am
using a separate JTAG chain for each section. The first will have just
a small CPLD. The second will have an ARM MCU and a large CPLD. The
third section will have the DSP and an FPGA. The DSP and FPGA will be
daisy chained, two jumpers can be used to isolate the DSP for debug.
The ARM and the CPLD will also be daisy chained. I am thinking about
using a combination of resistors and jumpers to try to minimize the
number and size of the jumpers (very, very small, crowded board).
+-----+ +------+
TDO ---+---| ARM |--+--/\/\/-+--| CPLD |-----/\/\/---+-- TDI
| +-----+ | | +------+ |
| | | | | |
| | +--------)------)-----------0 0--+
| | J1 | | J2
+------)---------0 0--+ |
| |
| |
TRSTarm--/\/\/-+ TMScpld--/\/\---+
| |
o o
J3 J4
o o
| |
V V
I figure that a 1K resistor driving a 10 pF load will create a 10 nS
(roughly) rise time. That should not create a problem with the 10 MHz
clocks typically found on JTAG. Anyone know if this will be a problem?
The stubs should all be pretty short since the entire circuit is only
about two or three inches long.
I have also considered running all the JTAG through a single device
which will act as a JTAG "roundtable". But I really don't want to add
yet another chip to the board if I can help it, plus the signal routing
gets a bit long. I might be able to use the large CPLD for this, but it
is in the "far" corner of the board from the rest of the JTAG.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 56027Ed Stevens wrote: >Thanks for the reply its been very helpful. > >Maybe a SpartanII is the way to go then. As I live in the UK its not really >worth sending boards backwards and forwards due to the postage / custom's >charges. I may just purchase the board from www.burched.com. > >Do you know if the XILINX Student software places any restrictions on the >VHDL for the Spartan 2 FPGA's? For example code size etc. > The software will compile all Spartan II devices with no limitations. Steve > >"Spam Hater" <spam_hater_7@email.com> wrote in message >news:ap07dvg9qje6mugq6np508863shimgjqiu@4ax.com... > > >>I have two answers (opinions) >> >>1) It is not possible. The contract between Xilinx and the synthesis >>vendor was terminated over a year ago. There is NO HDL software >>support for this device from Xilinx. See if Digilent will trade the >>board for a SpartanII board. >> >>2) The software is good, but the board is useless. All it has is the >>chip on a PCB; no oscillator, stake pins for I/O, and not even a >>voltage regulator. (I was going to make an expansion for mine, but >>decided that getting a different board would be cheaper.) >> >>$.02, >>SH7 >> >>PS: Take a look at Tony's products: www.burched.com >> >> >>On Tue, 27 May 2003 12:54:38 -0700, "Ed Stevens" >><ed@stevens8436.fslife.co.uk> wrote: >> >> >> >>>Hi everyone, >>> >>>I have 2 questions: >>> >>>For the past few weeks I've been trying to get started with VHDL and >>> >>> >FPGA's. > > >>>I've purchased a Spartan board from Digilent and I've also purchased the >>>Student software from XILINX. The problem im having is when I load the >>>XILINX software and select the Spartan device it won't allow me to select >>> >>> >a > > >>>VHDL design flow, it only allows EDIF. If I select a Spartan2 device it >>>will allow VHDL. Does anyone know if its possible to get the XILINX >>> >>> >Student > > >>>software to work with a Spartan in VHDL? >>> >>>My second question is: Does anyone have any opinions on the Cypress >>> >>> >Delta39K > > >>>CPLD Evaluation Board? Im thinking of buying it so I can implement a >>>Digital Phase Locked Loop on it, in VHDL. Would it be capable of doing >>>this? It appeals to me because it comes with the Cypress Warp VHDL >>>software, is this software any good? >>> >>>Thanks for any help, >>> >>> >>> > > > >Article: 56028
"Steve Casselman" <sc_nospam@vcc.com> wrote in message news:<S1tza.2434$kp2.56670410@newssvr21.news.prodigy.com>... > There is really no difference with your description and what happens with a > FPGA. You write a behavior and this is turned into low level programming > bits. These bits are then loaded into an electronic system in such a fashion > that your behavior is implemented. Believe me the FPGA is just as much > pre-defined hardware as is a processor. You can't change the transistors on > the die. The fact that the jargon and methods of hardware design was first > used to program them does not make FPGAs any less of a programmable device. > > It is all about the definition. > Programming: > Writing a behavior for a system. > > Are you programming when you write Verilog or VHDL? I think so. > > I could write a compiler that would take Verilog or VHDL and run it on a > processor. Doesn't this make it software? I can take C code and run it on a > FPGA. When did I stop writing software? What Verilog and VHDL don't have is, > the ability to describe dynamic processes that allow for the creation of > logic and interconnection. In the C/processor world I can use the resources > (mainly memory) in the system any way I want any time I want. I can alloc > memory or create a pipe to something or call on other precompiled units to > be loaded. I can run subroutines and even create object code on the fly. > You can do the same things with FPGAs it's just not easy. When FPGAs are > designed that do things like fetch their own configurations, at a time other > than boot time, then it will be easier to write C/C++ compilers for them. > > It's just a matter of time.... > > Steve I don't classify an FPGA's configuration bitstream as software because the bitstream is not a Turing Complete language. Verilog, VHDL, Confluence, etc., are complete languages. But synthesis translates these languages into a language that is not complete. This differs significantly from software compilation; the resulting assembly/machine code is still a Turing complete language. Of course, as you alluded to, once an FPGA can perform "self" reconfiguration, this changes everything. -- Tom Hawkins Launchbird Design Systems, Inc. 952-200-3790 tom1@launchbird.com http://www.launchbird.com/Article: 56029
It depends on what control you have over the "other side". ( you wrote "say" 8B10B...) If you can stutter the transmitter, making it send every byte twice, then you have 600 Mbps, and you are in business without any extras. Maybe too crude a suggestion... :-) Peter Alfke, Xilinx Ed Stevens wrote: > > Hi Kevin, > > Im not sure if its what your looking for but the website www.usb.org has a > document which describes how to extract the clock from an NRZI signal. It > includes a state machine. The document is called siewp.pdf. > > "Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message > news:JAPxa.892089$F1.111144@sccrnsc04... > > Is there a good way to do clock recovery (from, say, an 8B/10B data > stream) > > on a 300Mbps data using a Xilinx without the use of any external PLL or > > analog components? > > -Kevin > > > >Article: 56030
Hi everyone, I have 2 questions: For the past few weeks I've been trying to get started with VHDL and FPGA's. I've purchased a Spartan board from Digilent and I've also purchased the Student software from XILINX. The problem im having is when I load the XILINX software and select the Spartan device it won't allow me to select a VHDL design flow, it only allows EDIF. If I select a Spartan2 device it will allow VHDL. Does anyone know if its possible to get the XILINX Student software to work with a Spartan in VHDL? My second question is: Does anyone have any opinions on the Cypress Delta39K CPLD Evaluation Board? Im thinking of buying it so I can implement a Digital Phase Locked Loop on it, in VHDL. Would it be capable of doing this? It appeals to me because it comes with the Cypress Warp VHDL software, is this software any good? Thanks for any help,Article: 56032
"Patrik Eriksson" <patrik.eriksson@netinsight.net> wrote in message news:3ED363FF.7090708@netinsight.net... > Hi > > I have a design where i have to multiply a 19.44MHz clock signal by > four. I have tried to use a DCM. I connect my 19.44MHz signal to CLKIN > and uses the CLKFX output as my new 77.76MHz clock. No other > input/outputs are used. The 19.44MHz source is a crystal oscillator. > > The CLK_PERIOD attribute is set to 51.44 ns > > When I have downloaded this to my prototype board the DCM doesn't lock. > > What can be wrong? Maybe CLKIN isn't fast enough. You don't say what FPGA you're using, but from the Xilinx docs: "The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade (see The Programmable Logic Data Book for the most current values). " I seem to recall this being 25MHz for some parts. Cheers, JonB > -- > Patrik Eriksson | patrik.eriksson@netinsight.net > Net Insight AB | phone: +46 8 685 04 89 > Västberga Allé 9 | fax: +46 8 685 04 20 > SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net >Article: 56033
Hi Kevin, Im not sure if its what your looking for but the website www.usb.org has a document which describes how to extract the clock from an NRZI signal. It includes a state machine. The document is called siewp.pdf. "Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message news:JAPxa.892089$F1.111144@sccrnsc04... > Is there a good way to do clock recovery (from, say, an 8B/10B data stream) > on a 300Mbps data using a Xilinx without the use of any external PLL or > analog components? > -Kevin > >Article: 56034
Jon, The DCM CLKFX feature works down to a 1 MHz input frequency (as long as the output being synthesized is greater than 24 MHz). Note that you can not use "sync to DLL" (ie connect CLK0 to CLKFB) in this mode (DFS only mode). Austin Jon Beniston wrote: > > "Patrik Eriksson" <patrik.eriksson@netinsight.net> wrote in message > news:3ED363FF.7090708@netinsight.net... > > Hi > > > > I have a design where i have to multiply a 19.44MHz clock signal by > > four. I have tried to use a DCM. I connect my 19.44MHz signal to CLKIN > > and uses the CLKFX output as my new 77.76MHz clock. No other > > input/outputs are used. The 19.44MHz source is a crystal oscillator. > > > > The CLK_PERIOD attribute is set to 51.44 ns > > > > When I have downloaded this to my prototype board the DCM doesn't lock. > > > > What can be wrong? > > Maybe CLKIN isn't fast enough. You don't say what FPGA you're using, but > from the Xilinx docs: > > "The frequency of the clock signal at the CLKIN input must be in a specific > range depending on speed grade (see The Programmable Logic Data Book for the > most current values). " > > I seem to recall this being 25MHz for some parts. > > Cheers, > JonB > > > -- > > Patrik Eriksson | patrik.eriksson@netinsight.net > > Net Insight AB | phone: +46 8 685 04 89 > > Västberga Allé 9 | fax: +46 8 685 04 20 > > SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net > >Article: 56035
Hi, I'm looking to use dynamic reconfiguration of arithmetic units.For example something like at time t=t0,a particular sequence of operations say ADD,SUB,MULtiply(ASM) should be done but later depending upon some conditions at run-time the same sequence must be changed to say MSA(MUL,SUB,ADD).Any pointers/references on how to design a control unit to do the same? 2)Also can I use RTR to reuse any common hardware(like for example when reconfiguring from a fixed point unit adder and a floating point adder unit) while reconfiguring and thus minimize the reconfig time. Your help in this regard would be appreciated. Thanks, SriramArticle: 56036
"Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message news:bb027d$9os$1@news8.svr.pol.co.uk... > Thanks for the reply its been very helpful. > > Maybe a SpartanII is the way to go then. As I live in the UK its not really > worth sending boards backwards and forwards due to the postage / custom's > charges. I may just purchase the board from www.burched.com. > Also make sure you check out www.xess.com (I have board from both xess and burched) I think the xs50 is a nice lowcost board to learn on. RalphArticle: 56037
"Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message news:3ED2E125.8010402@neurophys.wisc.edu... > rickman wrote: > > The short stubs are important, and the traces shouldn't have any sharp > angles - you want a really clean signal all around. I assume you've got > ground planes and not a 2 layer board? That'll help a lot too. Why no sharp angles? BrettArticle: 56038
All versions of iMPACT support the Parallel Cable III. All versions of iMPACT support the SpartanII family. If you could give some indication of the error message you see or the log messages displayed then that might help isolate the problem. Thanks. Antti Lukats wrote: >Hi > >latest Xilinx iMpact doesnt seem to support the old style Parallel III >cable any more, and it seems there is no way to get the bitstream >into Spartan - the iMpact generated STAPL file does not work with JAM >player 2.3 gives bound error. > >We just received some Spartan II evaluation boards only to find out that >there are no means to get them configured. > >any good advice? >download software that takes the .bit and supports parallel cable III? >or a hint where to find STAPL player that doesnt get upset on xilinx >generated files? > >tnx > >Article: 56039
Mike Rosing wrote:
> rickman wrote:
>
>> I am finding JTAG to be a major hassle to try to use for both debug and
>> production boundary scan. Seems there are conflicting requirements
>> which the two camps are not generally interested in dealing with.
>> The biggest problem is the fact that a lot of debugger tools don't like
>> having anything extra in the scan path. I have never gotten a clear
>> answer from TI about this on their DSPs. They have lots of app notes
>> telling you how to do it, the software has hooks for describing the
>> other devices, but support tells me not to try! I have not looked into
>> the issue with the ARM tools yet.
>
>
> I can understand why. It's a pain in the butt to do it right. But you'd
> definitly expect TI to be able to deal with it.
>
>> My design will have three separate voltage sections where the first
>> turns on/off the second and the second controls the third. So I am
>> using a separate JTAG chain for each section. The first will have just
>> a small CPLD. The second will have an ARM MCU and a large CPLD. The
>> third section will have the DSP and an FPGA. The DSP and FPGA will be
>> daisy chained, two jumpers can be used to isolate the DSP for debug.
>> The ARM and the CPLD will also be daisy chained. I am thinking about
>> using a combination of resistors and jumpers to try to minimize the
>> number and size of the jumpers (very, very small, crowded board).
>>
>> +-----+ +------+
>> TDO ---+---| ARM |--+--/\/\/-+--| CPLD |-----/\/\/---+-- TDI
>> | +-----+ | | +------+ |
>> | | | | | |
>> | | +--------)------)-----------0 0--+
>> | | J1 | | J2
>> +------)---------0 0--+ |
>> | |
>> | |
>> TRSTarm--/\/\/-+ TMScpld--/\/\---+
>> | |
>> o o
>> J3 J4
>> o o
>> | |
>> V V
>>
>> I figure that a 1K resistor driving a 10 pF load will create a 10 nS
>> (roughly) rise time. That should not create a problem with the 10 MHz
>> clocks typically found on JTAG. Anyone know if this will be a problem?
>> The stubs should all be pretty short since the entire circuit is only
>> about two or three inches long.
>
>
> The short stubs are important, and the traces shouldn't have any sharp
> angles - you want a really clean signal all around. I assume you've got
> ground planes and not a 2 layer board? That'll help a lot too.
>
>> I have also considered running all the JTAG through a single device
>> which will act as a JTAG "roundtable". But I really don't want to add
>> yet another chip to the board if I can help it, plus the signal routing
>> gets a bit long. I might be able to use the large CPLD for this, but it
>> is in the "far" corner of the board from the rest of the JTAG.
>
>
> Jumpers should work just fine. If you can put multiple jtag headers next
> to each part that'd work great too, but it also takes up more space.
>
> Debuggers don't do boundary scan for reason - it's hard enough to make
> the debugger work! But I'd really like to know how many people would
> buy a combined device. I've thought about it, but it just seems like
> the market is too small and the effort too large.
>
> Patience, persistence, truth,
> Dr. mike
>
oops, I thought your resistors were terminal resistor ... and I think
your shem tdo is the conventional JTAG tdi input signal.
For your JTAG switch signal implementation, I would prefer something like :
tms ->------------------------------------
tck ->------------------------------------
tdo -<-----+---..-----Ĥ ARM Ĥ----------ĤCPLDĤ-------
Ĥ J1 Ĥ Ĥ
+---..-----------------+ Ĥ
J2 : J3 : J4
Ĥ Ĥ
tdi ->----------------------------------------------
Becomes very close to your shem replacing your 1K resistor by 0 ohm or
oo ohm (oo = infinit) or by a SMD jumper .
SVF is for serial vector formal => a nice format to describe a jtag
chain (have nice advantages for the config and download over JTAG and
assembly board test, but a little bit NOT apropriate for debug).
Amontec Team is actually working on a low cost universal JTAG solution
based SVF format and over the USB1. I just worry about the TI svf support!
Regards
Laurent
www.amontec.com
Article: 56040Allan Herriman wrote: > > On Tue, 27 May 2003 12:15:29 -0400, rickman <spamgoeshere4@yahoo.com> > wrote: > > >Jim Granville wrote: > >> > >> Imagine a ((RTC+NE555+4060+4093+22V10) * many), with the wide 1.65-5.5V > >> Vcc of TinyLogic and you get the target I envisage. > >> Would end up as widely used as EEPROMS :) > > > >This is largely what I am going to suggest to Semtech. Their MicroBuddy > >is a very good start down that path. They just need to tweek some of > >the specs and add the programmable logic. I am not sure what the 4093 > >is, but I think the 4060 is a counter chain, no? Yes, XTAL Osc + Ripple Counter block. > The MicroBuddy has a > >FLL running from the watch crystal which may do what you want with the > >555 and 4060. > > The 4093 is a quad nand schmitt trigger. > > I think this dream part would be easier to use if it had schmitt > inputs, with guaranteed min and max hysteresis and threshold voltages. Of course - _and_ designed for low linear mode currents. - ( plus optional Rail-Rail comparitors, with inbuilt mV Hyst ~LM393 ) > (No doubt Peter A. will point out his app note that shows how to use > "spare" pins and some resistors to make a schmitt input. But I > usually find I need a high input impedance (or can't spare the pins), > and it's easier to put a '14 or '132 on the board.) Hyst IS appearing on newer PLD offerings, either as an IP option, or always enabled. > > Regards, > Allan. > > >Since this chis is in a 3x3 QFN, if it had a higher freq range on the > >FLL, I would use it as clock generators scattered around my board. > > > >I don't know much about designing PLD chips, but it would seem to me > >that there is a market for very low power PLDs. While looking at > >discrete logic I noticed that the old 4000 series CMOS was much lower > >power than most of today's logic. I believe the quiescent current was > >in the nA range. For programmable, low power designs, that would be > >pretty amazing stuff to work with! 4000's series is spec'd from 3-18V, tho at 3V it's very slow. Newer AHC class devices are 1.65-5.5V - this device would try to be Static-Valid for Reset pathways etc as close to 1V as practical ( probably ~1.2V ). All logic that is comfortably clear of the extreme shrink devices should deliver sub uA operation, with a temperature qualifier. -jgArticle: 56041
In article <80a3aea5.0305270412.307530aa@posting.google.com>, Antti Lukats <antti@case2000.com> wrote: > >latest Xilinx iMpact doesnt seem to support the old style Parallel III >cable any more, I just built one and just upgraded to the latest WebPack SP (which includes an impact update) and used it to write XC9536/72. In what way is it "not supported"? -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 56042
Brett Foster wrote: > "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message > > > > The short stubs are important, and the traces shouldn't have > > any sharp angles - you want a really clean signal all around. > > I assume you've got ground planes and not a 2 layer board? > > That'll help a lot too. > > Why no sharp angles? Those electrons are moving at an appreciable fraction of the speed of light, and tend to oversteer. The rear end breaks loose going around those corners, and they are likely to go straight through the wall and injure somthing. :-) -- Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net> USE worldnet address!Article: 56043
Thanks for the reply its been very helpful. Maybe a SpartanII is the way to go then. As I live in the UK its not really worth sending boards backwards and forwards due to the postage / custom's charges. I may just purchase the board from www.burched.com. Do you know if the XILINX Student software places any restrictions on the VHDL for the Spartan 2 FPGA's? For example code size etc. "Spam Hater" <spam_hater_7@email.com> wrote in message news:ap07dvg9qje6mugq6np508863shimgjqiu@4ax.com... > I have two answers (opinions) > > 1) It is not possible. The contract between Xilinx and the synthesis > vendor was terminated over a year ago. There is NO HDL software > support for this device from Xilinx. See if Digilent will trade the > board for a SpartanII board. > > 2) The software is good, but the board is useless. All it has is the > chip on a PCB; no oscillator, stake pins for I/O, and not even a > voltage regulator. (I was going to make an expansion for mine, but > decided that getting a different board would be cheaper.) > > $.02, > SH7 > > PS: Take a look at Tony's products: www.burched.com > > > On Tue, 27 May 2003 12:54:38 -0700, "Ed Stevens" > <ed@stevens8436.fslife.co.uk> wrote: > > >Hi everyone, > > > >I have 2 questions: > > > >For the past few weeks I've been trying to get started with VHDL and FPGA's. > >I've purchased a Spartan board from Digilent and I've also purchased the > >Student software from XILINX. The problem im having is when I load the > >XILINX software and select the Spartan device it won't allow me to select a > >VHDL design flow, it only allows EDIF. If I select a Spartan2 device it > >will allow VHDL. Does anyone know if its possible to get the XILINX Student > >software to work with a Spartan in VHDL? > > > >My second question is: Does anyone have any opinions on the Cypress Delta39K > >CPLD Evaluation Board? Im thinking of buying it so I can implement a > >Digital Phase Locked Loop on it, in VHDL. Would it be capable of doing > >this? It appeals to me because it comes with the Cypress Warp VHDL > >software, is this software any good? > > > >Thanks for any help, > > >Article: 56044
On Tue, 27 May 2003 23:52:22 GMT, CBFalconer <cbfalconer@yahoo.com> wrote: >Brett Foster wrote: >> "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message >> > >> > The short stubs are important, and the traces shouldn't have >> > any sharp angles - you want a really clean signal all around. >> > I assume you've got ground planes and not a 2 layer board? >> > That'll help a lot too. >> >> Why no sharp angles? > >Those electrons are moving at an appreciable fraction of the speed >of light, and tend to oversteer. The rear end breaks loose going >around those corners, and they are likely to go straight through >the wall and injure somthing. :-) Gee, and I though that the smooth curves were not well thought of: from back in the days of hand layout, and black plastic trace tape, and the curves would move after some time as the tape shrunk after being stretched to make the nice curve. -- Arargh at [drop the 'http://www.' from ->] http://www.arargh.com Basic Compiler Samples Page: http://www.arargh.com/basic/basic.html To reply by email, change the domain name, and remove the garbage.Article: 56045
rickman wrote: > High speed signals see circuit board traces as wave guides. Sharp > corners in wave guides cause discontinuities. But this should not be an > issue with a 10 MHz signal unless the edges are razor sharp. Even then > the only real issue would be with the clock line unless your setup time > was very short and the ringing and bouncing of the data line ate up too > much of the time remaining. But signals that are driven fast should > give you extra setup time so there should be time for them to settle out > unless your traces are long. It's the combination that's bitten me - I can run long straight traces or short bent ones, but long bent ones tend to add too much noise to the TDI and some parts I've used won't daisy chain (the parts tend to amplify the noise). It's not radiation or line noise per se, it's the signal on the third chip in the line - it's too noisy to be useful. For JTAG, short lines are better in any case! Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 56046
On Wed, 28 May 2003 10:53:17 +1200, Jim Granville <jim.granville@designtools.co.nz> wrote: >Allan Herriman wrote: >> >> On Tue, 27 May 2003 12:15:29 -0400, rickman <spamgoeshere4@yahoo.com> >> wrote: >> >> >Jim Granville wrote: >> >> >> >> Imagine a ((RTC+NE555+4060+4093+22V10) * many), with the wide 1.65-5.5V >> >> Vcc of TinyLogic and you get the target I envisage. >> >> Would end up as widely used as EEPROMS :) >> > >> >This is largely what I am going to suggest to Semtech. Their MicroBuddy >> >is a very good start down that path. They just need to tweek some of >> >the specs and add the programmable logic. I am not sure what the 4093 >> >is, but I think the 4060 is a counter chain, no? > >Yes, XTAL Osc + Ripple Counter block. > >> The MicroBuddy has a >> >FLL running from the watch crystal which may do what you want with the >> >555 and 4060. >> >> The 4093 is a quad nand schmitt trigger. >> >> I think this dream part would be easier to use if it had schmitt >> inputs, with guaranteed min and max hysteresis and threshold voltages. > > Of course - _and_ designed for low linear mode currents. >- ( plus optional Rail-Rail comparitors, with inbuilt mV Hyst ~LM393 ) > >> (No doubt Peter A. will point out his app note that shows how to use >> "spare" pins and some resistors to make a schmitt input. But I >> usually find I need a high input impedance (or can't spare the pins), >> and it's easier to put a '14 or '132 on the board.) > > Hyst IS appearing on newer PLD offerings, either as an IP option, or >always enabled. Someone from Xilinx pointed out (via email) that Coolrunner II has hysteresis. I pointed out to him (also via email) that the datasheet doesn't guarantee a minimum Vh. If I want to use "analog" features of these chips, I need appropriate specifications! (Low linear mode currents would be good too *as long as they are specified*.) Regards, Allan >> >> Regards, >> Allan. >> >> >Since this chis is in a 3x3 QFN, if it had a higher freq range on the >> >FLL, I would use it as clock generators scattered around my board. >> > >> >I don't know much about designing PLD chips, but it would seem to me >> >that there is a market for very low power PLDs. While looking at >> >discrete logic I noticed that the old 4000 series CMOS was much lower >> >power than most of today's logic. I believe the quiescent current was >> >in the nA range. For programmable, low power designs, that would be >> >pretty amazing stuff to work with! > > 4000's series is spec'd from 3-18V, tho at 3V it's very slow. >Newer AHC class devices are 1.65-5.5V - this device would >try to be Static-Valid for Reset pathways etc as close to 1V >as practical ( probably ~1.2V ). > > All logic that is comfortably clear of the extreme shrink devices >should deliver sub uA operation, with a temperature qualifier. > > -jgArticle: 56047
Brett Foster wrote: > > "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message > news:3ED2E125.8010402@neurophys.wisc.edu... > > rickman wrote: > > > > The short stubs are important, and the traces shouldn't have any sharp > > angles - you want a really clean signal all around. I assume you've got > > ground planes and not a 2 layer board? That'll help a lot too. > > Why no sharp angles? > > Brett High speed signals see circuit board traces as wave guides. Sharp corners in wave guides cause discontinuities. But this should not be an issue with a 10 MHz signal unless the edges are razor sharp. Even then the only real issue would be with the clock line unless your setup time was very short and the ringing and bouncing of the data line ate up too much of the time remaining. But signals that are driven fast should give you extra setup time so there should be time for them to settle out unless your traces are long. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56048
In article <bb0omf$4lg94$1@ID-184277.news.dfncis.de>, custserv@forums.ws says... > > "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message > news:3ED2E125.8010402@neurophys.wisc.edu... > > rickman wrote: > > > > The short stubs are important, and the traces shouldn't have any sharp > > angles - you want a really clean signal all around. I assume you've got > > ground planes and not a 2 layer board? That'll help a lot too. > > Why no sharp angles? > > Brett At high frequencies, the the traces act as waveguides to the signals they carry, and can introduce reflections, which appears as signal "ringing", or extra oscillations. These can be misinterpreted as extra bits or illegal logic states, or just plain noise. --GeneArticle: 56049
Brett Foster wrote: > > "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message > news:3ED2E125.8010402@neurophys.wisc.edu... > > rickman wrote: > > > > The short stubs are important, and the traces shouldn't have any sharp > > angles - you want a really clean signal all around. I assume you've got > > ground planes and not a 2 layer board? That'll help a lot too. > > Why no sharp angles? > > Brett The inductance rises rapidly with the curvature. Analogously, a typical plumbing elbow has as much flow resistance as about 10 feet of pipe. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ
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