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tempedele@catcha.com (Tempe Dele) wrote in message news:<1093bfae.0305131904.5f285af5@posting.google.com>... Have you checked to see if the output is bit-reversed (if using 2-point butterfly core) or digit-reversed (dragonFly core). I think Xilinx uses dragongly core. So the output might be in the digit-reveresed order. > I have used Xilinx Coregen FFT 64 points using Triple Memory Space > (TMS) configuration. > > The timing diagram gave me correct information and confirm similar > with the timing diagram in the datasheet. > > The problem is on the result value, especially the sequence. I compare > the result with Matlab calculation. later I found, the value from > Xilinx coregen shows weird results. ( I used Modelsim). > > e.g : the data value for address 48 is appeared in address 16, data > value for address 1 is appeared in address 63. > > Anyone has the similar experience ? > > pls advice. > > Rgds. > > TempeArticle: 55626
Wong wrote: > Hi Mike, > Thanks for the pointer. But what if I have a synchronous design or > output registers and the device pins (make it simple, let say 2 bit > bus) still glitchy ? Post your code. -- Mike TreselerArticle: 55627
I have an obvious bias, but I'm going to give you some reasons to pay for a synthesis tool anyway. 1) Real timing driven synthesis with the ability to optimize for complex timing constraints such as multiple clocks, false and multi-cycle paths. My understanding is that constraints for XST only affect P&R. The netlist coming out of XST is not noticably affected by constraints. Real timing driven synthesis on big designs means that the tool can burn area for timing on your critical path and conserve area off of the critical path. We usually see large area savings on big designs. 2) Better timing results due to optimizing the netlist to meet your constraints, which on real designs involves multiple clocks at different frequencies. It is also true that on bigger designs that the area savings yields a faster design because the wires get shorter. For a small single clock design in a big part you may not see as much advantage, which is why we push people to benchmark on their real design. 3) Better design analysis linking post place and route results back to your RTL. The first step in fixing a problem is finding it's cause. 4) A support organization dedicated to synthesis. 5) Money. Multiply the price difference for a speed grade jump or a capacity jump times the number of systems you plan to build. Compare that to the cost of the synthesis tool. 6) If your volumes are high or you need a speedgrade that doesn't exist you can upgrade to physical synthesis (Amplify combines full placement and synthesis for Virtex-II). Ken McElvain CTO Synplicity, Inc. Yu Haiwen wrote: > Hi, Folks > > I'm doing design with Xilinx Virtex-II, and already have Xilinx ISE > 5.1i. The pack has its own synthesizer: XST. I've never used it before > and know little about its performance. > > My question is whether it's worth for me to buy another third party > synthesizer such as synplify or FPGA Compiler. They seem more powerful > yet cost a lot. > > Can you give me any advice or comparison of these tools? > > Thanks and Best Regards >Article: 55628
Jimmy wrote: > would be very thankfull if you could describe how to use global clock > signal and clock_enable. http://groups.google.com/groups?q=xilinx+clock+enable+webpack -- Mike TreselerArticle: 55629
valerio@most.it (Valerio Gionco) wrote in message news:<b472e06a.0305140453.5a4c27a4@posting.google.com>... > > Google for "Parallel Cable III" (with quotes) and you'll find a lot of > > info. I built one to their specs but I haven't built a proto board for > > the XC9536 to try it yet. > > I actually built it myself, along with a small test board. > Tested with ISE WebPack 5.2 on Windows 2000, misteriously > not working with WP4.2 and Win98. Search this newsgroup to find out why it did not work. It's a combination of broken software and an inferior schematic. The impact replaced the broken hardware debugger, whats left is the inferior schematic. Adding feedback resistors of 2K or so between the buffer outputs and inputs helps in many cases. Using a HCT chip with a low switching point (0.3 time VCC) improves the results even further. Kolja SulimmaArticle: 55630
Eduardo Wenzel Brião wrote: I already performed the same design in the Leonardo Spectrum using Graphic Interface without any error. But I performed line by line, copy-past them from a file TCL to Leonardo opened by simple text editor. I can generate all EDIFS needed to implement my design. However, creating EDIFs with line commnad tool, the execution is interrupted when apperaring some warning (I saw the log file generated by Leonardo. There are no errors). Is there some options in Leonardo Tool to ignore warnings in the line command execution? ---------- Don't know. Check the Leo reference manual. Send your script and description to support@mentor.com -- Mike TreselerArticle: 55631
Hi, I have been studying about self controlling dynamic reconfiguration since 2002. My work is to develop a reconfigurable system configuration manager that configures a part of FPGA according to a scheduling known. Recently I have problems with ICAP component. It is not well documented in by Xilinx. I would like any help about the ICAP. Thank you in advance for any help, sincerely yours, Ewerson Carvalho.Article: 55632
On 13 May 2003 19:15:15 -0700, tatto0_2000@yahoo.com (Wong) wrote: >Hi Mike, > Thanks for the pointer. But what if I have a synchronous design or >output registers and the device pins (make it simple, let say 2 bit >bus) still glitchy ? For example, I have the following SDF : If you're talking about the outputs of the registers arriving at the pins at different times, you can't avoid it completely. The best you can do is to instantiate the output registers at known locations (better yet, use the flops in the IOs) and make sure that the loads of the registers are the same (mainly the IO input capacitance). In that case, the two outputs are as balanced as they can get and the rest has to be tolerated by receiving logic. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 55633
Ken, To amplify your comments, here is a quote from our website: (FAQs on XST) "2 What is the quality of the XST's results? XST is comparable to other synthesis tools on the market. XST outperforms in some areas and not in others, as is true with any comparison between two synthesis tools. XST progresses in each release, improving clock frequencies and decreasing area, as well as reducing run time and memory utilization. XST has been tuned to Virtex architectures, inferring many of the architecture's specific primitives. Users have extensive control over inference capabilities and optimization techniques via global options and local attributes. Q3 Is Xilinx competing with Synplify and LeonardoSpectrum? No -- XST provides an OEM type, low-cost replacement for FPGA Express, and it is not intended to replace LeonardoSpectrum or Synplicity seats. These two tools offer superior interactive user features that help complete the highest-density, highest-speed designs: Xilinx shares its research into synthesis ideas with these two companies, and our software development focuses on PAR and is split across many other applications. Because of their single-minded focus on synthesis and our partnership efforts to help them continue to improve as quickly as possible, we expect these synthesis tools to remain superior. Q4 How extensive is XST language coverage? With each release, XST moves closer to the de facto coverage set by other synthesis tools. We estimate that our current language support covers at least 95% of the constructs supported by other synthesis tools. Many of the unsupported constructs are infrequently used or are easily worked around. Additionally, many of these constructs are not handled consistently by other synthesis tools -- one tool may accept a construct in a specific way, another in a different manner, and a third may flag a parsing error. These issues commonly occur when code is moved from one synthesis tool to another. In certain situations, XST is even more precise than other tools, as it requires exact, complete descriptions when other tools allow incomplete or vague code." Austin Ken McElvain wrote: > > I have an obvious bias, but I'm going to give you some reasons to > pay for a synthesis tool anyway. > > 1) Real timing driven synthesis with the ability to optimize for > complex timing constraints such as multiple clocks, false and > multi-cycle paths. My understanding is that constraints for XST > only affect P&R. The netlist coming out of XST is not noticably > affected by constraints. Real timing driven synthesis on big > designs means that the tool can burn area for timing on your critical > path and conserve area off of the critical path. We usually see > large area savings on big designs. > > 2) Better timing results due to optimizing the netlist to meet your > constraints, which on real designs involves multiple clocks at different > frequencies. It is also true that on bigger designs that the area > savings yields a faster design because the wires get shorter. For > a small single clock design in a big part you may not see as much > advantage, which is why we push people to benchmark on their real > design. > > 3) Better design analysis linking post place and route results back > to your RTL. The first step in fixing a problem is finding it's cause. > > 4) A support organization dedicated to synthesis. > > 5) Money. Multiply the price difference for a speed grade jump or > a capacity jump times the number of systems you plan to build. Compare > that to the cost of the synthesis tool. > > 6) If your volumes are high or you need a speedgrade that doesn't exist > you can upgrade to physical synthesis (Amplify combines full placement > and synthesis for Virtex-II). > > Ken McElvain > CTO > Synplicity, Inc. > > Yu Haiwen wrote: > > > Hi, Folks > > > > I'm doing design with Xilinx Virtex-II, and already have Xilinx ISE > > 5.1i. The pack has its own synthesizer: XST. I've never used it before > > and know little about its performance. > > > > My question is whether it's worth for me to buy another third party > > synthesizer such as synplify or FPGA Compiler. They seem more powerful > > yet cost a lot. > > > > Can you give me any advice or comparison of these tools? > > > > Thanks and Best Regards > >Article: 55634
Ray Andraka wrote: >Jan, > >I tried to explain what I think the problem you have is, and offered what I could to >help, but I get the impression you only read the first line. FPGA implementation tools >as well as the synthesis tools are not trivial programs, they entail hundreds of >thousands of lines of code. > We now have over 19 million lines of code now. Steve > The freee tools are a loss leader meant to lower the bar to >entry in FPGAs. Those free tools tend to be less capable than the more capable tools, >which you need to accept if you are going to use them. I'll bet you haven't even tried >searching the Xilinx answers data base like I suggested. > >Jan Panteltje wrote: > > > >>On a sunny day (Mon, 12 May 2003 20:04:27 GMT) it happened Ray Andraka >><ray@andraka.com> wrote in <3EBFFF2D.9899D504@andraka.com>: >> >> >> >>>Take a break, you are spending too much time in front of the computer. >>>Unfortunately with synthesis, unless you do a structural instantiation, you are >>>going to get internal nodes that don't map directly to the nodes in your verilog >>>design, hence the cryptic machine generated names. Unfortunately there isn't a >>>whole lot you can do about that, and it isn't unique to webpack. Webpack (or any >>>other synthesizer) is going to use your logic description to create logic that >>>matches what you conveyed in your description (whether it is right or wrong). If >>>the synthesis tool is half decent, it will do that mapping while attempting to make >>>the resulting circuit as efficient as it can given the input you gave it. >>>Frequently, that means using primitives such as carry chain components, or in your >>>case the MUXF6 primitives. >>> >>>Now to your problem, it looks like part of your mux is being optimized to eliminate >>>a whole 'leg' on the muxF6 or MUXF5 inputs. The synthesis software is optimizing >>>that out, but is not putting a buffer in its place. The implementation software >>>doesn't know how to change a VCC or Ground into a buffer so you are getting the >>>error you see. I think this is indeed a bug. CHeck the Xilinx answer database, >>>there may already be an answer in there for it (I've seen this problem before). If >>>not, the work around is to put syn_keep or similar attributes on the signals >>>connecting layers of the mux together to keep the synthesis from optimizing the LUTs >>>out, or to turn off use of the MUXF5's and 6's. I'm not sure what the control for >>>that is in the webpack, but I am sure there is something there somewhere. >>> >>> >>OK Ray, yes I am spending many hours in front of the monitor. >>But let's get things strait here, I just rebooted in Linux from the windows >>webpack re-wrote that design to bring some function back into the 'offending' >>part. >>That resulted in now 2 of the 16 units (they are all the same) getting a >>similar report. >>Since they are all the same I concluded that perhaps the design was to full >>up for webpack, and removed some logic (my serial routines) to see if the >>error would disappear. >>It did, but now you get 'programming error' in Impact without a reason WHY. >>(No its not hardware, the other stuff gives no programming error). >>So now I will be quite honest, and maybe Xilinx reads this too: >>My FIRST impression of Xilinx webpack was: total crap. >>Once I had a ZX81 (Sinclair) and a 'silversoft compiler' (some sort of basic >>compiler on tape), and it was JUST like webpack: slow, only some instructions >>works in some configuration, peculiar errors, never managed to make a working >>program with that. >> >>The FPGA without the right soft is useless. >>In stead of focusing on 10 GB links maybe it would be a lot wiser to focus >>on high quality soft. >>So people can actually use this stuff. >>Else I can only see webpack as an act of terrorism, and maybe I can get some >>European company to make FPGA so at least in the WW3 you guys provoke with >>it we will win because of better soft if not for better other reasons. >>Yes, I am sitting here now with the sandwiches with French Cheese and I am in >>a free country and can say this. >>When you look at good soft, like for example gcc, well, the guy who wrote >>webpack needs to do some study. >>Although some people (like that head -banging guy) CANNOT seem to understand >>how to program, for example Stroussup and C++. >>I wrote many a program, and many for the open source. >>I am not the greatest programmer, but at least it does what it needs to do. >>No I never had that problem of 'do what I want it to do', because I can write >>whatever I can think of and it will work. >>So I am canceling some FPGA projects now until there is sane software, lets >>say you are 20 years behind the state of the art with webpack. >>Now for my sandwiches. >>Regards >>Jan >> >> > >-- >--Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > > >Article: 55635
Hi Dick - Make sure you are using 5.2i with Service Pack 2. The versions that you mentioned (i.e. 4.2 and 5.1) have known bugs. Your issues should be solved with 5.2 SP2. Let me know if you continue to have problems... Thanks! Mark Richard Erlacher wrote: > I have implemented what amounts to a pretty simple design in the EV-module > that XILINX was giving away late last year to promote their CoolRunner-II > CPLD's. This isn't a bad board and it seems easy enough to use, BUT (and > that's what so frequently comes up with XILINX software) the software > doesn't seem, quite, to get the job done. There is a very rich feature set > associated with this CPLD family, and their pricing is not too bad, but the > ISE software doesn't seem to want to implement the functions correctly, or > even consistently from download to download. > > Has anybody else had such problems, or any experience to the contrary with > this series, and, specifically, with the last two versions (v4.2, v5.1) of > the ISE software? > > I've got lots of details, but won't bore the group with the specifics. > > thanx, > > DickArticle: 55636
Peter Alfke wrote: > Jan, > maybe you have a legitimate complaint, but you make it hard on us to > help you. All this ranting and raving, and "French cheese" and "free > country" nonsense just gets in the way of analyzing the problem. > Fewer generalities, shorter sentences, fewer incoherent comments, and I > might even forward your e-mail to our software folks. > But not this way... > Peter Alfke Jan Panteltje wrote: >> >>The FPGA without the right soft is useless. >>In stead of focusing on 10 GB links maybe it would be a lot wiser to focus >>on high quality soft. >>So people can actually use this stuff. >>Else I can only see webpack as an act of terrorism, and maybe I can get some >>European company to make FPGA so at least in the WW3 you guys provoke with >>it we will win because of better soft if not for better other reasons. I'm going to have to side with Xilinx on this. Your temper tantrum is helping no-one, least of all yourself. Many Xilinx folks here would have taken the effort to pass your literate complaints past tech support and directly to the developers, were you not going out of your way to insult them. If you think they are behaving maliciously, take your business elsewhere. The rest of us will work to make things better, in a civilized manner. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 55637
Steve Lass <lass@xilinx.com> writes: > Ray Andraka wrote: > > >Jan, > > > >I tried to explain what I think the problem you have is, and offered > >what I could to help, but I get the impression you only read the > >first line. FPGA implementation tools as well as the synthesis tools > >are not trivial programs, they entail hundreds of thousands of lines > >of code. > > > We now have over 19 million lines of code now. > > Steve Maintained by how many programmers? (I'm just curious) ThomasArticle: 55638
Jake Janovetz wrote: > Folks- > > How does one instantiate the schematic primitives in XST -- or is this > even possible now? Let's say I want a M2_1 (2-1 mux). The 'unisims' > directory of the Foundation toolset doesn't include these > 'primitives'. Rather, it includes things such as LUTs. Look for "black box" instantiation in the XST manual. You can even make your own black boxes and convince xst to use them. There is an attribute and a simple declaration syntax that takes care of it, and for unisims, there is a header file that to can include that even does that for you. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 55639
Followup to: <b9q0te$n08$1@cesium.transmeta.com> By author: H. Peter Anvin <hpa@zytor.com> In newsgroup: comp.arch.fpga > > Followup to: <6ed146ef.0305091923.5d70181d@posting.google.com> > By author: azafar@iupui.edu (Atif Zafar) > In newsgroup: comp.arch.fpga > > > > Does anyone know prices for a "loaded" MJL Stratix board (32 MB > > SDRAM+16 MB FLASH) and is it shipping now? I have emailed the MJL > > sales guys but no one responded. Thanks. > > > > $595 (until end of June) and it's shipping. Expect 2-3 week delivery > time to the U.S. though. I bugged them a few times last week and now > their online ordering web page is back up. > Sorry, that price was for the Cyclone board. The Stratix one is $795 plus $100 for the extra memory. (I was obviously looking for the Cyclone kit myself.) -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 55640
Followup to: <ff8a3afb.0305140150.8b9ecb5@posting.google.com>
By author: praveenkumar1979@rediffmail.com (praveen)
In newsgroup: comp.arch.fpga
>
> hi Sir/Friends,
> I wanted to know how to calculate the gate count in a FPGA design. If
> there is any article regarding it, do mention. If you can give an
> example it will be great.
>
Run your design through a synthesizer. Most of them spit out an
"effective gate count" or some equally useless number as part of their
spewage.
This number is completely arbitrary and technology-dependent; I have
in fact seen the Xilinx tools spit out a number over 150,000 gates for
a XC2100 design ("100,000 gates".) What really matters is the number
of LUTs, plus all the other things on the chip (block RAM, PLL/DLLs,
DSP elements, ...)
LUTs seem to be a decent metric; I have played with the same design in
Xilinx Spartan-II and Altera Cyclone synthesis, and the number of LUTs
(LEs in Altera jargon, half-slices in Xilinx jargon) usually stay
within 10% or so. Of course, these are both architectures without
lots of fancy elements like multipliers, which can throw everything
off completely.
-hpa
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
Article: 55641
Just to highlight your point, here is an XC2S15 (a 15K gate device) design I
did two weeks ago with an equivalent gate count of 67K gates:
------------------
Command Line : map -p xc2s15-5-tq144 -o map.ncd -fp paad.mfp -l -pr b
-detail
paad.ngd paad.pcf
Target Device : x2s15
Target Package : tq144
Target Speed : -5
Mapper Version : spartan2 -- D.27
Mapped Date : Tue May 06 15:21:27 2003
Design Summary
--------------
Number of errors: 0
Number of warnings: 147
Number of Slices: 192 out of 192 100%
Number of Slices containing
unrelated logic: 34 out of 192 17%
Number of Slice Flip Flops: 292 out of 384 76%
Total Number 4 input LUTs: 339 out of 384 88%
Number used as LUTs: 229
Number used as Shift registers: 110
Number of bonded IOBs: 69 out of 86 80%
IOB Flip Flops: 16
Number of Tbufs: 16 out of 224 7%
Number of Block RAMs: 3 out of 4 75%
Number of GCLKs: 4 out of 4 100%
Number of GCLKIOBs: 4 out of 4 100%
Number of RPM macros: 4
Total equivalent gate count for design: 67,851
Additional JTAG gate count for IOBs: 3,504
"H. Peter Anvin" wrote:
> Followup to: <ff8a3afb.0305140150.8b9ecb5@posting.google.com>
> By author: praveenkumar1979@rediffmail.com (praveen)
> In newsgroup: comp.arch.fpga
> >
> > hi Sir/Friends,
> > I wanted to know how to calculate the gate count in a FPGA design. If
> > there is any article regarding it, do mention. If you can give an
> > example it will be great.
> >
>
> Run your design through a synthesizer. Most of them spit out an
> "effective gate count" or some equally useless number as part of their
> spewage.
>
> This number is completely arbitrary and technology-dependent; I have
> in fact seen the Xilinx tools spit out a number over 150,000 gates for
> a XC2100 design ("100,000 gates".) What really matters is the number
> of LUTs, plus all the other things on the chip (block RAM, PLL/DLLs,
> DSP elements, ...)
>
> LUTs seem to be a decent metric; I have played with the same design in
> Xilinx Spartan-II and Altera Cyclone synthesis, and the number of LUTs
> (LEs in Altera jargon, half-slices in Xilinx jargon) usually stay
> within 10% or so. Of course, these are both architectures without
> lots of fancy elements like multipliers, which can throw everything
> off completely.
>
> -hpa
> --
> <hpa@transmeta.com> at work, <hpa@zytor.com> in private!
> "Unix gives you enough rope to shoot yourself in the foot."
> Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55642Thomas Heller wrote: >Steve Lass <lass@xilinx.com> writes: > > > >>Ray Andraka wrote: >> >> >> >>>Jan, >>> >>>I tried to explain what I think the problem you have is, and offered >>>what I could to help, but I get the impression you only read the >>>first line. FPGA implementation tools as well as the synthesis tools >>>are not trivial programs, they entail hundreds of thousands of lines >>>of code. >>> >>> >>> >>We now have over 19 million lines of code now. >> >>Steve >> >> > >Maintained by how many programmers? (I'm just curious) > I'd rather not give exact numbers, but it's quite a few. And I think we have over 50 engineers testing the software, so we do treat quality seriously. Steve Steve > >Thomas > >Article: 55643
Ray Andraka wrote:
>
<snip>
> Design Summary
> --------------
> Number of errors: 0
> Number of warnings: 147
> Number of Slices: 192 out of 192 100%
> Number of Slices containing
> unrelated logic: 34 out of 192 17%
:)) - amusing choice of words, just what can 'containing unrelated
logic'
mean!.
One would hope that all logic was related to the design ?
Article: 55644Steve Lass wrote: > > Thomas Heller wrote: > > >Steve Lass <lass@xilinx.com> writes: > >>> > >>We now have over 19 million lines of code now. > >> > >>Steve > > > >Maintained by how many programmers? (I'm just curious) > > > I'd rather not give exact numbers, but it's quite a few. And I think we > have over 50 engineers testing the > software, so we do treat quality seriously. I saw a release from Altera a while ago, that mentioned their SW designer count, was ahead of the hardware designer count, and both (IIRC) were in the hundreds. Clearly, this is non-trivial engineering, and sometimes the tools take one step back, as they endeavour to take two steps forward. "50 engineers testing the software" is OK, but it also needs inputs from those USING the SW, and pushing the tools as well. In many cases, the beef with tool flows is in the error messages, and how well they point users to problems. This can be 'off the radar' of those running test suites, and the coders themselves, so user feedback does help here. -jgArticle: 55645
I beginner with Xilinx ISE 4.1. I've read the ISE 4 Tutorial to create a 4-bit countuner with a Testbench Waveform Model. I can't run a Generate Expected Simulation Results, the console lines are: c:\Modeltech_xe\win32xoem\ModelSim.exe ISE Auto-Make Log File ----------------------- Updating: Generate Expected Simulation Results Starting: 'exewrap -tapkeep -mode pipe -sen 50 -tcl -command C:/Xilinx/data/projnav/__simulateAnnoTestBench.tcl __antTOano.rsp' Creating TCL Process Running Automatic Do File: counter_tbw.ado Starting: '@HKLM/SOFTWARE/Classes/XLNXEDA/products/DESIGNCNTR10/paths/VSystemPath/@/vsim -c -do counter_tbw.ado' Done: failed with exit code: 0005. The Simulate Behavioral VHDL Model is: ISE Auto-Make Log File ----------------------- Updating: Simulate Behavioral VHDL Model Starting: 'exewrap @__updateTBW_exewrap.rsp' Starting: 'C:/Xilinx/bin/nt/tb.exe /u "d:\my_projects\tutorial2\counter_tbw.tbw" ' EXEWRAP detected that program 'C:/Xilinx/bin/nt/tb.exe' completed successfully. Done: completed successfully. Starting: 'exewrap @_vhdTOfdo_exewrap.rsp' Starting: 'xilperl C:/Xilinx/data/projnav/createfdo.pl __vhdTOfdo.rsp ' Opening __vhdTOfdo.rsp ERROR: Model Technology's ModelSim executable cannot be found by Project Navigator. Please go to the 'Edit' menu, select 'Preferences' and then select the 'Partner Tools' tab. Using this dialog select the ModelSim executable that you wish to use for simulation. Then re-start Project Navigator and try this process again. EXEWRAP detected a return code of '-1' from program 'xilperl' Done: failed with exit code: 65535. Anybody fit the problem? Thanks in advance, DavidArticle: 55646
On a sunny day (Wed, 14 May 2003 12:26:09 GMT) it happened Ray Andraka <ray@andraka.com> wrote in <3EC236C8.BD3D225D@andraka.com>: >Jan, > >I tried to explain what I think the problem you have is, and offered what I could to >help, but I get the impression you only read the first line. FPGA implementation tools >as well as the synthesis tools are not trivial programs, they entail hundreds of >thousands of lines of code. The freee tools are a loss leader meant to lower the bar to >entry in FPGAs. Those free tools tend to be less capable than the more capable tools, >which you need to accept if you are going to use them. I'll bet you haven't even tried >searching the Xilinx answers data base like I suggested. Bet for a copy of Synplicity? xilinx logs if they keep any should show I did, also I did not read only the first lines. And I tried to subscibe to 'webcase' which is not allowed. 50 soft designers he? Then you need at least 5 to 10 managers and with that many managers you get communication problems then you need someone for that too. But this explains a lot. ByeArticle: 55647
Uwe Bonnes wrote: > Do you run with native msvcrt and wine set to emulate the right windows > version? That is at least what often helps with webpack and winehq CVS wine. > Try something like the following in ~/.wine/config (webpack comes with > msvcrt dlls for winxp) > > [Version] > "Windows" = "winxp" > > [DllOverrides] > "msvcrt" = "native, builtin" > [AppDefaults\\sol.exe\\Version] Hi Uwe, Yes tried all that, I was using the "win2k" setting but "winxp" didn't help. I'm using a native msvcrt that I downloaded from dll-files.com - it's from win98 which is what Xilinx recommend. I also had to get msvcirt.dll. It's interesting, I can run all of the individual tools, and I can run "xflow -norun" to generate the tcl and .bat scripts of the flow, the problem only manifests itself when xflow itself attempts to run the tools. i'll keep digging and see what i come up with. I know you're a bit of an "ISE under linux" guru - are you able to run xflow successfully? I'm using fpga.flw, the implementation flow, and fast_runtime.opt. Cheers, JohnArticle: 55648
John Williams wrote: > Uwe Bonnes wrote: > >> Do you run with native msvcrt and wine set to emulate the right windows >> version? That is at least what often helps with webpack and winehq >> CVS wine. >> Try something like the following in ~/.wine/config (webpack comes with >> msvcrt dlls for winxp) >> >> [Version] >> "Windows" = "winxp" >> >> [DllOverrides] >> "msvcrt" = "native, builtin" >> [AppDefaults\\sol.exe\\Version] > > > Hi Uwe, > > Yes tried all that, I was using the "win2k" setting but "winxp" didn't > help. I'm using a native msvcrt that I downloaded from dll-files.com - > it's from win98 which is what Xilinx recommend. I also had to get > msvcirt.dll. I just tried again after copying the dlls out of the "redist" directory in the ISE5.2 disks, and setting the windows version in wine accordingly. Still the same result, each tool runs fine by itself, but xflow chokes after it runs ngdbuild, but before it launches map.Article: 55649
Normally, if the timing diagram has matched with the Xilinx datasheet = then it should be alright. Maybe it is the time to check your matlab = session. Best regards. Basuki -----Original Message----- From: Sandeep [mailto:smukthav@yahoo.com] Posted At: Thursday, May 15, 2003 12:17 AM Posted To: fpga Conversation: Xilinx Coregen FFT64 Subject: Re: Xilinx Coregen FFT64 tempedele@catcha.com (Tempe Dele) wrote in message = news:<1093bfae.0305131904.5f285af5@posting.google.com>... Have you checked to see if the output is bit-reversed (if using 2-point butterfly core) or digit-reversed (dragonFly core). I think Xilinx uses dragongly core. So the output might be in the digit-reveresed order. > I have used Xilinx Coregen FFT 64 points using Triple Memory Space > (TMS) configuration. >=20 > The timing diagram gave me correct information and confirm similar > with the timing diagram in the datasheet. >=20 > The problem is on the result value, especially the sequence. I compare > the result with Matlab calculation. later I found, the value from > Xilinx coregen shows weird results. ( I used Modelsim). >=20 > e.g : the data value for address 48 is appeared in address 16, data > value for address 1 is appeared in address 63. >=20 > Anyone has the similar experience ? >=20 > pls advice. >=20 > Rgds. >=20 > Tempe
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