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Jan, maybe you have a legitimate complaint, but you make it hard on us to help you. All this ranting and raving, and "French cheese" and "free country" nonsense just gets in the way of analyzing the problem. Fewer generalities, shorter sentences, fewer incoherent comments, and I might even forward your e-mail to our software folks. But not this way... Peter Alfke Jan Panteltje wrote: > > On a sunny day (Mon, 12 May 2003 20:04:27 GMT) it happened Ray Andraka > <ray@andraka.com> wrote in <3EBFFF2D.9899D504@andraka.com>: > > >Take a break, you are spending too much time in front of the computer. > >Unfortunately with synthesis, unless you do a structural instantiation, you are > >going to get internal nodes that don't map directly to the nodes in your verilog > >design, hence the cryptic machine generated names. Unfortunately there isn't a > >whole lot you can do about that, and it isn't unique to webpack. Webpack (or any > >other synthesizer) is going to use your logic description to create logic that > >matches what you conveyed in your description (whether it is right or wrong). If > >the synthesis tool is half decent, it will do that mapping while attempting to make > >the resulting circuit as efficient as it can given the input you gave it. > >Frequently, that means using primitives such as carry chain components, or in your > >case the MUXF6 primitives. > > > >Now to your problem, it looks like part of your mux is being optimized to eliminate > >a whole 'leg' on the muxF6 or MUXF5 inputs. The synthesis software is optimizing > >that out, but is not putting a buffer in its place. The implementation software > >doesn't know how to change a VCC or Ground into a buffer so you are getting the > >error you see. I think this is indeed a bug. CHeck the Xilinx answer database, > >there may already be an answer in there for it (I've seen this problem before). If > >not, the work around is to put syn_keep or similar attributes on the signals > >connecting layers of the mux together to keep the synthesis from optimizing the LUTs > >out, or to turn off use of the MUXF5's and 6's. I'm not sure what the control for > >that is in the webpack, but I am sure there is something there somewhere. > > OK Ray, yes I am spending many hours in front of the monitor. > But let's get things strait here, I just rebooted in Linux from the windows > webpack re-wrote that design to bring some function back into the 'offending' > part. > That resulted in now 2 of the 16 units (they are all the same) getting a > similar report. > Since they are all the same I concluded that perhaps the design was to full > up for webpack, and removed some logic (my serial routines) to see if the > error would disappear. > It did, but now you get 'programming error' in Impact without a reason WHY. > (No its not hardware, the other stuff gives no programming error). > So now I will be quite honest, and maybe Xilinx reads this too: > My FIRST impression of Xilinx webpack was: total crap. > Once I had a ZX81 (Sinclair) and a 'silversoft compiler' (some sort of basic > compiler on tape), and it was JUST like webpack: slow, only some instructions > works in some configuration, peculiar errors, never managed to make a working > program with that. > > The FPGA without the right soft is useless. > In stead of focusing on 10 GB links maybe it would be a lot wiser to focus > on high quality soft. > So people can actually use this stuff. > Else I can only see webpack as an act of terrorism, and maybe I can get some > European company to make FPGA so at least in the WW3 you guys provoke with > it we will win because of better soft if not for better other reasons. > Yes, I am sitting here now with the sandwiches with French Cheese and I am in > a free country and can say this. > When you look at good soft, like for example gcc, well, the guy who wrote > webpack needs to do some study. > Although some people (like that head -banging guy) CANNOT seem to understand > how to program, for example Stroussup and C++. > I wrote many a program, and many for the open source. > I am not the greatest programmer, but at least it does what it needs to do. > No I never had that problem of 'do what I want it to do', because I can write > whatever I can think of and it will work. > So I am canceling some FPGA projects now until there is sane software, lets > say you are 20 years behind the state of the art with webpack. > Now for my sandwiches. > Regards > JanArticle: 55601
In article <3EC1681F.80800@raytheon.com>, Michael Bills <mbbillsREMOVE_THIS@raytheon.com> wrote: >Does anyone know if the 50K gate Spartan3 has a DLL since it doesn't >have a DCM? The smallest Spartan3 has no DCMs, the DLLs are in the DCMs, so no it does not have one according to the datasheet. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 55602
Uwe Bonnes wrote: > > A recent well configured wine with the prerequisited for Installshield 6 > installers ( native stdole*.tbl) in the <wine>/windows directory should do > the job. Installation will take some time ( wine directory handling in > help/usenglish/newroot with it's 5499 files is not optimal) , show some > errors and message box stacking may be wrong so that na "OK" buttom is > hidden, but the installation should be useable. yup, worked for me after some MSVC*RT.DLL tweaking. taking thie most recent pair from winXP and setting wine version to winxp did the trick... wine spits out some error/debugging (?) info but all the command line programs below work fine... > First run the GUI, set up a project and run the toolchain. After that, ISE > has produced command files you may use in a script like this one for > Verilog: > export XILINX=l:\\webpack-5.2 > /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/xst -quiet -ifn __projnav/pasamain.xst -ofn pasamain.syr > /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/ngdbuild -quiet -dd h:\\work\\projekte\\alice\\pasa-astf\\fpga\\pasamain > /_ngo -uc xilinx.ucf -aul -a -p xc2s200-pq208-5 pasamain.ngc pasamain.ngd /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/map -quiet -p xc2s200-pq208-5 -cm speed -detail -pr b -k 4 -c 100 -tx of > f -o pasamain_map.ncd pasamain.ngd pasamain.pcf > /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/par -w -ol 2 -t 1 -detail pasamain_map.ncd pasamain.ncd pasamain.pcf > /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/bitgen -f pasamain.ut pasamain.ncd > /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/impact -batch impact.cmd > > This script will not stop on arrors. Connecting the commands with "&&" > should do that. ... except for the last (non command-line) one - apparently either impact can't see the board (Digilent's Digilab 2) hooked up through through the parallel port (albait it has no problem when running under VMWare on the very same PC box) or i don't know how to configure wine - at the moment I've got one of the LPT devices pointing to /dev/parport0 anyone knows if that's correct ? or what's a setup known to work ? does serial -> JTAG work ? lukasz -- ------------------------------------------------------------------------- Lukasz Salwinski E-MAIL: lukasz@mbi.ucla.edu DOE-MBI Center for Genomics and Proteomics PHONE : 310-825-1402 UCLA, Los Angeles FAX : 310-206-3914 -------------------------------------------------------------------------Article: 55603
> > >Does anyone know if the 50K gate Spartan3 has a DLL since it doesn't > >have a DCM? > > The smallest Spartan3 has no DCMs, the DLLs are in the DCMs, so no it > does not have one according to the datasheet. The production version of smallest Spartan-3 3S50, has two DCMs, 4 BlockRAMs and 4 multipliers. Spartan-3 datasheet was updated recently. http://direct.xilinx.com/bvdocs/publications/ds099-1.pdf -VikramArticle: 55604
Vikram Pasham <Vikram.Pasham@xilinx.com> wrote: :> :> >Does anyone know if the 50K gate Spartan3 has a DLL since it doesn't :> >have a DCM? :> :> The smallest Spartan3 has no DCMs, the DLLs are in the DCMs, so no it :> does not have one according to the datasheet. : The production version of smallest Spartan-3 3S50, has two DCMs, 4 BlockRAMs : and 4 multipliers. Spartan-3 datasheet was updated recently. : http://direct.xilinx.com/bvdocs/publications/ds099-1.pdf Sounds much more resonable... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55605
I have implemented what amounts to a pretty simple design in the EV-module that XILINX was giving away late last year to promote their CoolRunner-II CPLD's. This isn't a bad board and it seems easy enough to use, BUT (and that's what so frequently comes up with XILINX software) the software doesn't seem, quite, to get the job done. There is a very rich feature set associated with this CPLD family, and their pricing is not too bad, but the ISE software doesn't seem to want to implement the functions correctly, or even consistently from download to download. Has anybody else had such problems, or any experience to the contrary with this series, and, specifically, with the last two versions (v4.2, v5.1) of the ISE software? I've got lots of details, but won't bore the group with the specifics. thanx, DickArticle: 55606
These app notes from 1995 were written for the original XC4000 family, which only had asynchronous RAM. All families since then have synchronous RAM, including the XC4000E and XC4000XL/A. JDS wrote: > Hi, > > I am just wondering why the following App-notes are missing on the Xilinx web page: > Using the XC4000 RAM Capability (XAPP 031) > and High-Speed RAM design in XC4000 (XAPP 042) > > Can someone point me to those ANs? > > Thank you, > JDS -- Marc Baker Xilinx Applications (408) 879-5375Article: 55607
In article <b9rt38$ddc$1@news.tu-darmstadt.de>, Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >: and 4 multipliers. Spartan-3 datasheet was updated recently. >: http://direct.xilinx.com/bvdocs/publications/ds099-1.pdf > >Sounds much more resonable... EXCLELLENT! -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 55608
Hi Mike,
Thanks for the pointer. But what if I have a synchronous design or
output registers and the device pins (make it simple, let say 2 bit
bus) still glitchy ? For example, I have the following SDF :
(CELL
(CELLTYPE "OUTBUF")
(INSTANCE output_pad_0)
(DELAY
(ABSOLUTE
(PORT D (1.07:1.65:2.29) (1.07:1.65:2.25))
(IOPATH D PAD (8.80:13.20:18.29) (8.80:13.20:19.55))
)
)
)
(CELL
(CELLTYPE "OUTBUF")
(INSTANCE output_pad_1)
(DELAY
(ABSOLUTE
(PORT D (0.35:0.55:0.76) (0.35:0.55:0.75))
(IOPATH D PAD (8.80:13.20:18.29) (8.80:13.20:19.55))
)
)
)
where the instance output_pad_1 and output_pad_0 drive by 2
D-registers respectively. As shown above, for PORT D of pad_1, max
delay is 0.76/0.75 and the other one is not the same. I think this
will still introduce the glitch to the device pin, am I correct ?
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3EC13D24.7070909@flukenetworks.com>...
> Wong wrote:
>
> > # ** Warning: VitalGlitch: GLITCH Detected on port Y ; Preempted
> > Future Value := 1 @ 200152.541 ns; Newly Scheduled Value := 0 @
> > 200153.004 ns;
> > # Time: 200152317 ps Iteration: 0 Instance:
> > /mooredemo_tb/moore_pm/current_state_h/current_state_ns_0_and2_0
>
> > How these glitches can be removed ?
>
> They may not have to be removed if it is an internal node
> of a synchronous design.
> If it is a device pin, you may need an output register.
>
> In a synchronous design, glitches on internal combinational
> nodes that do not cause a setup violation at the next
> register are tolerable. For example, I might make a glitchy
> ripple counter driving an output register. Glitches
> on the D side would be expected, but not on the Q side.
>
> > Of course, I am not talking
> > about switching off the glitch-detect option in ModelSim.
>
> It probably makes sense to do just that for expected glitches.
>
> -- Mike Treseler
Article: 55609I have used Xilinx Coregen FFT 64 points using Triple Memory Space (TMS) configuration. The timing diagram gave me correct information and confirm similar with the timing diagram in the datasheet. The problem is on the result value, especially the sequence. I compare the result with Matlab calculation. later I found, the value from Xilinx coregen shows weird results. ( I used Modelsim). e.g : the data value for address 48 is appeared in address 16, data value for address 1 is appeared in address 63. Anyone has the similar experience ? pls advice. Rgds. TempeArticle: 55610
Folks- How does one instantiate the schematic primitives in XST -- or is this even possible now? Let's say I want a M2_1 (2-1 mux). The 'unisims' directory of the Foundation toolset doesn't include these 'primitives'. Rather, it includes things such as LUTs. Of course, I can instantiate a LUT with the proper init values, but it would go a long way in readability not to mention "error protection" to have the MUX available as a primitive. This goes for all the other less-primitive blocks such as ACC1(4/8/16) and so on. Are these just not available in XST as blocks? JakeArticle: 55611
Hi folks, I've been investigating using EDK under Linux/wine, and one of the major issues seems to be actually a problem with xflow. I'm using EDK3.2 and ISE5.2 all patched and service packed up to the latest and greatest. When you do the "make bits" step, it launches xflow to run through the ngdbuild,map,par,bitgen utilities. Each of them in their own right works under wine, but xflow doesn't. Here's the output I got: [jwilliam@g435-9029 linux_test]$ make -f system.make bits Copying Xilinx Implementation tool scripts.. ********************************************* Running Xilinx Implementation tools.. ********************************************* [snip normal output] Writing NGDBUILD log file "system.bld"... NGDBUILD done. ERROR:Xflow - ngdbuild: Invalid handle ERROR:Xflow:42 - Aborting flow execution... make: *** [implementation/system.bit] Error 1 As I said, each step can be executed by hand without problems, it's just the xflow wrapper that seems to be breaking. I searched the Xilinx answers database but found no mention of xflow issues within wine. My ISE/Wine setup is as per recommended by Xilinx. Can anybody offer any advice or suggestions? Thanks, JohnArticle: 55612
Jake, I think you are right. XST no longer supports the direct instantiation of the M2_1 primitive. The libraries guide states "For HDL, this design element is inferred rather than instantiated". This is probably a good thing to avoid now anyway. Synthesizers know how to construct carry chains and when to use block multipliers. Where I work we have built up a library of synthesizable, parametized elements. This lets us code in a structural style when we want but the library is architecture independent so our code is portable except for proprietary elements like block rams. There should really be a public domain library like this but I haven't found one. -- Pete Dudley Arroyo Grande Systems "Jake Janovetz" <jakespambox@yahoo.com> wrote in message news:d6ad3144.0305132010.7e425ff1@posting.google.com... > Folks- > > How does one instantiate the schematic primitives in XST -- or is this > even possible now? Let's say I want a M2_1 (2-1 mux). The 'unisims' > directory of the Foundation toolset doesn't include these > 'primitives'. Rather, it includes things such as LUTs. > > Of course, I can instantiate a LUT with the proper init values, but it > would go a long way in readability not to mention "error protection" > to have the MUX available as a primitive. > > This goes for all the other less-primitive blocks such as ACC1(4/8/16) > and so on. Are these just not available in XST as blocks? > > JakeArticle: 55613
John Williams <jwilliams@itee.uq.edu.au> wrote: : Hi folks, : I've been investigating using EDK under Linux/wine, and one of the major : issues seems to be actually a problem with xflow. I'm using EDK3.2 and : ISE5.2 all patched and service packed up to the latest and greatest. : When you do the "make bits" step, it launches xflow to run through the : ngdbuild,map,par,bitgen utilities. Each of them in their own right : works under wine, but xflow doesn't. Here's the output I got: : [jwilliam@g435-9029 linux_test]$ make -f system.make bits : Copying Xilinx Implementation tool scripts.. : ********************************************* : Running Xilinx Implementation tools.. : ********************************************* : [snip normal output] : Writing NGDBUILD log file "system.bld"... : NGDBUILD done. : ERROR:Xflow - ngdbuild: Invalid handle : ERROR:Xflow:42 - Aborting flow execution... : make: *** [implementation/system.bit] Error 1 : As I said, each step can be executed by hand without problems, it's just : the xflow wrapper that seems to be breaking. I searched the Xilinx : answers database but found no mention of xflow issues within wine. My : ISE/Wine setup is as per recommended by Xilinx. : Can anybody offer any advice or suggestions? Do you run with native msvcrt and wine set to emulate the right windows version? That is at least what often helps with webpack and winehq CVS wine. Try something like the following in ~/.wine/config (webpack comes with msvcrt dlls for winxp) [Version] "Windows" = "winxp" [DllOverrides] "msvcrt" = "native, builtin" [AppDefaults\\sol.exe\\Version] Hope this helps. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55614
Hi and thanks Mike! To be honest I dont have much experience of FPGA:s (as you most certainly know) so I would be very thankfull if you could describe how to use global clock signal and clock_enable. I'm using webpack and a spartan 11e fpgaArticle: 55615
Hi, Folks I'm doing design with Xilinx Virtex-II, and already have Xilinx ISE 5.1i. The pack has its own synthesizer: XST. I've never used it before and know little about its performance. My question is whether it's worth for me to buy another third party synthesizer such as synplify or FPGA Compiler. They seem more powerful yet cost a lot. Can you give me any advice or comparison of these tools? Thanks and Best RegardsArticle: 55616
hi Sir/Friends, I wanted to know how to calculate the gate count in a FPGA design. If there is any article regarding it, do mention. If you can give an example it will be great. wiating for your reply PraveenArticle: 55617
Jan,
I tried to explain what I think the problem you have is, and offered what I could to
help, but I get the impression you only read the first line. FPGA implementation tools
as well as the synthesis tools are not trivial programs, they entail hundreds of
thousands of lines of code. The freee tools are a loss leader meant to lower the bar to
entry in FPGAs. Those free tools tend to be less capable than the more capable tools,
which you need to accept if you are going to use them. I'll bet you haven't even tried
searching the Xilinx answers data base like I suggested.
Jan Panteltje wrote:
> On a sunny day (Mon, 12 May 2003 20:04:27 GMT) it happened Ray Andraka
> <ray@andraka.com> wrote in <3EBFFF2D.9899D504@andraka.com>:
>
> >Take a break, you are spending too much time in front of the computer.
> >Unfortunately with synthesis, unless you do a structural instantiation, you are
> >going to get internal nodes that don't map directly to the nodes in your verilog
> >design, hence the cryptic machine generated names. Unfortunately there isn't a
> >whole lot you can do about that, and it isn't unique to webpack. Webpack (or any
> >other synthesizer) is going to use your logic description to create logic that
> >matches what you conveyed in your description (whether it is right or wrong). If
> >the synthesis tool is half decent, it will do that mapping while attempting to make
> >the resulting circuit as efficient as it can given the input you gave it.
> >Frequently, that means using primitives such as carry chain components, or in your
> >case the MUXF6 primitives.
> >
> >Now to your problem, it looks like part of your mux is being optimized to eliminate
> >a whole 'leg' on the muxF6 or MUXF5 inputs. The synthesis software is optimizing
> >that out, but is not putting a buffer in its place. The implementation software
> >doesn't know how to change a VCC or Ground into a buffer so you are getting the
> >error you see. I think this is indeed a bug. CHeck the Xilinx answer database,
> >there may already be an answer in there for it (I've seen this problem before). If
> >not, the work around is to put syn_keep or similar attributes on the signals
> >connecting layers of the mux together to keep the synthesis from optimizing the LUTs
> >out, or to turn off use of the MUXF5's and 6's. I'm not sure what the control for
> >that is in the webpack, but I am sure there is something there somewhere.
>
> OK Ray, yes I am spending many hours in front of the monitor.
> But let's get things strait here, I just rebooted in Linux from the windows
> webpack re-wrote that design to bring some function back into the 'offending'
> part.
> That resulted in now 2 of the 16 units (they are all the same) getting a
> similar report.
> Since they are all the same I concluded that perhaps the design was to full
> up for webpack, and removed some logic (my serial routines) to see if the
> error would disappear.
> It did, but now you get 'programming error' in Impact without a reason WHY.
> (No its not hardware, the other stuff gives no programming error).
> So now I will be quite honest, and maybe Xilinx reads this too:
> My FIRST impression of Xilinx webpack was: total crap.
> Once I had a ZX81 (Sinclair) and a 'silversoft compiler' (some sort of basic
> compiler on tape), and it was JUST like webpack: slow, only some instructions
> works in some configuration, peculiar errors, never managed to make a working
> program with that.
>
> The FPGA without the right soft is useless.
> In stead of focusing on 10 GB links maybe it would be a lot wiser to focus
> on high quality soft.
> So people can actually use this stuff.
> Else I can only see webpack as an act of terrorism, and maybe I can get some
> European company to make FPGA so at least in the WW3 you guys provoke with
> it we will win because of better soft if not for better other reasons.
> Yes, I am sitting here now with the sandwiches with French Cheese and I am in
> a free country and can say this.
> When you look at good soft, like for example gcc, well, the guy who wrote
> webpack needs to do some study.
> Although some people (like that head -banging guy) CANNOT seem to understand
> how to program, for example Stroussup and C++.
> I wrote many a program, and many for the open source.
> I am not the greatest programmer, but at least it does what it needs to do.
> No I never had that problem of 'do what I want it to do', because I can write
> whatever I can think of and it will work.
> So I am canceling some FPGA projects now until there is sane software, lets
> say you are 20 years behind the state of the art with webpack.
> Now for my sandwiches.
> Regards
> Jan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55618
'Gate count' is kind of a hand waving exercise in FPGAs whose main value
seems to be for marketing. A more realistic count for FPGAs is the LUT
count. Take a look at this EDN article I contributed to in 1998:
http://www.e-insite.net/ednmag/archives/1998/080398/16cs.htm
praveen wrote:
> hi Sir/Friends,
> I wanted to know how to calculate the gate count in a FPGA design. If
> there is any article regarding it, do mention. If you can give an
> example it will be great.
>
> wiating for your reply
> Praveen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55619> Google for "Parallel Cable III" (with quotes) and you'll find a lot of > info. I built one to their specs but I haven't built a proto board for > the XC9536 to try it yet. I actually built it myself, along with a small test board. Tested with ISE WebPack 5.2 on Windows 2000, misteriously not working with WP4.2 and Win98. Tested devices are 9536XL and 9572XL (3.3V devices); should work with any 5V device too. http://spazioinwind.libero.it/valeriogionco/JTAG_cable.tar.gz http://spazioinwind.libero.it/valeriogionco/CPLD_test_board.tar.gz Included are source Eagle files (www.cadsoft.de) and Postscript output. Let me know if you need help.Article: 55620
Pete, Yes, Synthesizers know how to construct carry chains, etc. However, Jake knows where the mux should go. When you infer a mux, you have little control over where it goes and its more difficult and less readable to attach an RLOC to that 'inferrence'. The place and route tools haven't gotten all that smart and, despite timing constraints, area_group placement constraints, etc, they still place something 5 CLBs away from where it should go! (and thus not making timing). I took a short hiatus from FPGAs and returned hoping that the rumors I'd heard about the tools were correct -- they had gotten smarter. Unfortunately, it appears they'd gotten just smart enough to make people believe they could rip away certain features but not smart enough to justify the absence of those features. It's really unfortunate, too, because structural HDL with those nice primitives is a tolerable alternative to the worst-schematic-entry-tool-ever, ECS. What amazes me is that ECS somehow knows how to build a M2_1 out of the real primitives so it seems Xilinx has some QA and maintenance over those blocks -- why not just HDL them and let XST use 'em? Cheers, Jake "Pete Dudley" <pete.dudley@comcast.net> wrote in message news:<Ax-dnSERrd0XVVyjXTWcqQ@comcast.com>... > Jake, > > I think you are right. XST no longer supports the direct instantiation of > the M2_1 primitive. The libraries guide states "For HDL, this design element > is inferred rather than instantiated". > > This is probably a good thing to avoid now anyway. Synthesizers know how to > construct carry chains and when to use block multipliers. Where I work we > have built up a library of synthesizable, parametized elements. This lets us > code in a structural style when we want but the library is architecture > independent so our code is portable except for proprietary elements like > block rams. > > There should really be a public domain library like this but I haven't found > one. > > -- > Pete Dudley > > Arroyo Grande Systems > > "Jake Janovetz" <jakespambox@yahoo.com> wrote in message > news:d6ad3144.0305132010.7e425ff1@posting.google.com... > > Folks- > > > > How does one instantiate the schematic primitives in XST -- or is this > > even possible now? Let's say I want a M2_1 (2-1 mux). The 'unisims' > > directory of the Foundation toolset doesn't include these > > 'primitives'. Rather, it includes things such as LUTs. > > > > Of course, I can instantiate a LUT with the proper init values, but it > > would go a long way in readability not to mention "error protection" > > to have the MUX available as a primitive. > > > > This goes for all the other less-primitive blocks such as ACC1(4/8/16) > > and so on. Are these just not available in XST as blocks? > > > > JakeArticle: 55621
praveenkumar1979@rediffmail.com (praveen) wrote in message news:<ff8a3afb.0305140150.8b9ecb5@posting.google.com>... > hi Sir/Friends, > I wanted to know how to calculate the gate count in a FPGA design. If > there is any article regarding it, do mention. If you can give an > example it will be great. > > wiating for your reply > Praveen Today FPGA gate count numbers are used exclusively by marketing. This numbers has almost no sense from the (modern) FPGA designer's point of view. Use more reasonable characteristics like LC count, meemory bits/blocks, HW multipliers/ DSP blocks etc... All this things are not interchangable so there is no point in summing them together under gate count moniker. May be back in old days, when FPGAs had local cells and nothing more, gate count numbers made some sense... No more.Article: 55622
Hi Jake, You may want to take a look at the Xilinx software manual -> Libraries Guide -> Design Elements. M2_1 is a macro. You'll be able to located this element and find exemple code to infer it. http://toolbox.xilinx.com/docsan/xilinx5/manuals.htm Regards, Wei Jake Janovetz wrote: > Folks- > > How does one instantiate the schematic primitives in XST -- or is this > even possible now? Let's say I want a M2_1 (2-1 mux). The 'unisims' > directory of the Foundation toolset doesn't include these > 'primitives'. Rather, it includes things such as LUTs. > > Of course, I can instantiate a LUT with the proper init values, but it > would go a long way in readability not to mention "error protection" > to have the MUX available as a primitive. > > This goes for all the other less-primitive blocks such as ACC1(4/8/16) > and so on. Are these just not available in XST as blocks? > > JakeArticle: 55623
khankalimuddin@yahoo.com (Khan) wrote in message news:<51e963d.0304280512.340cb61c@posting.google.com>... > Hi Gurus, > > I am doing project on developing LDPC coder and decoder using Xilinx > FPGA. Any help as far as material links and VHDL code will be highly > appreciated. > > > Thanking you in advance, > > > Khan We just uploaded an LDPC decoder/corrector to opencores yesterday. It is a fully parallel implementation of Gallager's algorithm "A", so its synthesis quality and error correction performance may not be practical. But it does serve as an excellent starting point for more elaborate decoding architectures. The Verilog, VHDL, and C are located here: http://www.opencores.org/projects/cf_ldpc/ The Confluence source code is located here: http://www.launchbird.com/freeip.html Hope this helps. Regards, Tom -- Tom Hawkins Launchbird Design Systems, Inc. 952-200-3790 tom1@launchbird.com http://www.launchbird.com/Article: 55624
With synplify you can use the xc_map attribute to essentially do what fmaps used to do. To do so, the
inferred M2_1 has to be in a separate component so that you can put an RLOC on the component instance. I
pasted in the 2:1 mux from our fmap_logic.vhd file at the bottom of this post. I'm not sure if XST has
a similar attribute or not. That said, as long as you have only one layer of logic between flip-flops,
the placer should put the LUT in the slice with the flip-flop so you should be able to just place the
flip-flop and let the placer do the rest. Another option is to write a boolean string parser that
converts a boolean string to a LUT INIT= string which you then put on both the LUT INIT generic and the
attribute (synplify will now read the generic and generate the attribute automatically, I don't believe
XST does that yet).
--FMAP'd 2:1 mux
library IEEE;
use IEEE.std_logic_1164.all;
entity fmap_mux2 is
port ( d0,d1,s : in std_logic;
z : out std_logic);
end fmap_mux2;
architecture rtl of fmap_mux2 is
attribute xc_map : STRING;
attribute xc_map of rtl : architecture is "lut";
attribute syn_hier: string;
attribute syn_hier of rtl:architecture is "hard";
begin
z <= d0 when s='0'
else d1;
end rtl;
---------------------------------------------------------------------------------------------
Jake Janovetz wrote:
> Pete,
>
> Yes, Synthesizers know how to construct carry chains, etc. However,
> Jake knows where the mux should go. When you infer a mux, you have
> little control over where it goes and its more difficult and less
> readable to attach an RLOC to that 'inferrence'.
>
> The place and route tools haven't gotten all that smart and, despite
> timing constraints, area_group placement constraints, etc, they still
> place something 5 CLBs away from where it should go! (and thus not
> making timing). I took a short hiatus from FPGAs and returned hoping
> that the rumors I'd heard about the tools were correct -- they had
> gotten smarter. Unfortunately, it appears they'd gotten just smart
> enough to make people believe they could rip away certain features but
> not smart enough to justify the absence of those features.
>
> It's really unfortunate, too, because structural HDL with those nice
> primitives is a tolerable alternative to the
> worst-schematic-entry-tool-ever, ECS. What amazes me is that ECS
> somehow knows how to build a M2_1 out of the real primitives so it
> seems Xilinx has some QA and maintenance over those blocks -- why not
> just HDL them and let XST use 'em?
>
> Cheers,
> Jake
>
> "Pete Dudley" <pete.dudley@comcast.net> wrote in message news:<Ax-dnSERrd0XVVyjXTWcqQ@comcast.com>...
> > Jake,
> >
> > I think you are right. XST no longer supports the direct instantiation of
> > the M2_1 primitive. The libraries guide states "For HDL, this design element
> > is inferred rather than instantiated".
> >
> > This is probably a good thing to avoid now anyway. Synthesizers know how to
> > construct carry chains and when to use block multipliers. Where I work we
> > have built up a library of synthesizable, parametized elements. This lets us
> > code in a structural style when we want but the library is architecture
> > independent so our code is portable except for proprietary elements like
> > block rams.
> >
> > There should really be a public domain library like this but I haven't found
> > one.
> >
> > --
> > Pete Dudley
> >
> > Arroyo Grande Systems
> >
> > "Jake Janovetz" <jakespambox@yahoo.com> wrote in message
> > news:d6ad3144.0305132010.7e425ff1@posting.google.com...
> > > Folks-
> > >
> > > How does one instantiate the schematic primitives in XST -- or is this
> > > even possible now? Let's say I want a M2_1 (2-1 mux). The 'unisims'
> > > directory of the Foundation toolset doesn't include these
> > > 'primitives'. Rather, it includes things such as LUTs.
> > >
> > > Of course, I can instantiate a LUT with the proper init values, but it
> > > would go a long way in readability not to mention "error protection"
> > > to have the MUX available as a primitive.
> > >
> > > This goes for all the other less-primitive blocks such as ACC1(4/8/16)
> > > and so on. Are these just not available in XST as blocks?
> > >
> > > Jake
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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