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Why bother getting the micro to save the rest ?? Why not use a Maxim temperature switch & a FET which will simply shut off the power at the critical moment ?? MAX6501/2 comes to mind. It could either just shut down to power to the whole board and repower it again when the temperature drops, a second device at a lower temperature could warm the processor or it could measure the temp with a ADC input. This way nothing but the temp sensor and the on/off FET is powered at high temp. Simon "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3EAC5618.563F@designtools.co.nz... > rickman wrote: > > > > All this talk about low pin count FPGAs got me thinking about my current > > problem. I am looking for a small collection of board supervisory and > > control funtions that I can't seem to find in a single chip. I can't > > even get them in two or three chips since my combination of inputs for > > power control and reset are not common. > > > > So I thought about using one of the more recent, very small 8 bit micros > > to become a "super" supervisor and provide signals such as reset and > > power enable along with a RTC and temperature shutdown. Even > > considering that this will require using software, I think it will be > > the simplest, smallest and cheapest solution available. > > > > The only problem is, I am having a hard time finding the "right" 8 bit > > micro. This circuit needs to operate in temps of -40 to 125C. The rest > > of the board will only be rated for 85C and this circuit will shut off > > all power to the board to prevent damage from running above 85C. Seems > > there are some places in the world that get pretty durn hot. The inside > > of a locomotive sitting in a tunnel is one of them. > > > > So can anyone recommend a small, cheap, very low power MCU that will > > operate over -40 to 125C, has flash (OTP might be ok), RTC (software is > > ok if power level is very low), and can measure the temperature? I > > originally was going to use a 1% thermistor on an ADC, but all the ADC > > inputs are now taken. I guess the (small, cheap, simple) way to do the > > temperature is to just pick a resistor value that will give me a trip > > point, but then that requires a comparitor and a vref. > > > > I looked at the TMS430 and Cygnal parts and did not find anything that > > is rated to run over that temp range. The Fairchild ACE MCUs come in an > > automotive range, but have too few IOs, I need about 10 that I know of. > > > > I am not really up to date on automotive temp MCUs and not so current > > with the 8 bit MCUs either. I guess I will take a look at Motorola and > > Microchip next. I am getting to hate the web... > > Max temperature specs are a bit of a briar-patch. > > Vendors quote a Ta, when what they really worry about is Tj. > I suspect they are trying to simplify things for the customer, > but any uC designer can manage a thermal eqn :) > > Newer devices that push the TMAX up, are starting to quote Tj with > correct Thermal resistances ( just like power devices use ). > ABS-MAX Tj has not moved much, but they can push up their Ta MAX > quite a bit using this approach. > > Cygnal spec a ABS MAX of 125'C, and commit to functional > spec within -40-85'C so I'd talk with them to clarify what > happens 85'C to 125'C. > They do have on chip temperature reading, and do use a > low-thermal-resistance MLF package, and it also sounds > like you are running low clocks, so will have very low > thermal adders. > It also sounds like your > 85'C is not a long-term usage > need, but just an extreme case coverage, > to protect other devices from going above their ABS MAX Tj ? > > It's the same as SMD power device problems :- lower chip power, > and lower package thermal resistance mean higher tolerable ambients. > > -jgArticle: 55126
I using VirtexII to controll DDR SDRAM , i found some VGA card that it's DDR SDRAM is not using Vtt terminator , only series resistor ,is Vtt not necessary? Thanks ! ZhangArticle: 55127
dear sir/friends, I want to know how an Vhdl code of Counter is being mapped to FPGA. Any article regarding it will be very good. waiting for reply praveenArticle: 55128
Anyone know how to "lock" the on-board flash memory from Software on a NIOS Development board? I'm using the NIOS Stratix 1S10 devkit and would like to make the flash read-only during normal software execution. When my software app enters special modes (like software reflash, reconfiguration, etc.) I'd like make the flash read-write. There's a data sheet for most of the SOPC components for NIOS, but not for Flash, nor Ethernet (LAN91C111 registers for example). JimArticle: 55129
Mike Treseler <mike.treseler@flukenetworks.com> writes: > The documentation was very good. [...] > but having the source proved essential for system integration. This sounds a bit like a contradiction since you should be able to treat a core like a black box. Or do you mean the source of the test bench or a sample application? Cheers, ColinArticle: 55130
Zhang, Many people simulate their particular design with their chosen parts, and simplify the IO standard and achieve their desired performance. The only caution here is that going with a standard is a 'guarantee by design', as opposed to a design that has been verified and guaranteed by the engineer designing it. Austin zhang wrote: > I using VirtexII to controll DDR SDRAM , > i found some VGA card that it's DDR SDRAM is not using Vtt terminator , > only series resistor ,is Vtt not necessary? > Thanks ! > ZhangArticle: 55131
Jonathan Kirwan wrote: > > On Thu, 24 Apr 2003 22:04:31 -0400, rickman > <spamgoeshere4@yahoo.com> wrote: > > ><snip> > >This circuit needs to operate in temps of -40 to 125C. > > I know someone currently using the TI MSP430F149's at elevated > temperatures, in production. They are used in an environment > which operates at an ambient in the 150 C to 175 C temp range. > (The tougher part, I'm told, was finding batteries to operate > well, in that range.) Just a data point. > > Jon Yes, I am aware of the battery problem. But I am working on that. I have found a primary cell that will work in that range. I just don't know if it has the right mounting tabs or if I can buy it in small quantities (100's). The commercial temp board will have a small rechargable battery where it won't block any other options. The primary cell will potentially block a daughter card site. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55132
Hi, I'm using a APEX20KE device and Quartus 2, and I have some difficulties to drive a general IO and a FAST output directly from a dedicated clock input pin (CLKx). Ideas anyone? Thanks, Stein KArticle: 55133
Hello, I simulate a design with a ppc405 smartmodel from xilinx. I use the following vhdl simulators : ncsim from cadence scirocco from synopsys riviera from aldec I learned in the embedded systems development class from xilinx that it is possible to trace internal registers of the ppc405 and display them with a waveform viewer; at least if one uses the modelsim simulator. I did not succeed to trace any internal registers of the ppc405 using one of the simulators mentioned above. Has anybody used one of this simulators to simulate a design with a ppc405 smartmodel and was able to trace the internal registers ? RobertArticle: 55134
Simon wrote: > > Why bother getting the micro to save the rest ?? > > Why not use a Maxim temperature switch & a FET which will simply shut off > the power at the critical moment ?? MAX6501/2 comes to mind. It could > either just shut down to power to the whole board and repower it again when > the temperature drops, a second device at a lower temperature could warm the > processor or it could measure the temp with a ADC input. This way nothing > but the temp sensor and the on/off FET is powered at high temp. > > Simon That is an easy question to answer. The space is limited (as well as the cost). Due to the issues of testing mainly, I can get a single MCU to do all the tasks I need rather than to use one or two temp sensors along with an ADC along with random logic to shutdown the board and hold the processors in reset, etc... Once I have a temperature measurement along with the various voltage measurements and the intelligence of a micro, I can make the board do anything I want and even have different modes using the MCU EEPROM rather than jumpers! NO JUMPERS!!! Isn't that great? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55135
Hallo, i have a short question. I have to use I/O´s with LVDS-Standard. Therfore I must combine two Pins to one Signal. When I insert a pin and define it for LVDS, how can i combine this one with the second. Or think i absolutly wrong in it? Thanx a lot...Article: 55136
Hi Vaughn, I'm aware of the datapath's of NIOS but I was referring to the instruction size. You can always get more information into 32-bit than into 16-bit. With 32-bit instructions, you can do 3-operand instructions and with 16-bits instruction, you can only do 2-operand instructions. You can easily get in 16-bit immediate values in one instruction where you need more instructions for doing the same in a 16-bit instructions. So, with MicroBlaze, you will need less instructions for your code than NIOS. Simple as that. So even if MicroBlaze and NIOS was running at the same speed MicroBlaze would be doing more for each clock cycle and thus have more performance. For the LUT count, it's actually simpler to decode 32-bit instructions than 16-bit instructions. You have more bits to for describing the instruction and can easily lay out the coding so that they directly fits the datapath. Many units in the MicroBlaze datapath has it's control signal directly from the instruction word. With 16-bit, you need to squeeze in more information in less bits and therefore logic is needed for decoding the control bits for datapath. MicroBlaze is smaller than NIOS, isn't that proof enough. So for soft processor, it's much better to use 32-bit than 16-bit for minimizing the area size. Göran Vaughn Betz wrote: > Goran, > > Nios is configurable to use either a 16-bit or a 32-bit datapath. The > version Jim has created has a 32-bit datapath. > > You seem to be confusing datapath width with instruction encoding > length. Using 32-bit instructions instead of 16-bit gives you more > space to encode more instructions, but costs you cache efficiency, and > decode logic area. The extra op-code space also doesn't gain you much > if you don't have the need for the extra instructions, or the room to > build more function units that would execute the stranger opcodes > (likely the case in a soft processor). Whether 32-bit vs. 16-bit > instruction encoding is best is a tough question in embedded > processors, and there is no general rule -- SH-RISC is 16-bit, > ARM-thumb is 16, while ARM regular is 32, PowerPC is 32 and so on. > I'd say it's an even more open question in soft processors, given the > relatively higher cost of logic in FPGAs vs. that of embedded > processors built using standard cells or even custom layout. > > If a longer instruction length was simply better, we'd all be using > 64-bit instruction encodings, but nobody is. > > Which processor gets more work done in a given clock period is of > course a complex function of the cache / memory subsystem, processor > pipeline, and instruction set. The only way to measure what system > gets more work done per unit time is to use real benchmark programs. > > As for clock speed, it's hard to compare unless you have exactly the > same system. I know that the NIOS 32-bit core runs above 125 MHz in a > Stratix, -5 speed grade (got it right in front of me). De-rating for > the -6 speed grade Jim is using would let him run at 114 MHz or so > that in speed grade. So the critical path Jim is seeing is outside > the core somewhere. If it's in the "custom logic interfaces" Jim > built, there's no real way to compare speeds without building the > exact same system in another chip, and to do that you'd need Jim's > design. > > Vaughn Betz > > Goran Bilski <Goran.Bilski@Xilinx.com> wrote in message news:<3EA5EACB.318D5B85@Xilinx.com>... > > Hi Jim, > > > > I tried to create something similar using MicroBlaze and V2Pro > > The design has > > - MicroBlaze > > - 8Kb of onchip memory > > - Two External memories like flash and sram > > - lcd, led and button interface > > - One Uart > > - Two 32-bit timers > > - One Ethernet MAC > > > > My computer is a P3-900 Mhz with 512 MB of memory. > > > > The target device is a xc2vp4, package fg256, speed -6 > > I put a constraint on the clock for 120 MHz. > > It took the place and route tool (par) 8 min to get to that speed. > > Since MicroBlaze has 32-bit instructions (NIOS has 16-bit) and can therefore do more for each > > instruction, the actual performance should be higher even if the clock frequency is the same. > > > > Göran > > > > "Jim M." wrote: > > > > > Well, I've finished up a couple NIOS designs and here's the Fmax > > > values I obtained for a couple configurations: > > > > > > SETUP 1 -- 90 MHz (1S10-C6ES), slack +500ps > > > 32-bit NIOS CPU without instruction/data cache and with button input, > > > led output, lcd output, sram, flash, ethernet, 1 uart, 1 dma, and some > > > custom logic interfaces. This design had a positive slack time of > > > nearly 500 ps suggesting that 95 MHz is probably possible. I tried > > > 100 MHz and had a negative slack time of nearly 500 ps. > > > > > > SETUP 2 -- 90 MHz (1S10-C6ES), slack +50ps > > > Same as #1 with addition of SDRAM controller. > > > > > > No LogicLock regions used in design. > > > > > > In addition, I still experience a repeated fast fit during compilation > > > in Quartus. I'm not sure why this happens, but it occurs after any > > > change to the design. The first compile after a change results in a > > > database build, logic synthesis (using previous fitter results from > > > database), then a repeated fast-fit. I let one of these fast-fit > > > sessions run itself out and it took about 11 hours. It built up > > > 100-200 entries in the database. I received some pretty nice results > > > due to the 11 hour build. > > > > > > Now when I see the repeated fast-fit occurring, I stop the build after > > > the first fit then re-build. The rebuild skips the database builder > > > and logic synthesizer (since smart compile is enabled) and performs a > > > final fit (not fast-fit). > > > > > > I thought I'd post my final results. > > > > > > jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0304141222.15bf1ca8@posting.google.com>... > > > > I recently purchased a NIOS Stratix 1S10 Development Kit from Altera > > > > and have mixed feelings about Quartus, SOPC Builder, and the NIOS > > > > Core. (For those poor souls interested, I've included some comments > > > > at the end of this post... feel free to provide feedback.) > > > > > > > > However, here's my question: > > > > > > > > What's the maximum clock frequency anyone has achieved using the NIOS > > > > 3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM, > > > > Ethernet, PIO, UART, etc. as in the Reference Design provided by > > > > Altera)? > > > > > > > > I've tried isolating the various components into LogicLock regions. > > > > I've tried different fitter/netlist optimizations. The maximum Fmax I > > > > have achieved to date is 80 MHz. This is after letting Quartus "fit" > > > > for 10 hours... it actually didn't stop, I had to abort the fitting > > > > and refit to finially get an interim result (see other misc comments > > > > below). > > > > > > > > Altera advertises 125 MHz for the Stratix Device and NIOS 3.0... > > > > However a reference design that builds at that clock rate is not > > > > provided. It appears that Altera gives you just enough to get your > > > > feet wet... anything above and beyond that is Intellectual Property > > > > that you need to buy. > > > > > > > > Other Observations/Comments: > > > > > > > > 1. The Quartus II SP1 software is extremely flakey. I've generated > > > > numerous faults when deleting/modifying child LogicLock Regions. It > > > > also takes forever to fit my Stratix design which is only 6000 LEs. > > > > If I select the "limit fitting attempts to 1" option, Quartus > > > > sometimes fits many times (like forever...) why?!?!? Also, after a > > > > design is finished building, the software sits around for up to 5 > > > > minutes before it generates a "finished" dialog box. I'm not sure > > > > what's going on between the Quartus Application thread and the Quartus > > > > Compiler thread, but it's fustrating enough just waiting for the > > > > design to build, let alone waiting for Quartus to figure out the build > > > > is done. I could go on and on, and that's only the result of 4 weeks > > > > of effort with a small design. I feel sorry for those folks working > > > > on a 100,000+ gate design. I guess modularity is the key there. > > > > > > > > 2. I can't simulate designs with virtual pins. I get warning during > > > > the analysis of the simulation and then receive results with all input > > > > pins a zero and output pins undefined. In addition, I can generate > > > > hold time warnings during simulation for a design that didn't compile > > > > with any hold time warnings. I'm not talking about hold time warnings > > > > on my input signals, I'm talking about hold time warnings on internal > > > > registers in my verilog code. Registers that I've taken care to hold > > > > for 1 or more clock cycles before using in other parts of the design. > > > > Again, the compilation of the design did not generate hold time > > > > warnings... only the simulation of the design. > > > > > > > > 3. PLLs generate different timing analysis results. THIS IS VERY > > > > ANNOYING! When I build up a "black-bock" design with virtual pins I > > > > obtain a Fmax calculation from the timing analysis routine. I then > > > > LogicLock the design and export it. When I import the design into a > > > > new project and clock it using a PLL it generates negative slack time > > > > warnings! If I remove the PLL and replace it with a clock pin, I get > > > > the Fmax result that I obtained during the "black box" design. I beat > > > > myself up for a week trying to debug a design that wasn't broken > > > > because of this goofy behavior in Quartus. I'm still not sure if the > > > > slack time warning it legit and wether I should be concerned about it. > > > > > > > > 4. SOPC Builder will lock itself up if you double-click components > > > > before selecting them. Give it a try... double click a component line > > > > in your NIOS design before selecting the line item. After a couple > > > > times the SOPC builder application creeps to a halt. > > > > > > > > 5. Documentation on the various megafunctions is lacking. A good > > > > example is the altsyncram megafunction. It doesn't state any timing > > > > requirements on the input registers, enable, and clock signals. Do I > > > > hold the data 1 cycle before flipping the write enable? How about > > > > holding the write enable before de-activating it? Why is the > > > > addressing based upon the data bit-width? Trying to tie a 32-bit > > > > altsyncram block to a NIOS CPU is difficult because you need to > > > > specify the address space of the peripheral and the address space of > > > > the altsyncram block is based upon the bit width (not the number of > > > > bytes). > > > > > > > > 6. I have yet to get a Leonaro-Spectrum synthesized Verilog file to > > > > build in Quartus. I can used Spectrum generated .edf files but not > > > > verilog. I get LCELL parameter errors. Unfortunately, Altera can't > > > > seem to duplicate this... anyone else see this behavior? I'm not sure > > > > if Spectrum synthesizes Verilog better that Quartus, but it definitely > > > > does it faster. > > > > > > > > Feedback is welcome... even if it's the "you're an idiot and here's > > > > why" variety...Article: 55137
My first thought is to do this by table-look-up. Depends on the chip you are using Pter Alfke, Xilinx Applications Steve wrote: > > Hello all, > I am in desperate and urgent need of help here. Thanks to my poor > programming skill, I've been almost sleepless for days trying to come > up with ABEL source code for a 4 bit Multiplier and Divider. Can > anyone provide any kind of help? > Grateful, > SteveArticle: 55138
Hi All: I have a bit of a problem using the FLEX 10k's bidir port. My project interfaces to a static ram on which I want to program a clock pattern, then 'play' it back. The problem is I can't seem to program the correct values into the static ram. I'm pretty sure I'm using the static ram correctly, so I think my problem lies in my use of the bidir and bidirc primitives. I can't seem to find any good docs that explicitly tell me how to use these things. From what I can see I do not actively change them from input to output, but have to make sure my external devices on the bus do not contend with one another. I'm sure this assumption is wrong. I was wondering if somone might know of some docs I can read, or some good advise on use of the bidir and bidirc ports on a FLEX10k class pga. Thanks -- Andrew Tubbiolo enigma at seds dot lpl dot arizona dot edu This is for spambots don't use .... webmaster@phhhht.orgArticle: 55139
Colin Marquardt wrote: > Mike Treseler <mike.treseler@flukenetworks.com> writes: >>The documentation was very good. > [...] >>but having the source proved essential for system integration. > > This sounds a bit like a contradiction since you should be able to > treat a core like a black box. I added a new capability to the core because of a change in our requirements. -- Mike TreselerArticle: 55140
To understand Bidirectional description (in VHDL), GOTO http://www.amontec.com/fix/core/amt_hdl_util/amt_hdl_utilindex.htm and check the components amt_c_bidir or amt_c_bidir_vect or amt_c_bidir_gio Amontec Team www.amontec.com Andrew Tubbiolo wrote: > Hi All: > > I have a bit of a problem using the FLEX 10k's bidir port. My project > interfaces to a static ram on which I want to program a clock pattern, then > 'play' it back. The problem is I can't seem to program the correct values into > the static ram. I'm pretty sure I'm using the static ram correctly, so I think > my problem lies in my use of the bidir and bidirc primitives. I can't seem to > find any good docs that explicitly tell me how to use these things. From what > I can see I do not actively change them from input to output, but have to make > sure my external devices on the bus do not contend with one another. I'm sure > this assumption is wrong. I was wondering if somone might know of some docs I > can read, or some good advise on use of the bidir and bidirc ports on a FLEX10k > class pga. > > > ThanksArticle: 55141
On Mon, 28 Apr 2003 11:04:57 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Jonathan Kirwan wrote: >> >> On Thu, 24 Apr 2003 22:04:31 -0400, rickman >> <spamgoeshere4@yahoo.com> wrote: >> >> ><snip> >> >This circuit needs to operate in temps of -40 to 125C. >> >> I know someone currently using the TI MSP430F149's at elevated >> temperatures, in production. They are used in an environment >> which operates at an ambient in the 150 C to 175 C temp range. >> (The tougher part, I'm told, was finding batteries to operate >> well, in that range.) Just a data point. >> >> Jon > >Yes, I am aware of the battery problem. But I am working on that. I >have found a primary cell that will work in that range. I just don't >know if it has the right mounting tabs or if I can buy it in small >quantities (100's). If I recall, he's found a battery which will operate at over 225 C. I think he told me it was originally for military use. But is available commercially. I don't recall who makes it, but I could always ask. He's using small quantities, as well. JonArticle: 55142
in VHDL you code it like:
...
port (
d : inout std_logic_vector(7 downto 0);
...
case state is
when idl =>
-- tri state
d <= "ZZZZZZZZ";
when wr =>
-- drive data on bus
d <= wr_reg;
when rd =>
-- read data
in_reg <= d;
...
hope this helps,
Martin
--------------------------------------------------------
JOP - a Java Processor core for FPGAs now
on Cyclone: http://www.jopdesign.com/cyclone/
"Andrew Tubbiolo" <enigma@seds.org> schrieb im Newsbeitrag
news:b8jnj7$5fq$1@oasis.ccit.arizona.edu...
> Hi All:
>
> I have a bit of a problem using the FLEX 10k's bidir port. My project
> interfaces to a static ram on which I want to program a clock pattern,
then
> 'play' it back. The problem is I can't seem to program the correct values
into
> the static ram. I'm pretty sure I'm using the static ram correctly, so I
think
> my problem lies in my use of the bidir and bidirc primitives. I can't seem
to
> find any good docs that explicitly tell me how to use these things. From
what
> I can see I do not actively change them from input to output, but have to
make
> sure my external devices on the bus do not contend with one another. I'm
sure
> this assumption is wrong. I was wondering if somone might know of some
docs I
> can read, or some good advise on use of the bidir and bidirc ports on a
FLEX10k
> class pga.
>
>
> Thanks
> --
> Andrew Tubbiolo
> enigma at seds dot lpl dot arizona dot edu
>
> This is for spambots don't use ....
> webmaster@phhhht.org
>
Article: 55143The Altera PCI32 Target daughtercard doesn't seem to be compatible with the Cyclone NIOS board. The Cyclone NIOS board doesn't have the same connectors as the older Apex NIOS this daughtercard was designed for. Correct me if I'm wrong, Altera. Any other vendors out there working on a Cyclone PCI board? I'm looking for a PCI host version that would fit into a PICMG passive PCI backplane. That's asking for a lot, but it doesn't hurt to ask. BTW, is anyone out there using the Cyclone 1C3 in a PCI application? It doesn't have PCI buffers, but I'm wondering if anyone has worked around this issue. Thanks. > "Paul Leventis" <paul.leventis@utoronto.ca> ha scritto nel messaggio > news:SY8qa.141485$BQi.97105@news04.bloor.is.net.cable.rogers.com... > > Hi Mike, > > > > One product Altera offers is the PCI32 Nios Add-on Dev Kit. This is a > board > > that you hook-up to any Nios dev kit (including the Cyclone version), and > > you can plug it into a PCI32 slot. It provides a PCI interface to your > Nios > > dev board, an API, etc. I don't know anything about it besides what's on > > our web site. > > > > You can read about it here: > > > > http://www.altera.com/products/devkits/altera/kit-dev_nios_pci32.html > > > > - Paul > > > > "mike" <mxv@yahoo.com> wrote in message > > news:8ea508fe.0304242036.224f0c6e@posting.google.com... > > > I've searched the web with no luck for a PCI development board with > > > using an Altera Cyclone part. Probably because it's a new part, but if > > > anyone knows where I can find one, please post a link. It must be > > > Cylone, and it can be a PCI board or PMC module. > > > > > > Thanks in advance. > > > >Article: 55144
Jonathan Kirwan wrote: > On Mon, 28 Apr 2003 11:04:57 -0400, rickman > <spamgoeshere4@yahoo.com> wrote: > > >>Jonathan Kirwan wrote: >> >>>On Thu, 24 Apr 2003 22:04:31 -0400, rickman >>><spamgoeshere4@yahoo.com> wrote: >>> >>> >>>><snip> >>>>This circuit needs to operate in temps of -40 to 125C. >>> >>>I know someone currently using the TI MSP430F149's at elevated >>>temperatures, in production. They are used in an environment >>>which operates at an ambient in the 150 C to 175 C temp range. >>>(The tougher part, I'm told, was finding batteries to operate >>>well, in that range.) Just a data point. >>> >>>Jon >> >>Yes, I am aware of the battery problem. But I am working on that. I >>have found a primary cell that will work in that range. I just don't >>know if it has the right mounting tabs or if I can buy it in small >>quantities (100's). > > > If I recall, he's found a battery which will operate at over 225 > C. I think he told me it was originally for military use. But > is available commercially. I don't recall who makes it, but I > could always ask. He's using small quantities, as well. Electrochem makes batteries for downhole electronics. I have a pair of their C cell lithiums that are good to 150C. About $100 each many years ago.Article: 55145
Hi Jens, > > i have a short question. I have to use I/O´s with LVDS-Standard. > Therfore I must combine two Pins to one Signal. When I insert a pin > and define it for LVDS, how can i combine this one with the second. Or > think i absolutly wrong in it? The method is to just declare the actual signal, and tell Quartus that it uses LVDS as the I/O standard (use the Assignment Organizer for this). Quartus will then automatically pick two adjacent pins to implement the signal. Best regards, BenArticle: 55146
Hmmm... I tend to write it as follows: datain <= d; d <= dataout when (writing) else (OTHERS => 'Z'); This pretty literally describes the I/O buffers, and this immediately splits the bidir bus into its input and output counterparts. The (writing) expression could of course be anything. Best regards, Ben "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:slfra.64520$v62.689926@news.chello.at... > in VHDL you code it like: > ... > port ( > d : inout std_logic_vector(7 downto 0); > ... > case state is > > when idl => > -- tri state > d <= "ZZZZZZZZ"; > when wr => > -- drive data on bus > d <= wr_reg; > when rd => > -- read data > in_reg <= d; > ... > > hope this helps, > Martin > > -------------------------------------------------------- > JOP - a Java Processor core for FPGAs now > on Cyclone: http://www.jopdesign.com/cyclone/ > > "Andrew Tubbiolo" <enigma@seds.org> schrieb im Newsbeitrag > news:b8jnj7$5fq$1@oasis.ccit.arizona.edu... > > Hi All: > > > > I have a bit of a problem using the FLEX 10k's bidir port. My project > > interfaces to a static ram on which I want to program a clock pattern, > then > > 'play' it back. The problem is I can't seem to program the correct values > into > > the static ram. I'm pretty sure I'm using the static ram correctly, so I > think > > my problem lies in my use of the bidir and bidirc primitives. I can't seem > to > > find any good docs that explicitly tell me how to use these things. From > what > > I can see I do not actively change them from input to output, but have to > make > > sure my external devices on the bus do not contend with one another. I'm > sure > > this assumption is wrong. I was wondering if somone might know of some > docs I > > can read, or some good advise on use of the bidir and bidirc ports on a > FLEX10k > > class pga. > > > > > > Thanks > > -- > > Andrew Tubbiolo > > enigma at seds dot lpl dot arizona dot edu > > > > This is for spambots don't use .... > > webmaster@phhhht.org > > > >Article: 55147
Hi Jim, I don't have them handy right now, but I suggest that you browse to the EP1S10 schematic when it's running its web server demo, and look at how the Flash is connected to the Stratix. If I'm not mistaken, the Flash is a fairly standard AMD-compatible flash. Find the WE pin on the Flash, and see if someone had the foresight to connect it to the FPGA through a jumper or not. If not, there's no way you can protect the Flash without de-soldering the WEn pin, wiring it up to a jumper or switch, and wiring the other end back to the pad. The idea is that, as long as the WEn pin is not pulled to 0V, it's impossible to write into the Flash. This has to be done externally, as there is no other way you can 100% guarantee that your design will not happen to accidentally pull the signal low, attempt to write to the magic addresses etc, etc otherwise. The reason why there are no datasheets for the external components is that they are property of the companies producing the parts and that, as the original documentation states, reproduction of the documentation is (lawyerese translated to laymen's terms) a hassle. A simple web search should supply you with the proper datasheets though. Best regards, Ben "Jim M." <jim006@att.net> wrote in message news:6f3fc0f8.0304280540.54d5b99@posting.google.com... > Anyone know how to "lock" the on-board flash memory from Software on a > NIOS Development board? > > I'm using the NIOS Stratix 1S10 devkit and would like to make the > flash read-only during normal software execution. When my software > app enters special modes (like software reflash, reconfiguration, > etc.) I'd like make the flash read-write. > > There's a data sheet for most of the SOPC components for NIOS, but not > for Flash, nor Ethernet (LAN91C111 registers for example). > > JimArticle: 55148
Hi Stein, > I'm using a APEX20KE device and Quartus 2, and I have some > difficulties to drive a general IO and a FAST output directly from a > dedicated clock input pin (CLKx). Ideas anyone? I'm afraid there is no way I know to drive a general-purpose I/O pin directly from a clock net in an Apex. The trick I generally use is to take 2 TFFs. One toggles on the rising edge of the clock, the other one on the falling edge. XOR the outputs of the 2 TFFs, and this will give you a signal that toggles at the same speed as the input clock. Depending on your reset condition you may need to invert it to match clock phase. If you pack this 3-LE block into a single LAB that is next to the I/O pad that needs to feed the signal out (you can either use LogicLock, a Custom Region or even direct LAB assignments for this) you'll have an almost 50% duty cycle and very little jitter on the resulting signal. The skew depends on where the output is relative to the input clock pin location, but it will generally be in the <1ns range unless you're really crossing a big device. Best regards, BenArticle: 55149
References: <39b51bc5.0301091523.2819b08e@posting.google.com> <3E1E2306.781A@designtools.co.nz> <OCqT9.900$CZ6.635@newssvr16.news.prodigy.com> <39b51bc5.0301100933.1c71cd53@posting.google.com> Virtex 2 Pro is not available as a -4. A -4 V2 is cheaper then a -5 V2P, which you are forced to buy, even if you don't need the speed.
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