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Matt, I obviously cannot speak for Cyclone, but I would just artificially reduce the output drive of the FPGA. In Virtex you can go down to 2 mA guaranteed drive ( of course higher worst case) and even better, you can implement the on-chip serial termination, which gives you a 50 Ohm output impedance (guaranteed). I have heard a rumor that Cyclone has similar capabilities... Then you can just laugh when somebody creates bus contention. No damage! Peter Alfke, Xilinx ======================================= Matt Ettus wrote: > > I need to make a bus between an FPGA (Cyclone) and a microcontroller. > The bus will operate as fast as 48 MHz. It will need to be > bidirectional. > > What I am worried about is accidentally having both sides driving the > bus at the same time (during prototyping). I think I can insure that > my designs don't do that, but this is a development board, and I don't > know what code other people might put on it. Should I make the bus > open drain? Or put resistors in the lines to prevent burnouts? Or > just be very careful... > > Thanks > MattArticle: 55026
>I would be interested to hear what objections you have to Amba or >CoreConnect. What features do you want? > >-- >Best regards, >Mit freundlichen Grüßen, > >Charles Gardiner At first: Sorry for not having posted back in time. I don't have usenet acces in the hardware lab, and therefore can only respond from my private PC. I meant Avalon is not as flexible by means of control over internal bus structure, which is actually this strange AVALON Bus module, greatly created by the SOPC Builder... AMBA and CoreConnect are better - I think - compared to Avalon. But I thought one had to pay for a license in order to use them!? For I don't know, I use WISHBONE which is completely free... hence limited to some kind of simple burst modi I now have to cope with - and to make the best of it. BTW: Doesn't SIEMENS (respectively Infineon) also have an own SOC-bus system? I heard something like that! best regards Chris.Article: 55028
"Rudolf Usselmann" <russelmann@hotmail.com> schrieb im Newsbeitrag news:d44097f5.0304180426.18f7a609@posting.google.com... > "Robert Finch" <robfinch@sympatico.ca> wrote in message news:<jNFna.5378$KH1.690502@news20.bellglobal.com>... > > > SOC-bus protocol that allows for pipelining and is user-configurable, > > > > Just curious, why does it have to be pipelined ? Can't fifo's be used ? > > I think what he really means is that it is fully synchronous. > E.g. he wants that the ACK signal is not asynchronously generated > from the STROBE signal. Just a Wild Guess ! > > BTW: I thought that WISHBOINE fixed that and optionally can > be fully synchronous. I think this is in the latest revision. > > > > manufacturer independent... and free of fees. :-) > > > > > > Rob > > Regards, > rudi > ------------------------------------------------ > www.asics.ws - Solutions for your ASIC needs - > FREE IP Cores --> http://www.asics.ws/ <--- not exactly. I only wanted to mention, that the WISHBONE protocol doesn't allow for separate REQUEST and RESPONSE phases! And that is: If I issue a first REQUEST on the bus, I have to wait for the first response in order to go on with the next address. And that - can - take considerably long. regards Chris.Article: 55029
Hi Christian, > not exactly. I only wanted to mention, that the WISHBONE protocol doesn't > allow for separate REQUEST and RESPONSE phases! And that is: If I issue a > first REQUEST on the bus, I have to wait for the first response in order > to go on with the next address. And that - can - take considerably long. > regards > Chris. So, do you sort of want the Amba split transaction feature or do you want to have a general transaction queue? The split transaction feature allows the bus to be freed while a slave device completes the transaction, but the slave will accept no additional requests. In the meantime other slave devices may be addressed. A transaction queue implies that a master can issue a number of transaction requests to an arbitrary number of slaves without stalling. This is tricky, especially with reads. BenArticle: 55030
Hi Matt, The Cyclone can definitely limit their output current, but this has to be set in the project. Same goes for Virtex, and idem for setting its output termination (and, idem with Stratix's termination, for that matter), so all of these are prone to the dreaded User Error syndrome. What I think you're saying though, is whether there is a foolproof way to make sure that this kind of design fault does not happen. Of course, just being very careful, and boldly marking the section about the bidirectional bus on the front page, the back page and anywhere inbetween in the documentation in red blinking ink is _the_ solution, as it greatly reduces component cost and keeps performance up. Practically though, I doubt that anyone will actually read your carefully crafted documentation until it's too late, so I would indeed put some resistors on this bus if I were you. Cyclone buffers will sink up to 15mA (too lazy to look at their drive spec), so a 220ohm series resistor should protect your circuit from going up in smoke. Depending on the Other Side (what it considers to be logic 1, its own input impedance, the capacitance of the line etc), this should work without too many problems. Best regards, Ben > Matt, I obviously cannot speak for Cyclone, but I would just > artificially reduce the output drive of the FPGA. In Virtex you can go > down to 2 mA guaranteed drive ( of course higher worst case) and even > better, you can implement the on-chip serial termination, which gives > you a 50 Ohm output impedance (guaranteed). I have heard a rumor that > Cyclone has similar capabilities... > Then you can just laugh when somebody creates bus contention. No damage! > > Peter Alfke, Xilinx > ======================================= > Matt Ettus wrote: >> >> I need to make a bus between an FPGA (Cyclone) and a microcontroller. >> The bus will operate as fast as 48 MHz. It will need to be >> bidirectional. >> >> What I am worried about is accidentally having both sides driving the >> bus at the same time (during prototyping). I think I can insure that >> my designs don't do that, but this is a development board, and I don't >> know what code other people might put on it. Should I make the bus >> open drain? Or put resistors in the lines to prevent burnouts? Or >> just be very careful... >> >> Thanks >> MattArticle: 55031
Matt Ettus <matt@ettus.com> wrote: : I need to make a bus between an FPGA (Cyclone) and a microcontroller. : The bus will operate as fast as 48 MHz. It will need to be : bidirectional. : What I am worried about is accidentally having both sides driving the : bus at the same time (during prototyping). I think I can insure that : my designs don't do that, but this is a development board, and I don't : know what code other people might put on it. Should I make the bus : open drain? Or put resistors in the lines to prevent burnouts? Or : just be very careful... Using GTL level for the bus allows for indefinite contention, while speed is very good. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55032
HDLmaker version 6.5.9 is now available. The support for Virtex2 has been significantly enhanced. There is also some Spartan3 support in this release. HDLmaker generates hierarchical Verilog and VHDL as well as scripts and constraint files for all Xilinx FPGAs and Altera Stratix devices. This version adds support for Mentor's Precision synthesis tool. HDLmaker is offered by Polybus Systems free of charge. It is open source, licensed under a BSD style license. Get it from http://www.polybus.com/hdlmaker/users_guide/ Also Polybus is now offering a complete set of customizable In System FPGA test patterns. The test suite tests the internal functionality and interconnect of any Xilinx FPGA. More details about the FPGA test patterns can be found at, http://www.polybus.com/xilinx_test_patterns/Article: 55033
Hi Bob, Due to leakage between adjacent (and in general close) FFT bins, it might be better to remove the DC from the set of samples that you want to analyze, since the low frequency data resulting from the FFT should be less affected by leakage. If you will be using your FFT engine multiple times to analyze a sequence that is longer than yout FFT length, you need to pay attention that you remove the DC from the ENTIRE sequence first, not only the sub-sequences before they are put through the FFT. Ljubisa stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0304230335.44f1f80e@posting.google.com>... > Hi, > > When calculating an FFT, how does the inclusion of the DC value affect > things i.e. I have seen some examples of FFT code where the DC is > removed and some where it left. > > Is the best strategy to remove the DC or leave it. For example in a > COFDM system, will its removal or inclusion have any effect? I am > thinking of its > implementation in an ASIC, where DC removal adds overhead and I'm > wondering if it really necessary to remove it. How will adding > removing the DC level affect the ifft? > > Thank you > BobArticle: 55034
Hello-
I have a large adder (48-bits to 64-bits) that I am implementing in a
Spartan IIE using Verilog synthesis. I assumed that the adder LUTs,
carry logic, and resulting flip-flops would be placed in a column of
CLBs but alas, they are not. Instead, the carry logic is nice, but
the other stuff is sort of scattered about.
So, I tried to pull out the floorplanner and throw things around the
way I think they should be, but the tool won't let me. My questions
are:
- Why doesn't the placer do things correctly? This seems like a
no-brainer placement problem to me. The carry chain alone provides a
pretty hefty constraint.
- Can the adders be forced to be implemented as an RPM without doing
the whole coregen thing or building my own adder and rloc'ing it?
- Is there some limitation that I'm missing that won't allow the LUTs
to be stacked reasonably and in the same slice?
Now, for the purposes of this email, I've simplified somethings, but I
think justifiably so. Namely, the adder is really:
always @(posedge clk) begin
out1 <= val + (sel ? out1 : out0);
end
Where 'sel' is a mux select and val is a register. The mux/adder
should fit nicely in the LUT (and does).
Cheers,
Jake
Article: 55035All this talk about low pin count FPGAs got me thinking about my current problem. I am looking for a small collection of board supervisory and control funtions that I can't seem to find in a single chip. I can't even get them in two or three chips since my combination of inputs for power control and reset are not common. So I thought about using one of the more recent, very small 8 bit micros to become a "super" supervisor and provide signals such as reset and power enable along with a RTC and temperature shutdown. Even considering that this will require using software, I think it will be the simplest, smallest and cheapest solution available. The only problem is, I am having a hard time finding the "right" 8 bit micro. This circuit needs to operate in temps of -40 to 125C. The rest of the board will only be rated for 85C and this circuit will shut off all power to the board to prevent damage from running above 85C. Seems there are some places in the world that get pretty durn hot. The inside of a locomotive sitting in a tunnel is one of them. So can anyone recommend a small, cheap, very low power MCU that will operate over -40 to 125C, has flash (OTP might be ok), RTC (software is ok if power level is very low), and can measure the temperature? I originally was going to use a 1% thermistor on an ADC, but all the ADC inputs are now taken. I guess the (small, cheap, simple) way to do the temperature is to just pick a resistor value that will give me a trip point, but then that requires a comparitor and a vref. I looked at the TMS430 and Cygnal parts and did not find anything that is rated to run over that temp range. The Fairchild ACE MCUs come in an automotive range, but have too few IOs, I need about 10 that I know of. I am not really up to date on automotive temp MCUs and not so current with the 8 bit MCUs either. I guess I will take a look at Motorola and Microchip next. I am getting to hate the web... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55036
Jake,
Been a while since I've heard from you... Anyway, you've discovered one
of the warts on the tools. There are several things that can make it
impossible to pack the carry chain components properly. If you have
access to a mapped HDL viewer, I would reference that to see what the
synthesis did to your adder. Some possibilities:
1) it might have put logic between the carry chain and the register.
Typically this is a mux after the add or a sync reset that didn't get
sucked into the flip-flop (usually because of a global reset already
occupying the pin).
2) a clock enable or reset net is split up so that registers that should
have been packed can't be
3) The carry chain got messed up. This can happen if you are adding a
constant. I've seen synthesis 'optimize' a carry chain where one or more
bits are constants in such a way that the carry chain can no longer be
placed. What typically happens is you get two sub-chains. If the bottom
of the upper chain is on an odd bit, the placer will shift the chain down
by half a slice. Put a syn keep on the constant input signal to avoid
this.
4) The LUT logic can get strewn hither and yonder by optimization that
breaks the LUT down in funny ways.
5) Finally, the placer just doesn't do a very good job with the logic
associated with carry chains for some reason. You can sometimes improve
the results by adjusting the timing constraints, but only if the packer
has already properly paired the pieces.
For stuff that is speed or density critical, I find it is easier just to
do the RLOCing using a generate....oh yeah, you are using Verilog so you
don't have a generate. That makes the RLOCs a lot more awkward.
Jake Janovetz wrote:
> Hello-
>
> I have a large adder (48-bits to 64-bits) that I am implementing in a
> Spartan IIE using Verilog synthesis. I assumed that the adder LUTs,
> carry logic, and resulting flip-flops would be placed in a column of
> CLBs but alas, they are not. Instead, the carry logic is nice, but
> the other stuff is sort of scattered about.
>
> So, I tried to pull out the floorplanner and throw things around the
> way I think they should be, but the tool won't let me. My questions
> are:
> - Why doesn't the placer do things correctly? This seems like a
> no-brainer placement problem to me. The carry chain alone provides a
> pretty hefty constraint.
> - Can the adders be forced to be implemented as an RPM without doing
> the whole coregen thing or building my own adder and rloc'ing it?
> - Is there some limitation that I'm missing that won't allow the LUTs
> to be stacked reasonably and in the same slice?
>
> Now, for the purposes of this email, I've simplified somethings, but I
> think justifiably so. Namely, the adder is really:
> always @(posedge clk) begin
> out1 <= val + (sel ? out1 : out0);
> end
>
> Where 'sel' is a mux select and val is a register. The mux/adder
> should fit nicely in the LUT (and does).
>
> Cheers,
> Jake
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55037"Loi Tran" <leotran@att.net> wrote in message news:NW_oa.72385$ja4.4813800@bgtnsc05-news.ops.worldnet.att.net... > > >Before you give up on installing Xilinx, did you find viewing the > >"agreement" would let you install the software? I can't imagine that > >Xilinx would *block* you from using this under another OS. > > I would if I could, but the policy isn't even displayed. > > >My suggestion: get over being ticked at Xilinx and find a way to upgrade > >your OS to Win2000 or even XP. Or maybe this is the nudge you need to > >switch to Linux! Before I will switch to XP, I will give Linux a > >serious go. Win2000 will be my last Microsoft OS. > > The reason why I'm still using Windows 98 is because I swore I would never buy > anything from M$ or M$ related again. You can stop groaning now (and thinking > I'm a cheapskate). I would pay for anything that's proven itself. The only > thing that Microsoft has proven is that it produces an inferior product and > claim superiority. I stop counting the number of times I've cursed and > sworn at a computer running Microsoft product (at work and at home). But > Webpack is the one thing I'd like to use and it isn't supported under Linux > except with WINE (which I don't want to USE). > > LT > The upgrade to windows xp pro was well worth it for me. (Upgraded from win98 on one and nt4 on another) More stable, still runs programs for windows 98 and 95 but when those programs crash they don't take down the os. Best thing for me is clear type on a lcd screen. I've had less crashes with windows xp than I have with my linux boxes, that is even with installing microsoft service patches when they come out. I was going to use win2000 but the major hassles I had with service pack3 on another computer made me decide not to. If you can wait out to the next version of web pack there supposedly will be a linux version. Other option if you need windows is get a fairly decent box smp if you can afford it and 2GB+ of ram install linux or freebsd then vmware and run windows inside that. AlexArticle: 55038
I've searched the web with no luck for a PCI development board with using an Altera Cyclone part. Probably because it's a new part, but if anyone knows where I can find one, please post a link. It must be Cylone, and it can be a PCI board or PMC module. Thanks in advance.Article: 55039
I just came across Northwest Logic's (http://www.nwlogic.com) PCI/PCI-X core offerings (for Altera and Xilinx) and was wondering if there were any folks out there who have used them (or other cores from Northwest Logic) and would like to share their experiences. Thanks in advance for information, BerendArticle: 55040
I made a little headway at the Motorola site. I think I have a feel for how their part numbers work... at least in part. I am looking hard at the MC68HLC98JL3E. But there is also an MC68HLC98JL3 *without* the E at the end (well, near the end, this is followed by the temperature and package designators). I can't find anywhere what the durn E means and the two data sheets are impossible to compare without eyeballing every word on every page. The only thing I see different in the "specs" section is the addition of "2 ICAP/OCAP/PWM" in the non-E data sheet. But I don't think this is meaningful since both chips have these three features. Is this some electrical difference, enhanced process? The price on these units seems cheap. $1.50 to $3 for the 1.5 KB flash and 4 KB flash parts. Although to get a small package you have to buy the largest part which comes in a 48 pin LQFP, go figure! rickman wrote: > > All this talk about low pin count FPGAs got me thinking about my current > problem. I am looking for a small collection of board supervisory and > control funtions that I can't seem to find in a single chip. I can't > even get them in two or three chips since my combination of inputs for > power control and reset are not common. > > So I thought about using one of the more recent, very small 8 bit micros > to become a "super" supervisor and provide signals such as reset and > power enable along with a RTC and temperature shutdown. Even > considering that this will require using software, I think it will be > the simplest, smallest and cheapest solution available. > > The only problem is, I am having a hard time finding the "right" 8 bit > micro. This circuit needs to operate in temps of -40 to 125C. The rest > of the board will only be rated for 85C and this circuit will shut off > all power to the board to prevent damage from running above 85C. Seems > there are some places in the world that get pretty durn hot. The inside > of a locomotive sitting in a tunnel is one of them. > > So can anyone recommend a small, cheap, very low power MCU that will > operate over -40 to 125C, has flash (OTP might be ok), RTC (software is > ok if power level is very low), and can measure the temperature? I > originally was going to use a 1% thermistor on an ADC, but all the ADC > inputs are now taken. I guess the (small, cheap, simple) way to do the > temperature is to just pick a resistor value that will give me a trip > point, but then that requires a comparitor and a vref. > > I looked at the TMS430 and Cygnal parts and did not find anything that > is rated to run over that temp range. The Fairchild ACE MCUs come in an > automotive range, but have too few IOs, I need about 10 that I know of. > > I am not really up to date on automotive temp MCUs and not so current > with the 8 bit MCUs either. I guess I will take a look at Motorola and > Microchip next. I am getting to hate the web... > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55041
In article <3EA897AF.C4494A00@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >The only problem is, I am having a hard time finding the "right" 8 bit >micro. This circuit needs to operate in temps of -40 to 125C. The rest The Microchip PIC series can do this in the Automotive package. For an 8 pin flash version you want the 12F629 or 12F675 (adds A/D). Has internal reset, power on delay, brownout detection, oscillator, etc. It can get by with almost zero external components in most situations. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 55042
Ben Jackson wrote: > > In article <3EA897AF.C4494A00@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >The only problem is, I am having a hard time finding the "right" 8 bit > >micro. This circuit needs to operate in temps of -40 to 125C. The rest > > The Microchip PIC series can do this in the Automotive package. > For an 8 pin flash version you want the 12F629 or 12F675 (adds A/D). > Has internal reset, power on delay, brownout detection, oscillator, > etc. It can get by with almost zero external components in most > situations. Thanks, I just spent the evening looking at Motorola, Microchip, TI and Cygnal. I don't see where TI or Cygnal make automotive parts at all. Both Motorola and Microchip have parts that meet the temperature specs. It looks pretty clear that Microchip has designed their chips so that you can use a 32.768 kHz xtal on T1 and let it run while the rest of the chip is off. It will output an periodic interrupt to wake up the CPU and allow it to see if it is time to wake up the rest of the board. It should also be able to take a temperature measurement in case that is what has shut the board down and it is cool enough to turn back on. All I have to do is figure out how to get it to take a temperature measurement since that is not built in... Maybe it is time to dig out my thermistor again. I am running out of stamina. I like the PIC, but I want to be thorough and will pick up with the AVR chips tomorrow. It is a shame that they don't include temperature range in the selection guides. BTW, it looks like Atmel has worked on their site a lot and it is much better than it was a year ago. Other than the Asian vendors, did I miss any of the easy to use chips (and easy to browse web sites)? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55043
Hi Rick, Booth Motorola and Microchip have very small and cheep devices in this range(look at the Nitron family from Mot) You get a code size (4k) limitied version of Metrowearks C-compiler for free if you are using this family (at least you did 1/2 year ago when the part was released). For low power and very good A/D converter support I would select the MSP430 family from Texas Instruments, it is a 16-bit micro priced at the same level as the mid to low end 8-bits :) only problem here is that at the moment there is no automotive temp range avalible (+125C). Not a realy small part is the COP8AM from National Semi, it comes in a SO-28 package, meats your temp spec has built in Tempsensor and AD-converter prices is not that bad for 8-k of flash (+3$ in 1k volume according to NS homepage), there is also a ref design availble to this part that is very good (Will not tell who took part in the development :) Cheers Fredrik rickman <spamgoeshere4@yahoo.com> wrote in message news:<3EA897AF.C4494A00@yahoo.com>... > All this talk about low pin count FPGAs got me thinking about my current > problem. I am looking for a small collection of board supervisory and > control funtions that I can't seem to find in a single chip. I can't > even get them in two or three chips since my combination of inputs for > power control and reset are not common. > > So I thought about using one of the more recent, very small 8 bit micros > to become a "super" supervisor and provide signals such as reset and > power enable along with a RTC and temperature shutdown. Even > considering that this will require using software, I think it will be > the simplest, smallest and cheapest solution available. > > The only problem is, I am having a hard time finding the "right" 8 bit > micro. This circuit needs to operate in temps of -40 to 125C. The rest > of the board will only be rated for 85C and this circuit will shut off > all power to the board to prevent damage from running above 85C. Seems > there are some places in the world that get pretty durn hot. The inside > of a locomotive sitting in a tunnel is one of them. > > So can anyone recommend a small, cheap, very low power MCU that will > operate over -40 to 125C, has flash (OTP might be ok), RTC (software is > ok if power level is very low), and can measure the temperature? I > originally was going to use a 1% thermistor on an ADC, but all the ADC > inputs are now taken. I guess the (small, cheap, simple) way to do the > temperature is to just pick a resistor value that will give me a trip > point, but then that requires a comparitor and a vref. > > I looked at the TMS430 and Cygnal parts and did not find anything that > is rated to run over that temp range. The Fairchild ACE MCUs come in an > automotive range, but have too few IOs, I need about 10 that I know of. > > I am not really up to date on automotive temp MCUs and not so current > with the 8 bit MCUs either. I guess I will take a look at Motorola and > Microchip next. I am getting to hate the web... > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55044
> > On the other hand, have you looked at the Cyclone parts? They run on > 1.5 volts and are available *now*. Or the Spartan IIE runs on 1.8 > volts, not a lot worse efficiency in the LDO. I am actually thinking about VirtexII - XC2V250 which is 1.5V powered. I know it is expensive, but I would like to use all Block RAMs available to create FIFOs. I do not need too much logic and really high speed, so even a small SpartanII(E) would do, but I'm short of two things: board space and available power, and I expect that this solution will be more efficient in both aspects. > > Which DSP are you using? > I already mentioned: TMS320VC5502. I think it is time to finish this topic, since at the moment it has nothing to do with original subject;) -- Robert PudlikArticle: 55045
Stephen Williams <icarus-hates-spam@icarus.com> writes: > This question has been asked a lot. Someone should put together a ready- > to-run WINE configuration (including config files and pre-installed disk > image) that works. > > At least for WebPACK. Yes, that would be nice. Does Xilinx allow redistribution of the WebPACK files?Article: 55046
Hi, I am also interested in Viterbi decoder..I have some things to clear.. 1) How do you synchronise the bits as the data transmitted is in serial mode..ie. when decoding... 2) I would like to add Low power design features, can u tell me if u have any idea to implement.. Thanks. regards, Sharan Jussi Lähteenmäki <jusa@students.cc.tut.fi> wrote in message news:<b87v2b$m29$1@news.cc.tut.fi>... > In comp.lang.vhdl vikas <vikas_akalwadi@indiatimes.com> wrote: > I have been working quite a lot with viterbi, but feel somewhat inadequate > to answer to your questions. I have always felt that the only things truly > affecting the overall area consumption are the number of softbits and and > the chosen traceback depth. Things beyond those are merely bits and > pieces. Anyhow, my intention was to tell you that I have access to those > ieee papers, so if you drop me a mail I can send them to you in return. I > don't really know how legal it is to do so, but it can never be too > illegal to share knowledge (yes I am a researcher :) )... > > regards, > juza > > > : 3. After survival data equal to trace back deapth has been stored, we > : start trace back. If we are to start the traceback with lowest partial > : path metric, how do we determine that state if we do "localised > : normalisation" > > : 4. What are the different techniques for trace back operation ? > : Since i am implementing it on hardware, functionality, area and timing > : all are very important. > > : expecting reply, > : regards, > : VikasArticle: 55047
KB <khimbittle@cliftonremovesystems.com> wrote: : On Mon, 14 Apr 2003 16:59:06 -0400, Theron Hicks : <hicksthe@egr.msu.edu> wrote: :>Has anyone noticed that this part is available with LEGS? It appears :>that someone at Xilinx was listening to the request for non-BGA parts. :> : Actually I was a little disappointed in this area. Only the XC3S50 / : 200 / 400 is available in the 208 pin pqfp .. the 2e took this package : up the 300 part so some improvement yes .. but the Cyclone EP1C12 is : available in a 240 pin pqfp ... 30+ more I/O pins, and the cyclone has : 12K registers , a bunch more than the new 400 part. my 2'c KB But I don't see on-chip termination for the Cyclone part. Or did I miss something? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55048
Hi Mike, One product Altera offers is the PCI32 Nios Add-on Dev Kit. This is a board that you hook-up to any Nios dev kit (including the Cyclone version), and you can plug it into a PCI32 slot. It provides a PCI interface to your Nios dev board, an API, etc. I don't know anything about it besides what's on our web site. You can read about it here: http://www.altera.com/products/devkits/altera/kit-dev_nios_pci32.html - Paul "mike" <mxv@yahoo.com> wrote in message news:8ea508fe.0304242036.224f0c6e@posting.google.com... > I've searched the web with no luck for a PCI development board with > using an Altera Cyclone part. Probably because it's a new part, but if > anyone knows where I can find one, please post a link. It must be > Cylone, and it can be a PCI board or PMC module. > > Thanks in advance.Article: 55049
RISC_taker@alpenjodel.de (RISC taker) wrote: >Hey, I need to calculate (n mod 3) in a Virtex-II design. n is a >10-bit unsigned number and 3 is a constant. This has to be done in the >same cycle (combinatorial!). Now what's a good way to implement that? > >I thought of a lookup table (distributed RAM) but this takes quite a >lot of space. Any better ideas? (Ray, the arithmetic guru? :-) A good way of implementing it? Write a 1024 case switch assigning the required output. If the solution is a simple combinatorial expression the tool will create it - no arithmetic guru required.
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