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Spartan-3 supports partial configuration, but it is slightly different from Virtex-II. If you have detailed questions about the capability and/or restrictions, we will gladly help you. Just e-mail me. Peter Alfke ================== Silvano Bettinzana wrote: > > Hi there, > > is possible to partial reconfigure SpartanIII devices (something similar to > partial reconfiguration of VirtexII) ? > > Thanks > > SilvanoArticle: 54776
Austin Lesea <Austin.Lesea@xilinx.com> writes: > Smaller parts are smaller for the minimum required current. > > The difference between two already tiny parts is too tiny to spec. Sure, but I'd expect there to be a non-trivial difference in the minimum required current for the XC2S15 vs. the XC2S200. Yet the data sheet still gives the single 500 mA figure for all the parts.Article: 54777
The primary advantages of the Spartan-IIE family in the 256-ball BGA package is that you can choose between six devices already in volume production that are readily available in a footprint-compatible package. Spartan-IIE also offers lower price points for 182 I/O pins. Plus, Spartan-IIE devices offer distributed RAM and shift-register capabilities within each logic cell, which can dramatically increase logic effectiveness by a factor of 16X! Likewise, Spartan-IIE has internal bi-directional bussing capability without consuming any logic cells. Furthermore, Spartan-IIE supports PCI up to 64 bits wide at 66 MHz. The five pin-compatible Spartan-IIE devices in full production include the following. * XC2S50E (1,536 LUT+FF pairs) * XC2S100E (2,400 LUT+FF pairs) * XC2S150E (3,456 LUT+FF pairs) * XC2S200E (4,704 LUT+FF pairs) * XC2S300E (6,144 LUT+FF pairs) * XC2S400E (9,600 LUT+FF pairs) The six Spartan-IIE devices in the 256-ball BGA package range in price from US$16.61 to $91.52 in 24-99 quantity, depending on speed grade (SOURCE: www.avnetmarshall.com). Pricing in the U.S. is also available via www.insight.com and http://www.nuhorizons.com. Nearly all device/package combinations are in stock at the distributor. The wider range of densities provides finer granularity on logic vs. I/O. If your design is primarily I/O, then prices start as little as $16.61. Compare this to only two Cyclone devices in this package, ranging in price from US$33.20 to $174 in 24-99 quantity, depending on speed grade (SOURCE: www.arrow.com). All devices show 6 weeks lead-time. Spartan-IIE is manufactured on 0.15u (150 nm) technology using 300 mm wafers. Certainly, 0.15u is larger than Cyclone's 0.13u technology, so Cyclone has roughly a 25% die size advantage at comparable logic densities. However, Cyclone is manufactured on 200 mm wafers. The 300 mm wafer manufacturing advantage provides Spartan-3 with about a 30% cost saving. If designing for applications going to production early next year and if you are considering changing FPGA families, you should also consider the recently announced Spartan-3 family. Spartan-3 is manufactured on advanced 90 nm (0.09u) technology, offering about a 50% area advantage over 0.13u. Software support is already available in ISE 5.2i, but I recommend downloading the latest service pack for recent feature upgrades. http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp There are three footprint-compatible Spartan-3 devices planned in the 256-ball BGA package, as shown below. The XC3S1000 recently started sampling. There are 173 I/O in the 256-ball BGA package for Spartan-3. Spartan-3 advantages over Cyclone include larger block RAM size (18Kb vs. 4Kb), embedded 18x18 multipliers, four digital clock managers (clock frequency synthesis, de-skewing, clock correction, etc.), more supported I/O standards, distributed RAM/shift-register capability, dedicated DDR registers, wide multiplexers, more devices, more I/O, and higher device densities. * XC3S200 (3,840 LUT+FF pairs, planned) * XC3S400 (7,168 LUT+FF pairs, planned) * XC3S1000 (15,360 LUT+FF pairs, sampling) --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3 E-mail: steve.knapp@xilinx.com --------------------------------- CB wrote: > > comparing the spartan2e and cyclone component lines in the 256 pin bga > packages , can anyone please tell me advantages in going with the > cyclone versus staying with the spartan2e , i don't care minor > differences in the ram and i/o but i am interested in significant > advanges the cylcone may have, thank you in advance --Article: 54779
> SOC-bus protocol that allows for pipelining and is user-configurable, Just curious, why does it have to be pipelined ? Can't fifo's be used ? > manufacturer independent... and free of fees. :-) RobArticle: 54780
Michael Garvie wrote: > Single Event Latch-Up seems to be extremely uncommon and when it > does happen reconfiguration restores correct functionality. For latchup, power cycling is generally necessary to clear the condition; latchup is self-sustaining from VDD --> GND. -- rk, Citizen, Noooo Yawk "Sometimes when you connect the dots you get a picture. Other times you just have a bunch of dots." -- rk, January 23, 2003Article: 54781
At the low end of the density range, packaging and test costs dominate the end-user price. The big differences on Spartan-3 happen on the higher densities and the price differentials become huge. Regarding your question on pricing for the Spartan-3 XC3S200, I would recommend contacting your local Xilinx sales representative. Judging from your E-mail address, you appear to be from Brazil. Likewise, there are a number of price competitive solutions in Spartan-IIE as well. BRAZIL BP&M Representacoes e Consultoria S/C Ltda Rua Americo Brasiliense, 2171 sala 404 04715-005 Sao Paulo - SP - Brazil 55-11-5181-4788 55-11-5181-4790 fax --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3 E-mail: steve.knapp@xilinx.com ------------------------------ Luiz Carlos wrote: > > How much does cost the XC3S-200? > U$3.50 for XC3S-50 is not that much competitive. It's half the logic > cells (LUT+FF) of the EP1C3, does not have block RAM nor DCM (PLL > like) and itīs just 50 cents cheaper!!! > Will Xilinx let Altera reign free in this logic range? > > Luiz Carlos Oenning Martins > KHOMP Solutions -- ---Article: 54782
Steve Knapp wrote > Nearly all sevice/package combinations are in stock at the distributor. If only this were so. I types XC2S50E into NuHorizon's search engine and only 3 out of 29 combinations were in stock. This is not a one-off situation. There is clearly a major problem in getting off-the-shelf delivery of Spartan-2 and Spartan-2E parts from distribution.Article: 54783
Sorry, I was referring to the Avnet site. I'll make sure that our distribution manager sees this. -- --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3 E-mail: steve.knapp@xilinx.com --------------------------------- Tim wrote: > > Steve Knapp wrote > > Nearly all sevice/package combinations are in stock at the distributor. > > If only this were so. I types XC2S50E into NuHorizon's search > engine and only 3 out of 29 combinations were in stock. > > This is not a one-off situation. There is clearly a major problem > in getting off-the-shelf delivery of Spartan-2 and Spartan-2E parts > from distribution.Article: 54784
Semantics: "Single-event upsets" are normally defined as soft errors, latches loosing their data content. "Latch-up" is normally defined as the n-channel/p-channel combination turning on as an SCR. Latch-up is extremely rare in well-designed CMOS, and can be made even rarer by processing methods like epi-layer. Ouside of extreme radiation, latch-up is really a non-issue. ( and yes, it would require powering down). SEUs cannot be avoided,but they can always be repaired in an FPGA, even without powering down. Peter Alfke ========================== rk wrote: > > Michael Garvie wrote: > > > Single Event Latch-Up seems to be extremely uncommon and when it > > does happen reconfiguration restores correct functionality. > > For latchup, power cycling is generally necessary to clear the > condition; latchup is self-sustaining from VDD --> GND. > > -- > rk, Citizen, Noooo Yawk > "Sometimes when you connect the dots you get a picture. Other times you > just have a bunch of dots." > -- rk, January 23, 2003Article: 54785
Paul Baxter wrote: > > "Bill Hanna" <billh40@aol.com> wrote in message > news:97d137ce.0304171001.5ec5461d@posting.google.com... > > I have designed Altera chips for over 6 years and never had a > > problem. > > I was listening until you said that. > > Sorry but Altera and Xilinx both have a fair share of problems. If you are > going to berate Xilinx at least don't ruin the case by unfounded Altera > comments. > > My 0.02cents I know that a common opinion is that that the Xilinx tools can give you a better result, but the Altera tools are much easier to use. But it turns out the one time I was using the Altera tools professionally they not only gave problems, they literally turned a hard project into a nearly impossible one. I was just talking today with one of my former coworkers about this (former because of this very project to some extent). I think we have both sworn off MaxPlusII. Fortunately Altera supports most of their products with Quartus. In fact, I am convinced that is why they were not interested in fixing the problem. This was on an older part that will never be supported with Quartus and they did not care enough to fix the problem with MaxPlusII either. Not many design wins with a three or four year old part. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54786
One approach to consider. The idea is to avoid the external clock buffer by generating several copies of the clock in the Xilinx. Make a 240 MHz clock. Use that to make a 120 MHz sq wave, and feed that to several nearby IOBs. Nearby is to reduce skew, so you want them all on the same clock line. I think that constrains you to left or right side rather than top or bottom. You would need to check the final routing carefully. You might be able to do something similar by connecting several OBUFs (rather than one) to the output of the DCM. You just need a way to make sure the skew between them is low. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 54787
Ben Twijnstra wrote: > > Hi Rick, > > > Was the EP1C4 > > added as an afterthought after the other devices had been planned? It > > seems like 5 months is a long time after all the other family members > > are out. > > Since the Cyclone family spec was based on a lot of customer feedback, I > guess that it took five months of customers complaining about too little I/O > per LE in the Cyclone family to get this one started ;-) > > By the way, if you install Quartus II 2.2 service pack 2 you can already > start designing for it. Actually I received an email from someone who I think is an Altera FAE who said pretty much that. The 1C4 was concieved after feedback on the planned 1C line said, "give us more IO on the low end". That was always my complaint with the XC2V line, but I guess Xilinx was listening to the users wanting the larger chips. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54788
Paul Leventis wrote: > > > After reading Fredrik's post, I found the release dates by searching the > > press releases which contained a link. > > If you go to the 'Overview' page on the Cyclone web site, it also lists the > Production availability dates -- Sept 2003 is for production devices. > > http://www.altera.com/products/devices/cyclone/overview/cyc-overview.html > > > I am curious. Since all the other devices are shipping now, why is the > > EP1C4 shipping so much later? I saw on the EBV web site that they still > > don't even list the EP1C4 in the Cyclone Family Overview. Was the EP1C4 > > added as an afterthought after the other devices had been planned? It > > seems like 5 months is a long time after all the other family members > > are out. > > Really the anomally is rolling out (to full production status, no less) four > devices in three months -- when you look at the roll-out of other FPGA > families, 9 months from first to last member is not abnormal. > > The technical reason: In order to achieve the higher IO density on the 1C4, > we use a staggered (vs. linear) pad ring, which required a small amount of > additional design, verification and software modeling effort. All the other > Cyclone members use a linear pad ring and share the same IO building > blocks -- that's why we could stamp them out so quickly. Thanks for the feedback. I don't see many Altera people posting here. I guess I missed the Overview page because when I clicked on Cyclone on the Devices page, I thought I *was* looking at the Overview page. Turns out I was looking at the Marketing page. Anyway, I got what I needed for now. Thanks. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54789
Sorry, but I feel the need to clean up a few common misconceptions.
Only Spartan-II FPGA (non-E) family, announced January 2000, is 0.18u.
Spartan-IIE is 0.15u and has been in volume production for over 18
months now. Still, Cyclone at 0.13u potentially has a 25% area
advantage (potentially a ~25% cost advantage) at comparable densities
(1-((0.13^2)/(0.15^2)))=25%. However, Spartan-IIE is manufactured on
300 mm wafers, which delivers about a 30% cost reduction over 200 mm
production. Cyclone, I understand, is not yet on 300 mm wafers but will
be about the same time that the 90 nm Spartan-3 devices start
production. In production, Spartan-3 will be at 90 nm on 300 mm,
offering a double cost benefit.
Another posting under this same thread shows that cost is more than just
LEs. Spartan-IIE solutions at 180+ pins start at just US$16.61 while
Cyclone starts at $33.20. Some applications need more LEs at this I/O
range, some don't.
Also, the claim about Cyclone being cheaper per LE is a bit spurious.
The claim is only true assuming that you never use any of the following
logic structures.
-- Multiplexers larger than 2:1
-- Internal bussing structures
-- Small FIFOs
-- Delay buffers or serial-in/serial-out shift registers
-- Multipliers
Take a simple 4:1 multiplexer. How many LEs are required to implement
this feature in both architectures? Let's define an LE as a LUT+FF pair
inside the Altera LAB or Xilinx CLB.
Spartan-IIE: 2 LEs, one level of logic
Cyclone: 3 LEs, two levels of logic
In this simple example, Cyclone uses 50% more LEs and an additional
layer of logic.
Now expand it to an 8:1 multiplexer.
Spartan-IIE: 4 LEs, one level of logic
Cyclone: 8 LEs, three levels of logic
Again, Cyclone uses 50% more LEs and an additional layers of logic..
Now, let's look at an example where we have eight byte-wide functions
connected to a common bus. How much logic is required to create the
bi-directional bus?
Spartan-IIE: 0 LEs (the architecture has internal three-state
functionality)
Cyclone: Requires eight 8:1 multiplexers at 6 per instance, or 48
LEs.
Now, let's look at a serial-in/serial-out shift register.
Four-deep shift register:
Spartan-IIE: 1 LE (the architecture has distributed RAM/serial shift
functionality)
Cyclone: 4 LEs (okay, in reality, it's only the flip-flops that are
used)
Sixteen-deep shift register:
Spartan-IIE: 1 LE (the architecture has distributed RAM/serial shift
functionality)
Cyclone: 16 LEs (okay, in reality, it's only the flip-flops that are
used)
In this example, 1 Spartan-IIE LE equals 16 Cyclone LEs or in some
cases, one Cyclone block RAM.
In real applications, Spartan-IIE uses roughly 15% fewer LUT+FF pairs
than Cyclone. Use Spartan-IIE for any small buffering or DSP
applications and Spartan-IIE offers even greater advantages.
Many of the Cyclone architectural limitations vs. Spartan-IIE are
outlined in one of Altera's own application notes.
AN 255: Guidelines to Migrating Spartan Designs to Cyclone Designs
http://www.altera.com/literature/an/an255.pdf
The question is now "How many LEs do I get per dollar?" The question is
"How much logic can I implement per dollar?"
These opinion are obviously my own and may not reflect those of my
employer.
--
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3
E-mail: steve.knapp@xilinx.com
---------------------------------
Paul Leventis wrote:
>
> Hi CB,
>
> The biggest advantages are cost, logic density, and performance.
>
> Cyclone is a 0.13u device, architected for low-cost. Spartan-IIE is 0.18u
> device that recycles the Virtex-E architecture. Cyclone is cheaper for
> almost all applications -- both companies claim the lowest cost part, but
> Cyclone is much cheaper per LE. Cyclone goes up to 20K LEs, while
> Spartan-IIE goes up to 13.8K (or 12K vs 9.6K in a 256-pin package). Cyclone
> is also MUCH faster, partially due to the process advantage and partially
> due to a superior architecture. This speed can turn into a cost reduction,
> since you don't need to buy as fast a speed grade, or you may not need to
> parallelize your data as much (and hence can fit in a smaller part).
>
> That's about it without getting into the details of the features.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
> [This is my spammable email address; I have no affiliation with the
> University of Toronto besides being a student there]
>
> "CB" <cb@hotmail.com> wrote in message
> news:3e9e18e4.32935894@news.compuserve.com...
> > comparing the spartan2e and cyclone component lines in the 256 pin bga
> > packages , can anyone please tell me advantages in going with the
> > cyclone versus staying with the spartan2e , i don't care minor
> > differences in the ram and i/o but i am interested in significant
> > advanges the cylcone may have, thank you in advance
Article: 54790Yeah, and in the CMOS technologies it's the parasitic transisotrs that turn-on, p-n-p-n and as long as the sustaining current and voltage are there it'll stay latched, unless something fries first, perhaps after some thermal runaway. Anyways, perhaps Michael meant SEU and not SEL? And agreed, for well-designed parts and systems, latchup (w/out radiation) is quite rare, can't even think of the last time I saw that. Latchup w/ radiation is not too uncommon in test beams for many production parts not designed for that environment. Epi-layers of the appropriate thickness, assuming that other good design rules are followed, can eliminate that problem. Note that some devices with epi layers that are too thick will still be subject to SEL or devices with appropriate epi layer thickness but other poor design rules can also latch. In some older technologies like CD4000B (z suffix? long time ago) they would hit the devices with neutrons to aid in the prevention of latchup; kill the bipolars and leave the CMOS transistors standing. CMOS is usually good to around 10^14 n/cm^2 or so, 1 MeV equivalent energy. Cheers, -- rk Peter Alfke wrote: > Semantics: > "Single-event upsets" are normally defined as soft errors, latches > loosing their data content. > "Latch-up" is normally defined as the n-channel/p-channel > combination turning on as an SCR. Latch-up is extremely rare in > well-designed CMOS, and can be made even rarer by processing > methods like epi-layer. Ouside of extreme radiation, latch-up is > really a non-issue. ( and yes, it would require powering down). > SEUs cannot be avoided,but they can always be repaired in an FPGA, > even without powering down. > > Peter Alfke > ========================== > > rk wrote: >> >> Michael Garvie wrote: >> >> > Single Event Latch-Up seems to be extremely uncommon and when it >> > does happen reconfiguration restores correct functionality. >> >> For latchup, power cycling is generally necessary to clear the >> condition; latchup is self-sustaining from VDD --> GND. -- rk, Citizen, Noooo Yawk "Sometimes when you connect the dots you get a picture. Other times you just have a bunch of dots." -- rk, January 23, 2003Article: 54791
Hi, Some band-pass IIR filters require large precision. The Fixed-point analysis depends heavely on the IIR characteristics. Altera has developed several tools to help you to design fixed-point IIR filters. You can probably start by downloading the Altera IIR-Compiler http://www.altera.com/products/ip/dsp/filtering/m-alt-iircompiler.html This is an IP. With the evaluation version, you start from the floating-point IIR coefficients and use the built-in floating to fixed-point conversion analysis tools. This help you to determine which bit can be truncated in both feedback and feedforward data-path. The IIR-compiler is interactif and displays dynamically the filter response in the zero-pole or frequency or time domain, based on parameters such as bit-width selection/truncation (among others) In addition, in this tool you can evaluate various IIR structures, such as direct form II, biquad cascaded or biquad parallel. You probably will find out that the fixed-point maths vary from one structure to another. You can also trade-off FPGA multiplier/adder style (parallel distributed arithmetic, MAC based). If you are familiar with Matlab Simulink, another option consists of using the DSP Builder, which is a Simulink plug-in and can be downloaded from : http://www.altera.com/products/software/system/products/dsp/dsp-builder.html From the Simulink cockpit , you can use the IIR compiler, or build the IIR structure with the DSP Builder primitives (Multiply, Add, LUT ...) optimized for Cyclone or Stratix. The DSP Builder-Simulink flow gives you enhanced sink and source block for system analysis, and this could be very usefull in this case when you need to analyze complex aspects of fixed-point IIR design such as stability. Building the filter with DSP Builder primitive may take longer than using the IIR-Compiler, however it may allow you to explore FPGA architectures implementation which are not yet present in the IIR-Compiler such as multi-bit serial. I hope that this will help you to build efficient IIR filters for Cyclone device. Philippe Molson Altera Corporation "gallenm" <gallenm@ic24.net> wrote in message news:<v9tmpdn101mb60@corp.supernews.com>... > Hi, > Just adding a plug for ONEoverT digital filter designer. It will > automatically produce > synthesizable VHDL for IIRs and FIRs. Very cheap, the demo can be downloaded > from > the website > www.tyder.com > > If you download the case study, it will show you the implemention of an IIR > onto a Spartan > FPGA. > > Yours > Alan Mc Kitterick > www.tyder.com > > "Pramod" <pramod@procsys.com> wrote in message > news:a7c0720d.0304152101.581c85be@posting.google.com... > > Hi All, > > I am new to this group and also to the field of FPGA based design. > > I have some doubts and issues which I feel will be easy for you guys > > to answer. > > 1. For a 4 pole IIR Filter in FPGA (targeted device EP1C6), I have a > > spec of 24 bit wide data input and > > 32 bit wide coeff (dynamic) inputs. So, the multiplied results should > > ideally have > > 56 bits width. Are these widths practically relevant for a 4 pole > > filter > > or can we get an affordable precision with rounding to lower sizes? > > If so, can anyone suggest a standard procedure for > > rounding the results with lowest error and without causing the output > > to become unstable? > > 2. Another thing I would like to get some advice is, if I go with the > > 24 X 36 busses, > > since I have to implement a number of such filters in a single device, > > the bit-parallel implementation will take up huge resources. > > The digit serial approach using (either small multiplier or LUT > > method) > > also will end up in huge resources due to big number of partial > > products and sums involved. > > If anyone can suggest any alternate method it will be of great help to > > me. > > 3. On another front, in a timing simulation scenario I am using > > Quartus II .vo output and ModelSIM PE. My code has > > a ROM (ALTSYNCRAM megafunction used to generate this). I found some > > differences in the > > readout data during timing simulation between using .MIF format file > > and .HEX format file for initializing ROM > > eventhough the QII displayed same contents in the memory editor. > > Has anyone ever faced any such issues? > > Hoping to get some valuable leads on these.. > > Thanks in advance, > > PramodArticle: 54792
Steve Knapp wrote:
>
> The primary advantages of the Spartan-IIE family in the 256-ball BGA
> package is that you can choose between six devices already in volume
> production that are readily available in a footprint-compatible
> package. Spartan-IIE also offers lower price points for 182 I/O pins.
> Plus, Spartan-IIE devices offer distributed RAM and shift-register
> capabilities within each logic cell, which can dramatically increase
> logic effectiveness by a factor of 16X! Likewise, Spartan-IIE has
> internal bi-directional bussing capability without consuming any logic
> cells. Furthermore, Spartan-IIE supports PCI up to 64 bits wide at 66
> MHz.
>
> The five pin-compatible Spartan-IIE devices in full production include
> the following.
I think your comparison is a bit uneven. Yes, the Xilinx parts seem to
split the range up into finer pieces. But the prices are not
necessarily better. In the largest size the Altera part is more
expensive, but it also has about 50% more LEs than the XC2S600E.
So the Xilinx parts have one size, the XC2S150E, that gives a
significant price advantage over the Cyclone parts. But then this is
based on "list" prices and means nothing once you start wheeling and
dealing with your disti.
Xilinx LUT+FF pairs Altera LEs
* XC2S50E 1,536 $ 16.61
* XC2S100E 2,400 $ 24.47 EP1C3 2,910 $16.60 (T144)
* XC2S150E 3,456 $ 26.84 EP1C4 4,000 $???
* XC2S200E 4,704 $ 31.29
* XC2S300E 6,144 $ 48.01 EP1C6 5,980 $33.20
* XC2S400E 9,600 $ 91.52 EP1C12 12,060 $87.00
* XC2S600E 13,824 $152.90 EP1C20 20,060 $222.00
(FG456) (FT400)
For a minute I thought you had made a mistake on the logic cell count
until I remembered that the Xilinx data sheet got "creative" on what
they call a logic cell. Someone in marketing should be shot for that
one. Gate counts are pure myth. But I always thought I knew what a
logic cell was.
> The six Spartan-IIE devices in the 256-ball BGA package range in price
> from US$16.61 to $91.52 in 24-99 quantity, depending on speed grade
> (SOURCE: www.avnetmarshall.com). Pricing in the U.S. is also available
> via www.insight.com and http://www.nuhorizons.com. Nearly all
> device/package combinations are in stock at the distributor. The wider
> range of densities provides finer granularity on logic vs. I/O. If your
> design is primarily I/O, then prices start as little as $16.61.
>
> Compare this to only two Cyclone devices in this package, ranging in
> price from US$33.20 to $174 in 24-99 quantity, depending on speed grade
> (SOURCE: www.arrow.com). All devices show 6 weeks lead-time.
Maybe only two in *that* package. But Altera's approach is to use
packages with a compatible footprint. So you can buy the 1C6 and the
1C12 in the F256 package and move up to the 1C20 in the F324 or F400
package in a compatible footprint. Design this in up front and you
won't have to redo your PCB. Or you can move *down* to the 1C4 in the
F324 or F400 package and get up to 301 IOs!
> Spartan-IIE is manufactured on 0.15u (150 nm) technology using 300 mm
> wafers. Certainly, 0.15u is larger than Cyclone's 0.13u technology, so
> Cyclone has roughly a 25% die size advantage at comparable logic
> densities. However, Cyclone is manufactured on 200 mm wafers. The 300
> mm wafer manufacturing advantage provides Spartan-3 with about a 30%
> cost saving.
But that only matters if it shows up in the prices above, and it
doesn't.
> If designing for applications going to production early next year and if
> you are considering changing FPGA families, you should also consider the
> recently announced Spartan-3 family. Spartan-3 is manufactured on
> advanced 90 nm (0.09u) technology, offering about a 50% area advantage
> over 0.13u. Software support is already available in ISE 5.2i, but I
> recommend downloading the latest service pack for recent feature
> upgrades.
>
> http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
>
> There are three footprint-compatible Spartan-3 devices planned in the
> 256-ball BGA package, as shown below. The XC3S1000 recently started
> sampling. There are 173 I/O in the 256-ball BGA package for Spartan-3.
> Spartan-3 advantages over Cyclone include larger block RAM size (18Kb
> vs. 4Kb), embedded 18x18 multipliers, four digital clock managers (clock
> frequency synthesis, de-skewing, clock correction, etc.), more supported
> I/O standards, distributed RAM/shift-register capability, dedicated DDR
> registers, wide multiplexers, more devices, more I/O, and higher device
> densities.
>
> * XC3S200 (3,840 LUT+FF pairs, planned)
> * XC3S400 (7,168 LUT+FF pairs, planned)
> * XC3S1000 (15,360 LUT+FF pairs, sampling)
>
> ---------------------------------
> Steven K. Knapp
> Applications Manager, Xilinx Inc.
> Spartan-3/II/IIE FPGAs
> http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3
> E-mail: steve.knapp@xilinx.com
> ---------------------------------
>
> CB wrote:
> >
> > comparing the spartan2e and cyclone component lines in the 256 pin bga
> > packages , can anyone please tell me advantages in going with the
> > cyclone versus staying with the spartan2e , i don't care minor
> > differences in the ram and i/o but i am interested in significant
> > advanges the cylcone may have, thank you in advance
CB, I hope the price/size comparison above helps. The Altera parts seem
to be a better buy for the size. Unless you need the lowest priced
part, you seem to get more bang for the buck. If you go with a smaller
package, you still get a better deal with the Altera. Also, you have a
higher range chip to choose with Altera, 1C20.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 54793Does all FPGA lost its configuration once you turn off the power? If that is the case, how can you make a consumer product using an FPGA? Does the device comes with its own download mechanism that will automatically download and configure itself when the device is turned on?Article: 54794
For those who havn't noticed.. theres a Cyclone errata relating to the power on surge.. seems it might have been a bad die .. or smeone was asleep that week >:-) 500mA is the correct value not 1.2 Amps SimonArticle: 54795
Hello, In the ISE tool with version 5.1i, is there any incremental tming reporting? I mean, once RUN the Implement Design, it performs the TRANSLATE, MAP & PAR operations. Now after PAR, suppose I am getting few violated paths, for which I m defining them as either false or multi-cycle paths in the UCF file & I want the corresponding timing report. After this, do I have to do the PAR again? Or do I have to do MAP again? Or do I have to start from TRANLATE? Or without doing any of these, can I simply get the timing report corresponding to the changed UCF (constraint file)? REgards, VLSI CHAMP....Article: 54796
On Thu, 17 Apr 2003 10:15:34 +0800, "Victor Chen" <victor.hjchen@msa.hinet.net> wrote:
>Hi fellows:
>
>I want to use the user-defined registers of JTAG on Xilinx FPGA.
>I view the data sheet of Xilinx Virtex serials that it support two
>registers of JTAG are USER1 and USER2. I do not know how I can use
>and configure them on real chip.
>
>Thanks
>
>Victor
You need to create your own data register, and connect it to
the JTAG primitive.
For your entertainment, here is an example of doing it for
Virtex-II.
================================================
`timescale 1ps/1ps
//
// JTAG_DDT Copyright 2001, 2002 (C) Fliptronics
//
//
// data_reg The data to the design, from jtag_ddt host
// cap The data to jtag_ddt host from design
// jtag_clk The jtag clock, buffered with a bufg
// update The jtag update signal. Rising edge updates the data_reg
//
// NOTE: The output signal jtag_clk wiggles only when the data register (DR) is
// being shifted. The rest of the time it is HIGH. It has REG_SIZE+1 falling
// edges, and the same number of rising edges. The update signal pulses high
// after JTAG_CLK has stopped wiggling and is high. I.E. can't use JTAG_CLK
// to sample UPDATE, and JTAG_CLK is probably not much use for anything else,
// in the level above, but we output it just in case someone wants it.
//
//
//
module jtag_ddt (data_reg,cap,jtag_clk,update) /* synthesis syn_noprune=1 */;
parameter REG_SIZE = 32;
input [REG_SIZE - 1:0] cap;
output [REG_SIZE - 1:0] data_reg;
output jtag_clk;
output update;
wire drck1_prebuff;
wire jtag_clk;
jtag_dr #(REG_SIZE) jtag_reg_0 (.tdo(tdo),
.data_reg(data_reg),
.cap(cap),
.shift(shift),
.tdi(tdi),
.sel(sel1),
.jtag_reset(jtag_reset),
.drck(drck1),
.update(update))/* synthesis syn_noprune=1 */;
BSCAN_VIRTEX2 bscan_interface (.TDO1(tdo),
.TDO2(1'b0),
.CAPTURE(),
.DRCK1(drck1_prebuff),
.DRCK2(),
.RESET(jtag_reset),
.SEL1(sel1),
.SEL2(),
.SHIFT(shift),
.TDI(tdi),
.UPDATE(update))/* synthesis syn_noprune=1 */;
BUFG bufgmux_jtag_ddt (.I(drck1_prebuff), .O(drck1));
assign jtag_clk = drck1;
endmodule
//
// tdo connect to tdo of bscan module
// data_reg the data to the design, from jtag_ddt host
// cap the data to jtag_ddt host from design
// shift connect to shift of bscan module
// tdi connect to tdi of bscan module
// sel connect to select of bscan module
// jtag_reset connect to jtag_reset of bscan module
// drck connect to drck of bscan module
// update connect to update of bscan module
//
module jtag_dr (tdo,data_reg,cap,shift,tdi,sel,jtag_reset,drck,update);
parameter REG_SIZE = 32;
input [REG_SIZE - 1:0] cap;
input shift,tdi,sel,jtag_reset,drck,update;
output [REG_SIZE - 1:0] data_reg;
output tdo;
wire [REG_SIZE - 1:0] sr_in;
reg [REG_SIZE - 1:0] sr;
reg [REG_SIZE - 1:0] data_reg;
assign sr_in = shift ? {tdi,sr[REG_SIZE - 1:1]} : cap;
assign tdo = sr[0];
always @ (posedge drck)
if (jtag_reset) begin
sr <= 0;
end
else begin
sr <= sr_in;
end
always @ (posedge update)
if (jtag_reset) begin
data_reg <= 0;
end
else begin
if (sel)
data_reg <= sr;
end
endmodule
Philip Freidin
Fliptronics
Article: 54797Steve Knapp <steve.knapp@xilinx.com> wrote: : Sorry, I was referring to the Avnet site. : I'll make sure that our distribution manager sees this. Perhaps show him http://www.altera.com/products/devices/cyclone/overview/cyc-overview.html about a public statement for the production availability status of parts. I never saw such a thing for Xilinx. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54798
"Robert Finch" <robfinch@sympatico.ca> wrote in message news:<jNFna.5378$KH1.690502@news20.bellglobal.com>... > > SOC-bus protocol that allows for pipelining and is user-configurable, > > Just curious, why does it have to be pipelined ? Can't fifo's be used ? I think what he really means is that it is fully synchronous. E.g. he wants that the ACK signal is not asynchronously generated from the STROBE signal. Just a Wild Guess ! BTW: I thought that WISHBOINE fixed that and optionally can be fully synchronous. I think this is in the latest revision. > > manufacturer independent... and free of fees. :-) > > > Rob Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <---Article: 54799
billh40@aol.com (Bill Hanna) wrote in message news:<97d137ce.0304171001.5ec5461d@posting.google.com>... > I have been designing a Digital Signal Processor using the XC2V4000 > chip. > Software errors in ISE 4.2 and 5.1 have caused long hours of delay in > developing the design: > > Software bugs in SystemAce causes erase problems in the MPM. > Deleting signal wires in ECS causes Fatal errors that crash the > system. > A large design exceeds the 2GB memory limit and generates a fatal > memory error. > > I have designed Altera chips for over 6 years and never had a > problem. > > All digital designers should stop designing new projects with > Xilinx ICs until Xilinx corrects all software problems with ISE. > > Bill Hanna In that case I think we need to boycott both Xilinx and Altera ;*) I had so many problems with both of them ... (actually in my case, I had more problems with Quartus than ISE). But really what we need to look at is the root of the problem: The OS you are running the tools on. Let me guess, you are using some version of Windoze, aren't you ? I have stopped upgrading ISE since Version 4.2 and will not upgrade until they have a linux version. It supports all parts I need and will most likely need for the long future. Spartan 3 sounds very interesting, when that becomes widely available I have to reevaluate my decision. In my entire office, we have only ONE Laptop with Windows NT JUST for Xilinx ISE. Over 50 PCs with Linux, running all kinds of software to make ASICs. This has been our setup for about 3 years now - absolutely no complains. And while we at it, lets boycott Phillips until they make more reliable fluorescent (Ecotone) light bulbs that last more than 4 months, when the box claims they supposed to last 6 years (may be 4 months in Netherlands are equivalent to 6 years elsewhere, I have to check with their Government). They charge about $10 for the 20W one, but no dealer so far would replace them and uphold this warranty claim even though I have all receipts ... what a rip-off ! rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <---
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