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Hello, I recently aqquired a spartan2e fpga based prototyping board with a default usb interface. I am interested in finding out where I can find resources to get cores such as a risc cpu core that I can integrate with a software program.Thanks!, if more detail is needed please let me know.Article: 53626
Hello, I recently aqquired a spartan2e dev board with a usb programming interface (uses cypress ez chip). I am very new to fpgas and curious as to where I can find a fpga core that is a cpu such as risc or cisc. Something just very simple so that I can attempt to send the cpu a command such as add two values or decrementing/incrementing a value. If anyone can help me with this I would be very grateful with any suggestions. Thank you.Article: 53627
It's all done, allready. You can simply take the Xilinx download cable type III, write an spi driver and flash your serial data flash. That's exactly what I do in my systems. However I use the 2MBit version. You will get up to 4..8Mbit ~2US$ that hat ISP capability.... If someone is interested I can help, however the knowledge is not free, since I did invest some time to make it working ... markus "Jim Granville" <jim.granville@designtools.co.nz> schrieb im Newsbeitrag news:3E763BDA.5E7A@designtools.co.nz... > Peter C. Wallace wrote: > > > > I just tested sucessfully a very simple and inexpensive serial > > Flash EEPROM configuration device for SpartanII and IIE 100K gate or > > smaller. I was using a PIC with a serial EEPROM before but with this > > specific chip all thats needed is one inverter from /SYSRESET to > > SYSRESET needed to generate falling /CS edge for the flash. > > > > Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) > > > > Connections: > > > > FLASH DI = TIED HIGH > > FLASH SCLK = FPGA CCLK > > FLASH DO = FPGA D0 > > FLASH /RESET = /SYSRESET = FPGA /PROGRAM > > FLASH /CS = SYSRESET (note inversion) > > FLASH /WP = /SYSRESET > > > > FPGA configuration set for master slave mode. This works because the > > 45LF010 has a read command of FF (DI tied high) and supports sequential > > bit readout.What happens is the first config clocks shift in a FF command > > (read) and an 1FFFF address. Subsequent clocks read the data from > > 1FFFF,0,1, etc etc > > Very clever - so you just need careful file alignment to go ? > > IIRC this family also has bigger siblings, also in SO8 > > Q: why is WP tied to sysreset, and not disabled ? > What about ISP of the 45LF, did you try that ? > -jg -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 53628
Have a look at Xilinx PicoBlaze 8-bit soft controller, OR the 32-bit risc architecture MicroBlaze. Here's a quick link : http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Processor+Centr al "newdevkit" <n/a@n/a.com> wrote in message news:ee7c6c4.-1@WebX.sUN8CHnE... Hello, I recently aqquired a spartan2e dev board with a usb programming interface (uses cypress ez chip). I am very new to fpgas and curious as to where I can find a fpga core that is a cpu such as risc or cisc. Something just very simple so that I can attempt to send the cpu a command such as add two values or decrementing/incrementing a value. If anyone can help me with this I would be very grateful with any suggestions. Thank you.Article: 53629
Hello.. I am looking for a low pinout (~16),3V logic & low power cpld for a hobby application. Gate count is not an issue as the logic required for my purposes is fairly minimal. The BIG issue is package size and power dissipation. Any suggestions would be welcomed. Thanks.. -- Jim Flanagan james_r_flanagan@raytheon.comArticle: 53630
hello,everyone:
who can help me introduce Strict Priority scheduling algorithm?
Article: 53631The lowest-power CPLD is Xilinx CoolRunner, but it is much more complex and has more pins than what you want. Check the Fairchild product line, they seem to have a lot of simple things, but most likely not in hobby-friendly through-hole packages... Sorry to say, it's not your grandfather's hobby-world anymore... (Been there, done that! ) Peter Alfke James Flanagan wrote: > > Hello.. > I am looking for a low pinout (~16),3V logic & low power cpld for > a hobby application. Gate count is not an issue as the logic required > for my purposes is fairly minimal. The BIG issue is package size and > power dissipation. Any suggestions would be welcomed. > > Thanks.. > > -- > Jim Flanagan > james_r_flanagan@raytheon.comArticle: 53632
Homework?? You haven't worked very hard... Just Google "vhdl priority" or "verilog priority" and you'll be overwhelmed with info!! "Apollo" <chen.songwei@mail.zte.com.cn> wrote in message news:913ddf38.0303180609.63447374@posting.google.com... > hello,everyone: > who can help me introduce Strict Priority scheduling algorithm?Article: 53633
Have you looked at existing products? Xilinx's System Generator is a simulink
to VHDL tool that works reasonably well. Accelchip has a new offering out
that takes matlab code and produces generic VHDL that is not tied to a
specific vendor. Either one may be a good starting point for you rather
than starting from scratch.
Michael Gauckler wrote:
> Hello,
>
> we are currently working on a project to integrate Modelsim, a FPGA board
> and Simulink. I am wondering if anybody in this newsgroup is interested in
> this.
>
> The idea is to enable the step by step implementation and simulation of a
> system level design (defined in Simulink) in VHDL. This is achieved by an
> automatic VHDL interface generation from the Simulink model and Simulink
> extensions which allow the simultaneous simulation of the system level
> design with parts thereof implemented in VHDL (simulated with Modelsim
> and/or emulated on the FPGA).
>
> If your interested to know more about this project, write me at
> mgauckle@ee.ethz.ch.
>
> - Michael
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53634In comp.arch.fpga Vijayvithal Jahagirdar <jahagirdar@nojunk.ti.com> wrote: : Sync resets may not reach all flops in a multiple clock domain case where : some clocks are gated off at powerup hence it is better to assert reset : asynchronously and deassert it synchronously : regards It is very important that you asynchronously control the state of any flop that controls the state of an external pin. But if a flop is buried deep inside your logic and its output is only seen by other deeply buried flops then who cares if it doesn't go to known state until the first clock edge? My last chip had 60,000 flops and only about 150 of them had any direct control of an IO pad.Does it make sense to put an async reset on ALL those flops or only the 150 that really need it? If you use async then you are forcing the compiler to select a very specific logic implementation. By using sync you allow synthesis the opportunity to logic reduce the reset along with all the other sync signals. That logic reduction is very important. A lot of designers will put an async reset on every flop and force them into a known state at powerup. But if you are designing for an embedded product that is always powered up then it is "prudent" to design in the ability for software to do a "soft" reset on selected internal blocks. By resetting blocks when they are idle you reduce the chances that a random disruption would force the customer to power cycle. These "soft" resets are effectivly sync resets that place the circuit in the same state as the async reset. If you had used a sync reset for powerup then these would be combined together by synthesis for a net overall savings of gates. John EatonArticle: 53635
Larry Doolittle wrote: > On Fri, 14 Mar 2003 16:16:58 -0700, Roy White <whiter@xilinx.com> wrote: > > > >Windows 2000 dll's on WINE were not compatible with 5.1i. You can find the > >information on this in the "Configuring WINE for Xilinx" section of the 5.1i > >Release and Installation Guide. > > Doh! I had read this once, but ingored it this week. > > >Both your Red Hat and Wine versions are newer > >than those supported for the 5.1i release, but I have not heard of any major > >issues with them, so I doubt they are the problem. > > Assuming I use Windows NT configuration, how will I know when > I find the right samlib.dll, netapi32.dll, and netrap.dll? You'll know if you an run "wine map" w/o errors using the NT compatibility command line switch. As long as you get them from an NT environment, it should be fine. I'll also point out that, unlike Windows, using W98 dll's vs. NT does not affect the stability or operation of the WINE environment or Xilinx tools either way - i.e. NT dll's are not more stable. WINE uses these dll's for API calls that control GUI display behavior. Its typically been easier to use your own licensed W98 SE disk to obtain the dll's, and there is less complexity in WINE command line switches than in emulating NT. > > Wine includes a builtin netapi32.dll, is that OK? Shall I > try www.dll-files.com for the other two? Why didn't Xilinx include these files > in the kit? The source of obtaining your dll's is up to you. Xilinx does not provide them because they aren't licensed for re-distribution by Microsoft. > Do the Xilinx-supplied w2k > DLLs in config/redist/w2k work with Wine in NT emulation mode? These dll's will work fine for running the 5.1i tools, but they are not the entire set of dll's that you need for WINE. You still need to follow the "configuring WINE for Xilinx" steps that include all the dll's needed for the WINE environment. > > > >I agree you are very close, and if needed, our support engineers will be > >able to help you sort out your dll issues. > > I hope so, just as soon as I am cleared to open a WebCase. Please include a copy of your "config" file with your case. It speeds up the process. > > > > - LarryArticle: 53636
Hi Pete, I haven't done this personally but several of my colleagues have with success. If you haven't done so already, check out the hierarchy display after you compile a design with SOPC Builder logic in Quartus - you should see most peripherals (master or slave) displayed as individual entities in the compilation hierarchy - this makes it easy to logic lock entire peripherals (or just portions of them). I'd recommend reading the logic lock app note (AN 161 - see the section on creating logic lock regions with the hierarchy window) if you haven't already as it shows how to lock down these entities. One word of advise.. if you're planning on subtle changes to the system (adding/removing peripherals or changing the bus interconnects), then I would not logic lock the 'arbitrator' entities down, as these will change when (for example) you connect another master up to a slave. We did some experiments quite awhile ago logic-locking the Nios CPU and saw that it was useful in cases where (as an example) you needed to raise clock speed by an extra 10% or so - this was around the time Nios 2.0 was released, working with Apex. I suggest checking out the "README_LogicLock.txt" file in the "80_mhz_32" design for the Nios-Apex development board. Regards, Jesse Kempa Embedded Apps. Engr. Altera jkempa @ altera . com (nospam: remove spaces) petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0303170706.2862ba65@posting.google.com>... > Has anyone tried using LogicLock with slaves or masters placed using > Altera's SOPC Builder? > > Would this be possible? > > Thanks for your time. > > -- PeteArticle: 53637
James Flanagan wrote: > > Hello.. > I am looking for a low pinout (~16),3V logic & low power cpld for > a hobby application. Gate count is not an issue as the logic required > for my purposes is fairly minimal. The BIG issue is package size and > power dissipation. Any suggestions would be welcomed. There are no 16 pin SPLDs, but look at these 24 pin ones Atmel ATF22V10CQZ - available in TSSOP24 ICT PEEL22CV10Z - available in TSSOP24 Philips/Xilinx P3Z22V10/XCR22V10 - now defunct, but some are still about (IIRC only in SO24W ) Lattice have a new 22V10Z, but it is not 3.3V cored. Or, you can use multiple TinyLogic devices -jgArticle: 53638
Let me add to this that every flip-flop in every Xilinx FPGA ever manufactured ( note the strong statement!) is being held reset ( or set, your option) during the configuration process. This is invisible hardware that does not need any synthesis or other software. During configuration all flip-flops are frozen, and all I/O are 3-stated. But the clocks are running, and the internal logic works. The only tricky issue is the trailing edge of this automatic (re)set. If the distribution of this trailing edge, even though it is (optionally) automatically synchronized to the user clock, takes more than one user-clock period, the wake-up may not be entirely clean. Please excuse the convoluted language, but I wanted to be unambiguously clear... Peter Alfke, Xilinx Applications John Eaton wrote: > > In comp.arch.fpga Vijayvithal Jahagirdar <jahagirdar@nojunk.ti.com> wrote: > : Sync resets may not reach all flops in a multiple clock domain case where > : some clocks are gated off at powerup hence it is better to assert reset > : asynchronously and deassert it synchronously > : regards > > It is very important that you asynchronously control the state of any flop > that controls the state of an external pin. But if a flop is buried deep > inside your logic and its output is only seen by other deeply buried flops > then who cares if it doesn't go to known state until the first clock edge? > > My last chip had 60,000 flops and only about 150 of them had any direct > control of an IO pad.Does it make sense to put an async reset on ALL those > flops or only the 150 that really need it? If you use async then you are > forcing the compiler to select a very specific logic implementation. By using > sync you allow synthesis the opportunity to logic reduce the reset along > with all the other sync signals. > > That logic reduction is very important. A lot of designers will put an async > reset on every flop and force them into a known state at powerup. But if > you are designing for an embedded product that is always powered up then > it is "prudent" to design in the ability for software to do a "soft" reset > on selected internal blocks. By resetting blocks when they are idle you > reduce the chances that a random disruption would force the customer to > power cycle. These "soft" resets are effectivly sync resets that place > the circuit in the same state as the async reset. If you had used a sync > reset for powerup then these would be combined together by synthesis for > a net overall savings of gates. > > John EatonArticle: 53639
Hello, Xilinx has just released a new version of System Generator for DSP which can perform HDL and Hardware Co-Simulation with Simulink. You can find out more about it at: http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=system_generator Regards, Nabeel ShiraziArticle: 53640
On 18 Mar 2003 02:11:35 -0800, J_Jeniffer@excite.com (Jeniffer) wrote: >Hi all, >Given a bit file and the architecture for which the bit file is compiled, >is there a way, I can covert it back into an ncd file so that I can view >it in an FPGA editor? >Thanx, >Jeniffer No. =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 53641
The beauty of the English language: It takes only two letters to put this issue to rest. Compare that to: Nein, njet, non, nej, and other inefficiencies. :-) Peter AlfkeArticle: 53642
"Utku Ozcan" <utku.ozcan@netas.com.tr.spamela> schrieb im Newsbeitrag news:3E6F7710.1F34FD5A@netas.com.tr.spamela... > > We have design targetted to a XCS30-4-PQ240C which fails during > heat tests. Product is being tested at -20 degrees but our commercial > FPGA is heated with special equipment to +20 degrees on package > surface. > > The point is that the design fails during this testcase, and we wonder > whether it is of a good practice to emulate this test with TEMPERATURE > constraint in UCF file. We would like to hear the experiences around. Hmm. AFAIK the TEMPERATURE constraint only sets the "speed point" of the static timing analysis. Means, a cold chip is faster than a hot chip. So if you decrease the temperature, the design will get faster. If you are lucky, the static timing analysis finds a hold time problem, but I wouldnt bet on this. I guess you must find the problem on your own. A hold time problem is likely, but it can also be a unclean clock domain crossing, a clock skew problem on non-clock nets etc. Good luck. -- MfG FalkArticle: 53643
When I perform par command on the Assembling Phase of Modular Design, PAR tool issued the following error mesage: Loading device database for application par from file "..\..\pims/contador_A/contador_A.ncd". "top" is an NCD, version 2.37, device xc2v1000, package fg456, speed -4 The STEPPING level for this design is 0. FATAL_ERROR:Guide:basgitaskphyspr.c:369:1.17.4.3:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1_0 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria. The design will not be completely placed and routed by Par-Guide Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com What is the problem? Do someone have some idea about it? Regards Eduardo Wenzel Brião Catholic University of Rio Grande do Sul State Porto Alegre City BrazilArticle: 53644
Hi I'm using Xilinx Foundation series 3.1i.I am able to synthesize my design and perform functional simulation.But I'm not able to implement it.The tool gives the following error message >> Automation caused an exception ,exit code 80010105 >> The server threw an exception I tried to run implmentation again and the error was.. >> Specified revision is Invalid I searched the Xilinx support(online)for help.But couldnt find any solution specific for version 3.1.They have provided the solution only for version 1.5. Kindly post me a solution to this problem. Bye Prasanth.AArticle: 53645
If I were working for the competition I wouldn't be posting this but.. For the 1st time I just happened to take a look at the pretty pictures in the archive and was looking at the copper wafer. http://www.xilinx.com/company/press/products/archive.htm I notice that 1 good die is offset (top right) ie the xy row col placement isn't entirely strict for no good obvious reason. If it is indeed the case that wafers can be sawed row by row then independantly col by col I can see a 10% yield increase by sliding the corner clipped rows sideways a bit. Perhaps that would lead to 10% price reduction too! Perhaps a reward or job too! I assume that production wafer layouts are hand or auto nudged to gain max no of good chip placements. Unless I am wrong about variable row scribing & cutting, 10% of your possible yield is down the shute for this particular case. If am right the math is simple. On a square wafer the placement would be 12 by 8 for 96 sites for this device. The 4 corners each lose 3 outside the circle leaving 80. The 4 corners each lose another 4 from badly clipped corners leaving 64. By adjusting the top & bottom 3 rows, 1 more device is yielded per row. Net yield about 70. Nudge the entire array a bit more to get 2 more dies asymetrically, and the grab point moved to a dead zone instead of across 2 dies. Net yield about 72. Perhaps the production wafers are already optimal, if so excuse this comment. Regards JJArticle: 53646
john jakson wrote: > If I were working for the competition I wouldn't be posting this but.. > > For the 1st time I just happened to take a look at the pretty pictures > in the archive and was looking at the copper wafer. > > http://www.xilinx.com/company/press/products/archive.htm What I find interesting is the Virtex die image. If you display a Virtex bitstream as a rectangular binary image with appropriate rows and cols (avail in the data sheet), the resemblance is uncanny. Right down to the little "flecks" you see on each CLB, and the lines across the centre of the chip. It shouldn't be a surprise, but the mapping between the bitstream format and the physical layout of the chip is more or less 1:1. Which probably explains Xilinx' desire to keep it to themselves. johnArticle: 53647
Hello, I am working on a fairly large project on a Xilinx XCV1000, and I am using ISE 5.1i for synthesis. I've tested my design in simulation and it behaves as it is supposed to, but when I program my FPGA, it behaves weirdly. I'm sure that everything is wired correctly and I can get simple VHDL programs to synthesize correctly. I'm certain that the issue isn't timing, I've slowed the clock down to molassas speed. I've spent many hours trying to debug this, and I've had no luck. I was wondering: Does anyone here have some suggestions?? This is really frustrating... Thanks for the help.Article: 53648
"Benoit" <benoit.hamon@elios-informatique.fr> wrote in message news:<b56q11$mo5$1@s1.read.news.oleane.net>...
> Hi,
>
> I need to calculate many CRC32 in a packet of data. So, I would like to
> write a function that I call
> for each CRC, without need to create a new component (with process, specific
> I/O etc...).
>
> See below the begining of my source code.
> Don't you have any idea to implemente this calcul in a FPGA ?.
>
> Thanks in advance.
> Benoit.
> x_in := (data_serie xor xout(31));
>
> xout(0) := x_in;
> xout(1) := (xout(0) xor x_in);
>'''''''''''''''''''''''''''''''''''''''''''''
>'''''''''''''''''''''''''''''''''''''''''''''
> xout(31):= xout(30);
>
> if (xout="11000111000001001101110101111011")
> then CRC_MATCH := '1';
Surely a better way to write this if you were using Verilog (can't say
for VHDL) would be something like
xout[31:0] <= (x_in)? { xout[30:0]^polynomial,1'b1 } : {
xout[30:0],1'b0 };
This synths to as a wire shift with 13 xors in poly 1 bits.
I can say that in a Verilog implementation I was able to do a full
flash CRC16 in about same no of lines of code as here once every
clock, obviously can't give it here. The division coeffs were worked
out with a small C program to count the parities of the division in
progress. C is a wonderful way to work out the math for things like
that. The resulting design allowed for CRC searching through different
candidate inputs.
Where as flash integer division using cond shift subs is expensive in
time & logic, flash polynomial division is much more efficient per
cycle given the cost is a few times more & does 16 or 32 times more
work. Most of the xors just wash out.
To do a parallel version just write the above Verilog assignment in
VHDL 32 times with each x_in bit indexed off the incoming word and
rename the intermediates. Maybe Synopsys can figure the reduction to
minimum xor trees for you.
Not sure if you wanted serial by design or was inferring parallel with
the loop.
Regards
JJ
Article: 53649>I am working on a fairly large project on a Xilinx XCV1000, and I am >using ISE 5.1i for synthesis. I've tested my design in simulation and >it behaves as it is supposed to, but when I program my FPGA, it >behaves weirdly. I'm sure that everything is wired correctly and I can >get simple VHDL programs to synthesize correctly. I'm certain that the >issue isn't timing, I've slowed the clock down to molassas speed. I've >spent many hours trying to debug this, and I've had no luck. I was >wondering: Does anyone here have some suggestions?? This is really >frustrating... Standard debugging problems... How many clocks are you using? Any skew problems? Any kludgy non-synchronous logic? Can you get a scope on a few signals for debugging? (cleanly) Any interesting internal signals to look at? Does it do anything interesting? Any parts of your design working? Can you break up your design into chunks and verify that each chunk works? Perhaps start at the input side and keep adding a chunk at a time. Or make something simple that just does the right timing on the control signals and drops all input data and puts a counter on the output bus. You might have to write some serious debugging (throwaway) code to figure out what the problem is. Get a friend to review your design and BS with you about how to debug it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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