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B. Joshua Rosen <bjrosen@polybus.com> wrote: : You sparked my curiosity, I did a google search and to my surprise the : 7408 in a 14 pin DIP still exists. Fairchild still makes it. : BTW some of you may be surprised that : Fairchild, the mother of all semiconductor firms, still exists. National, : which swallowed in the 80s, spit it out again in the late 90s. : Why are using a 7408 in a modern design? There are some microscopic cmos : devices available that do this function if you really need a piece of SSI. Well if you have an old system with one bad part do you plan on redesigning the whole system of just replacing the bad part? You may buy the latest technology every two or three years but there are some places that measure product life in decades. Besides the new parts may be "faster" but you may find out that the unwritten design specs required a minimum delay for the system to work. John EatonArticle: 53601
You can find the Xilinx and 3rd Party boards list on this quick link http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protobo ards_page "john jakson" <johnjakson@yahoo.com> wrote in message news:adb3971c.0303171027.44de7550@posting.google.com... > "Jerry" <nospam@nowhere.com> wrote in message news:<v7a83s19pgqj31@corp.supernews.com>... > > Tad off subject BUT, > > > > Does anyone know of a FPGA dev board that can be expanded? I know of the > > DINI group that > > has 5 large FPGAs on it but what I'm looking for is a board that can connect > > to other boards > > in order to expand the gate count. > > > > Tks in advance > > Jerry > > > > > At the high end (since you said DINI) Nallatech & AlphaData do boards > that have high pin count doughter boards that you could add more FPGA, > A/D or whatever. There are many more companies around, see the 3rd > fpga board lists at xilinx etc.Article: 53602
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:b555fc$25nton$1@ID-84877.news.dfncis.de... > > Can I use clk6 as global clock for a synchronous design in this device. > > You can, but only if you drive this 6 MHz clock off chip and come back into > on a global clock pad, since AFAIK there is no way to drive a global clock > net in this CPLD from inside (as it is possible with FPGAs). Is the Xc9500XL different? It looks like (from the datasheet) you could drive an unused golbal clock internaly so long as you havn't used the GCK pin for that clock. Is this correct? Thanks RalphArticle: 53603
John Eaton wrote: > > B. Joshua Rosen <bjrosen@polybus.com> wrote: > > : You sparked my curiosity, I did a google search and to my surprise the > : 7408 in a 14 pin DIP still exists. Fairchild still makes it. > > : BTW some of you may be surprised that > : Fairchild, the mother of all semiconductor firms, still exists. National, > : which swallowed in the 80s, spit it out again in the late 90s. > > : Why are using a 7408 in a modern design? There are some microscopic cmos > : devices available that do this function if you really need a piece of SSI. > > Well if you have an old system with one bad part do you plan on redesigning the > whole system of just replacing the bad part? You may buy the latest technology > every two or three years but there are some places that measure product life > in decades. Besides the new parts may be "faster" but you may find out that > the unwritten design specs required a minimum delay for the system to work. The 7408 is at the NFND stage, but it is still available. The 7407 is a good example of a very old device, still shipped in large volumes, and being designed in - 30V on your FPGA pins anyone ? -jgArticle: 53604
On Mon, 17 Mar 2003 14:18:11 -0500, John Eaton wrote: > B. Joshua Rosen <bjrosen@polybus.com> wrote: > > : You sparked my curiosity, I did a google search and to my surprise the > : 7408 in a 14 pin DIP still exists. Fairchild still makes it. > > : BTW some of you may be surprised that Fairchild, the mother of all > : semiconductor firms, still exists. National, which swallowed in the > : 80s, spit it out again in the late 90s. > > : Why are using a 7408 in a modern design? There are some microscopic > : cmos devices available that do this function if you really need a > : piece of SSI. > > Well if you have an old system with one bad part do you plan on > redesigning the whole system of just replacing the bad part? You may buy > the latest technology every two or three years but there are some places > that measure product life in decades. Besides the new parts may be > "faster" but you may find out that the unwritten design specs required a > minimum delay for the system to work. > > John Eaton I don't think that the OP was talking about an old system, why would he have been interested in ESD protection if all he was doing was repairing an antique system.Article: 53605
I just tested sucessfully a very simple and inexpensive serial Flash EEPROM configuration device for SpartanII and IIE 100K gate or smaller. I was using a PIC with a serial EEPROM before but with this specific chip all thats needed is one inverter from /SYSRESET to SYSRESET needed to generate falling /CS edge for the flash. Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) Connections: FLASH DI = TIED HIGH FLASH SCLK = FPGA CCLK FLASH DO = FPGA D0 FLASH /RESET = /SYSRESET = FPGA /PROGRAM FLASH /CS = SYSRESET (note inversion) FLASH /WP = /SYSRESET FPGA configuration set for master slave mode. This works because the 45LF010 has a read command of FF (DI tied high) and supports sequential bit readout.What happens is the first config clocks shift in a FF command (read) and an 1FFFF address. Subsequent clocks read the data from 1FFFF,0,1, etc etc PCWArticle: 53606
Peter C. Wallace wrote: > > I just tested sucessfully a very simple and inexpensive serial > Flash EEPROM configuration device for SpartanII and IIE 100K gate or > smaller. I was using a PIC with a serial EEPROM before but with this > specific chip all thats needed is one inverter from /SYSRESET to > SYSRESET needed to generate falling /CS edge for the flash. > > Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) > > Connections: > > FLASH DI = TIED HIGH > FLASH SCLK = FPGA CCLK > FLASH DO = FPGA D0 > FLASH /RESET = /SYSRESET = FPGA /PROGRAM > FLASH /CS = SYSRESET (note inversion) > FLASH /WP = /SYSRESET > > FPGA configuration set for master slave mode. This works because the > 45LF010 has a read command of FF (DI tied high) and supports sequential > bit readout.What happens is the first config clocks shift in a FF command > (read) and an 1FFFF address. Subsequent clocks read the data from > 1FFFF,0,1, etc etc Very clever - so you just need careful file alignment to go ? IIRC this family also has bigger siblings, also in SO8 Q: why is WP tied to sysreset, and not disabled ? What about ISP of the 45LF, did you try that ? -jgArticle: 53607
On Mon, 17 Mar 2003 13:19:22 -0800, Jim Granville wrote: > Peter C. Wallace wrote: >> >> I just tested sucessfully a very simple and inexpensive serial Flash >> EEPROM configuration device for SpartanII and IIE 100K gate or smaller. >> I was using a PIC with a serial EEPROM before but with this specific >> chip all thats needed is one inverter from /SYSRESET to SYSRESET needed >> to generate falling /CS edge for the flash. >> >> Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) >> >> Connections: >> >> FLASH DI = TIED HIGH >> FLASH SCLK = FPGA CCLK >> FLASH DO = FPGA D0 >> FLASH /RESET = /SYSRESET = FPGA /PROGRAM FLASH /CS = SYSRESET (note >> inversion) FLASH /WP = /SYSRESET >> >> FPGA configuration set for master slave mode. This works because the >> 45LF010 has a read command of FF (DI tied high) and supports sequential >> bit readout.What happens is the first config clocks shift in a FF >> command (read) and an 1FFFF address. Subsequent clocks read the data >> from 1FFFF,0,1, etc etc > > Very clever - so you just need careful file alignment to go ? File alignment is not picky because the FPGA does nothing with the bitstream until the sync word is read > IIRC this family also has bigger siblings, also in SO8 Unfortunately they have a read command of 03 instead of FF, so they will work but need more help to get started > Q: why is WP tied to sysreset, and not disabled ? What about ISP of the WP should probably be tied to a pulldown resistor and brought out to the ISP connector. > 45LF, did you try that ? -jg Not yet but it should be easy, weve done ISP with the same chip using a PIC as a helperArticle: 53608
"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> schrieb im Newsbeitrag news:%uqda.18399$jE3.435878@news.xtra.co.nz... > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:b555fc$25nton$1@ID-84877.news.dfncis.de... > > > Can I use clk6 as global clock for a synchronous design in this device. > > > > You can, but only if you drive this 6 MHz clock off chip and come back > into > > on a global clock pad, since AFAIK there is no way to drive a global clock > > net in this CPLD from inside (as it is possible with FPGAs). > > Is the Xc9500XL different? > > It looks like (from the datasheet) you could drive an unused golbal clock > internaly so long as you havn't used the GCK pin for that clock. ??? I cant see this in the datasheet. But again, Iam not sure. Any other CPLD experts out there? -- MfG FalkArticle: 53609
Hi; I think that you might be running into another issue that you haven't covered yet (at least with the code you supplied). It's not apparent that you've instantiated the startup block or tied into the GSR for the XC4000 family. (You need to do this if you're going to use the external GSR pin to control resets of all internal FFs -- one way around this is to see if your synthesis tool will also let you assign a net to the GSR function). You should be able to find some documentation regarding this topic with either the synthesis tool you're using, Xilinx's web site (searching the answers database), or in the on-line documentation if you've installed it. This might get you on the right path of thinking... -bob Josh Pfrimmer wrote: > > Hi, all... > I'm TAing a 4th year processor design lab, and despite being very > familiar with the tools and VHDL, and having had success in the past, I've > gotten myself stumped on what seems like an extremely simple problem. I'm > hoping the Xilinx/VHDL experts around here can take a minute to point out > my mistake. I will accept mockery, afterwards, for being dumb, if that's > any incentive. > > - Using Foundation 4.1i, creating a new project for an XC4010XLA, HDL flow. > - create a new source file with > - library ieee; > -use ieee.std_logic_1164.all; > -use ieee.std_logic_unsigned.all; > -the appropriate inputs, and only one process: > > process (clk, rst) is > begin > if rst = '1' then > d_out <= '0'; > elsif rising_edge(clk) then > d_out <= din; > end if; > end process; > > Just your standard DFF, with asynchronous clear, right? But every time I > do this, synthesize and simulate, I get the same result: d_out responds to > din just fine, on the rising edge of the clock. But the reset is > ineffectual... no change on dout no matter what the state or activity on > rst. > > Upon closer examination of the signal hierarchy for dout, I notice that I > the tools have instantiated a IFD, rather than the FDE I expect from the > XC4000 library. The IFD has no reset, synchronous or otherwise. Why would > this get optimized out of the design? What can I change, in tool settings > or code, to avoid this? > > Thanks for your time. > > JP > > -- > Josh Pfrimmer, B.Eng. > _________________________________________ > University of Victoria, ECE > jpfrimmer<AT>ece<DOT>uvic<DOT>ca > _________________________________________ > ->My views and opinions are not necessarily UVic'sArticle: 53610
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:b55g48$254tbv$1@ID-84877.news.dfncis.de... > "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> > schrieb im Newsbeitrag news:%uqda.18399$jE3.435878@news.xtra.co.nz... > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > > news:b555fc$25nton$1@ID-84877.news.dfncis.de... > > > > Can I use clk6 as global clock for a synchronous design in this > device. > > > > > > You can, but only if you drive this 6 MHz clock off chip and come back > > into > > > on a global clock pad, since AFAIK there is no way to drive a global > clock > > > net in this CPLD from inside (as it is possible with FPGAs). > > > > Is the Xc9500XL different? > > > > It looks like (from the datasheet) you could drive an unused golbal clock > > internaly so long as you havn't used the GCK pin for that clock. > > ??? > I cant see this in the datasheet. > But again, Iam not sure. > Any other CPLD experts out there? On Page 2 of the XC9500XL datasheet it shows in the bock diagram that the Clocks are taken from the PIN before the IO Block, so I assume that if you drive that pin as an output then that output will also be available on the global clock associated with that pin. Can anyone confirm? Thanks RalphArticle: 53611
Falk Brunner wrote: > "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> > schrieb im Newsbeitrag news:%uqda.18399$jE3.435878@news.xtra.co.nz... >> "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message >> news:b555fc$25nton$1@ID-84877.news.dfncis.de... >>>> Can I use clk6 as global clock for a synchronous design in this >>>> device. >>> >>> You can, but only if you drive this 6 MHz clock off chip and come >>> back into on a global clock pad, since AFAIK there is no way to >>> drive a global clock net in this CPLD from inside (as it is >>> possible with FPGAs). >> >> Is the Xc9500XL different? >> >> It looks like (from the datasheet) you could drive an unused golbal >> clock internaly so long as you havn't used the GCK pin for that >> clock. > > ??? > I cant see this in the datasheet. > But again, Iam not sure. > Any other CPLD experts out there? The 9500XL global clock nets can only be driven from the GCK pins. But since these pins can also be used as normal outputs, you can output the 6 MHz signal on such a pin and then take it in again through the GCK feature of the same pin. This requires that you have a free, unconnected GCK pin, and I had to wrestle quite a bit with the synthesizer and fitter to prevent them from optimizing this arrangement away. It uses one macrocell for the clock output pin, and no product terms in the clocked macrocells since the GCK net is "free". It is an advantage if you are short of product terms in the clocked macrocells. If you don't do this, the fitter will use product-term clocks. It costs one of the five product terms per macrocell and is much easier to implement. It gives a little longer Tco. If the Tco is a problem, you can clock the clocked macrocells by the fast clock, and make a clock-enable from your divide-by-8 counter. The clocks are now "free" (provided you feed the 48 MHz into a GCK pin), but the clock-enables now cost a product term in each clocked macrocell. Karl OlsenArticle: 53612
In article <b54418$s18$1@dennis.cc.strath.ac.uk>, aeu96186 _MENOWANTSPAM@yahoo.co.uk says... > [...] with all of the connections > labelled with their Sunday name.....? What's a Sunday name?Article: 53613
Ralph Mason wrote: > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:b55g48$254tbv$1@ID-84877.news.dfncis.de... > > "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> > > schrieb im Newsbeitrag news:%uqda.18399$jE3.435878@news.xtra.co.nz... > > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > > > news:b555fc$25nton$1@ID-84877.news.dfncis.de... > > > > > Can I use clk6 as global clock for a synchronous design in this > > device. > > > > > > > > You can, but only if you drive this 6 MHz clock off chip and come back > > > into > > > > on a global clock pad, since AFAIK there is no way to drive a global > > clock > > > > net in this CPLD from inside (as it is possible with FPGAs). > > > > > > Is the Xc9500XL different? > > > > > > It looks like (from the datasheet) you could drive an unused golbal > clock > > > internaly so long as you havn't used the GCK pin for that clock. > > > > ??? > > I cant see this in the datasheet. > > But again, Iam not sure. > > Any other CPLD experts out there? > > On Page 2 of the XC9500XL datasheet it shows in the bock diagram that the > Clocks are taken from the PIN before the IO Block, so I assume that if you > drive that pin as an output then that output will also be available on the > global clock associated with that pin. > > Can anyone confirm? This works on Atmel CPLDs, & should on any where a GLKC is also IO - but as someone else mentioned, the challenge is not so much the silicon ability, as convincing the tool-flow of your intentions :) -jgArticle: 53614
Which version of Foundation are you using? This is the first year we've gone with 4.1, and while results aren't completely in yet, we don't seem to be having too many problems (especially since applying the workarounds noted earlier in the thread). Last year we used 3.1, and I _know_ we could make async. clear DQ ffs. JP "David Binnie" <david.binnie@btinternet.com> wrote in message news:b55eti$qli$1@helle.btinternet.com... > My finding is that the async reset does not simulate after synthesis usu=ing > Foundation software when you target an XC4000 device. Retarget the same > code to Virtex then then it does. Maybe a bug ? > There is an async reset on the chip which I haven't actually tested. > > > Josh Pfrimmer <yeah_spam_me@thisaddress.com> wrote in message > news:b55583$25demb$1@ID-132015.news.dfncis.de... > > I'm sorry, I don't understand this. Do you mean that it is impossible to > > infer FFs in an XC4000 (specifically, XC4010XLA) which have an > aysnchronous > > reset? If so, I'm afraid you're mistaken. > > > > http://direct.xilinx.com/bvdocs/publications/4000.pdf - Page 7, top, > > Set/Reset > > > > > > JP > > > > "David Binnie" <david.binnie@btinternet.com> wrote in message > > news:b55288$6d5$1@helle.btinternet.com... > > > 4000 series does not facilitate async reset > > > > > > > > > Josh Pfrimmer <yeah_spam_me@thisaddress.com> wrote in message > > > news:b4ret3$22m2l9$1@ID-132015.news.dfncis.de... > > > > Hi, all... > > > > I'm TAing a 4th year processor design lab, and despite being very > > > > familiar with the tools and VHDL, and having had success in the past, > > I've > > > > gotten myself stumped on what seems like an extremely simple problem. > > I'm > > > > hoping the Xilinx/VHDL experts around here can take a minute to point > > out > > > > my mistake. I will accept mockery, afterwards, for being dumb, if > > that's > > > > any incentive. > > > > > > > > - Using Foundation 4.1i, creating a new project for an XC4010XLA, HDL > > > flow. > > > > - create a new source file with > > > > - library ieee; > > > > -use ieee.std_logic_1164.all; > > > > -use ieee.std_logic_unsigned.all; > > > > -the appropriate inputs, and only one process: > > > > > > > > process (clk, rst) is > > > > begin > > > > if rst = '1' then > > > > d_out <= '0'; > > > > elsif rising_edge(clk) then > > > > d_out <= din; > > > > end if; > > > > end process; > > > > > > > > Just your standard DFF, with asynchronous clear, right? But every > time > > I > > > > do this, synthesize and simulate, I get the same result: d_out > responds > > to > > > > din just fine, on the rising edge of the clock. But the reset is > > > > ineffectual... no change on dout no matter what the state or activity > > on > > > > rst. > > > > > > > > Upon closer examination of the signal hierarchy for dout, I notice > that > > I > > > > the tools have instantiated a IFD, rather than the FDE I expect from > > the > > > > XC4000 library. The IFD has no reset, synchronous or otherwise. Why > > > would > > > > this get optimized out of the design? What can I change, in tool > > settings > > > > or code, to avoid this? > > > > > > > > Thanks for your time. > > > > > > > > JP > > > > > > > > -- > > > > Josh Pfrimmer, B.Eng. > > > > _________________________________________ > > > > University of Victoria, ECE > > > > jpfrimmer<AT>ece<DOT>uvic<DOT>ca > > > > _________________________________________ > > > > ->My views and opinions are not necessarily UVic's > > > > > > > > > > > > > > > > > > > >Article: 53615
Hi,
thanks....
I'm not explicitly using the STARTUP block. I've gotten into the habit of
coding all my flops with the style above, that is, as a process dependant
only on clock and reset, and with the first line being
if reset = '1' then
My question is, then... will the synthesis software recognize this,
generally, and map the GSR (from STARTUP) to all the flops in my project?
A corollary question is: If I expressly instantiate STARTUP, should I be
including that line of code in all my flops?
JP
"Robert Myers" <rjmyers@raytheon.com> wrote in message
news:3E76486D.92B8B2BC@raytheon.com...
> Hi;
>
> I think that you might be running into another issue
> that you haven't covered yet (at least with the code you supplied).
>
> It's not apparent that you've instantiated the startup block or
> tied into the GSR for the XC4000 family. (You need to do this if
> you're going to use the external GSR pin to control resets of all
> internal FFs -- one way around this is to see if your synthesis tool
> will also let you assign a net to the GSR function). You should be
> able to find some documentation regarding this topic with either
> the synthesis tool you're using, Xilinx's web site (searching the
> answers database), or in the on-line documentation if you've installed
> it.
>
> This might get you on the right path of thinking...
>
> -bob
>
> Josh Pfrimmer wrote:
> >
> > Hi, all...
> > I'm TAing a 4th year processor design lab, and despite being very
> > familiar with the tools and VHDL, and having had success in the past,
I've
> > gotten myself stumped on what seems like an extremely simple problem.
I'm
> > hoping the Xilinx/VHDL experts around here can take a minute to point
out
> > my mistake. I will accept mockery, afterwards, for being dumb, if
that's
> > any incentive.
> >
> > - Using Foundation 4.1i, creating a new project for an XC4010XLA, HDL
flow.
> > - create a new source file with
> > - library ieee;
> > -use ieee.std_logic_1164.all;
> > -use ieee.std_logic_unsigned.all;
> > -the appropriate inputs, and only one process:
> >
> > process (clk, rst) is
> > begin
> > if rst = '1' then
> > d_out <= '0';
> > elsif rising_edge(clk) then
> > d_out <= din;
> > end if;
> > end process;
> >
> > Just your standard DFF, with asynchronous clear, right? But every time
I
> > do this, synthesize and simulate, I get the same result: d_out responds
to
> > din just fine, on the rising edge of the clock. But the reset is
> > ineffectual... no change on dout no matter what the state or activity
on
> > rst.
> >
> > Upon closer examination of the signal hierarchy for dout, I notice that
I
> > the tools have instantiated a IFD, rather than the FDE I expect from
the
> > XC4000 library. The IFD has no reset, synchronous or otherwise. Why
would
> > this get optimized out of the design? What can I change, in tool
settings
> > or code, to avoid this?
> >
> > Thanks for your time.
> >
> > JP
> >
> > --
> > Josh Pfrimmer, B.Eng.
> > _________________________________________
> > University of Victoria, ECE
> > jpfrimmer<AT>ece<DOT>uvic<DOT>ca
> > _________________________________________
> > ->My views and opinions are not necessarily UVic's
Article: 53616
Perhaps he mis-typed sundry?
Walter Harley wrote:
> In article <b54418$s18$1@dennis.cc.strath.ac.uk>, aeu96186
> _MENOWANTSPAM@yahoo.co.uk says...
> > [...] with all of the connections
> > labelled with their Sunday name.....?
>
> What's a Sunday name?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 53617
Josh Pfrimmer wrote:
> Hi,
> thanks....
>
> I'm not explicitly using the STARTUP block. I've gotten into the habit of
> coding all my flops with the style above, that is, as a process dependant
> only on clock and reset, and with the first line being
> if reset = '1' then
> My question is, then... will the synthesis software recognize this,
> generally, and map the GSR (from STARTUP) to all the flops in my project?
> A corollary question is: If I expressly instantiate STARTUP, should I be
> including that line of code in all my flops?
The normal way to do that is to put into your top level vhdl code this
small fragment, to drive the reset lines that we want to be controlled
by GSR.
-- model of the Xilinx POR
roc_dev: roc
port map(
O => RESET
);
The roc model is already available in the Xilinx supplied unisim library
(notice that you will no longer drive it from your testbench), and the
other tools also understand it and will understand to attach those
points to the internal GSR.
--
My real email is akamail.com@dclark (or something like that).
Article: 53618In article <b55jiq$6e2$1@216.39.172.65>, walterh@cafewalter.com says... > In article <b54418$s18$1@dennis.cc.strath.ac.uk>, aeu96186 > _MENOWANTSPAM@yahoo.co.uk says... > > [...] with all of the connections > > labelled with their Sunday name.....? > > What's a Sunday name? All dolled up, ready for marketing. ;-) -- KeithArticle: 53619
"Gerardo Sosa" <gerardo_sr@yahoo.com> wrote in message
news:f4ee0441.0303131800.6b12ff0f@posting.google.com...
> Hi, I hope that somebody can help me, because I don't know
what more
> to do.
> I'm trying to integrate a VHDL component in a project in
Handel-C.
> DK-1 generate an .edf file and I create a new project in
ISE 5 and add
> this .edf, and try to synthesize, but I obtain the
following error in
> ISE:
>
> ERROR:NgdBuild:604 - logical block
> 'B90_reg32x1k_test_98_main_registers' with
> type 'reg32x1k1' could not be resolved. A pin name
misspelling can
> cause
> this, a missing edif or ngc file, or the misspelling of
a type
> name. Symbol
> 'reg32x1k1' is not supported in target 'virtexe'.
>
> And the interface in Handel-c for the vhdl component is:
>
> interface reg32x1k1(unsigned 32 data_out)
> registers(unsigned 10 address = addressVal with {extpath
> {registers.data_out}},
> unsigned 32 data_in = data_inVal,
> unsigned 1 ck = __clock,
> unsigned 1 write = writeVal);
>
It looks like Xilinx can't find the edif file for the
component.
The simplest way to do this is to copy the edif output from
your VHDL
synthesis tool into the project directory of Xilinx 5.1. If
both edif
files are in the same directory, then it "should just work"
:-)
The edif file name must be exactly 'reg32x1k1.edf' and in
the project
or it won't find it.
regards
Alan
--
Alan Fitch
www.doulos.com
Article: 53620"Keith R. Williams" <krw@attglobal.net> wrote in message news:MPG.18e05556eff9272098a155@enews.newsguy.com... > In article <b55jiq$6e2$1@216.39.172.65>, walterh@cafewalter.com > says... > > In article <b54418$s18$1@dennis.cc.strath.ac.uk>, aeu96186 > > _MENOWANTSPAM@yahoo.co.uk says... > > > [...] with all of the connections > > > labelled with their Sunday name.....? > > > > What's a Sunday name? > > All dolled up, ready for marketing. ;-) I think thats what I meant!Article: 53621
Hi,
I need to calculate many CRC32 in a packet of data. So, I would like to
write a function that I call
for each CRC, without need to create a new component (with process, specific
I/O etc...).
See below the begining of my source code.
Don't you have any idea to implemente this calcul in a FPGA ?.
Thanks in advance.
Benoit.
________________________________________________________
type stock_pq is array (0 to 20) of std_logic_vector(7 downto 0);
....
FUNCTION fct_crc32 (paq_teste : stock_pq ) return std_logic is
variable xout : std_logic_vector (31 downto 0) := (others=> '1');
variable data_octet : std_logic_vector(7 downto 0) := "00000000";
variable data_serie : std_logic :='0';
variable x_in : std_logic :='0';
variable CRC_MATCH : std_logic :='0';
BEGIN
For i in paq_teste'range loop
data_octet := paq_teste(i);
For j in 0 to 7 loop
data_serie := data_octet(j);
x_in := (data_serie xor xout(31));
xout(0) := x_in;
xout(1) := (xout(0) xor x_in);
xout(2) := (xout(1) xor x_in);
xout(3) := xout(2);
xout(4) := (xout(3) xor x_in);
xout(5) := (xout(4) xor x_in);
xout(6) := xout(5);
xout(7) := (xout(6) xor x_in);
xout(8) := (xout(7) xor x_in);
xout(9) := xout(8);
xout(10):= (xout(9) xor x_in);
xout(11):= (xout(10) xor x_in);
xout(12):= (xout(11) xor x_in);
xout(13):= xout(12);
xout(14):= xout(13);
xout(15):= xout(14);
xout(16):= (xout(15) xor x_in);
xout(17):= xout(16);
xout(18):= xout(17);
xout(19):= xout(18);
xout(20):= xout(19);
xout(21):= xout(20);
xout(22):= (xout(21) xor x_in);
xout(23):= (xout(22) xor x_in);
xout(24):= xout(23);
xout(25):= xout(24);
xout(26):= (xout(25) xor x_in);
xout(27):= xout(26);
xout(28):= xout(27);
xout(29):= xout(28);
xout(30):= xout(29);
xout(31):= xout(30);
if (xout="11000111000001001101110101111011")
then CRC_MATCH := '1';
end if;
end loop;
end loop;
return CRC_MATCH;
END;
....
result_CRC32_1 <= fct_crc32(paq_teste) when EO_P = '1'
else '0';
Article: 53622Hi all, Given a bit file and the architecture for which the bit file is compiled, is there a way, I can covert it back into an ncd file so that I can view it in an FPGA editor? Thanx, JenifferArticle: 53623
Hello, we are currently working on a project to integrate Modelsim, a FPGA board and Simulink. I am wondering if anybody in this newsgroup is interested in this. The idea is to enable the step by step implementation and simulation of a system level design (defined in Simulink) in VHDL. This is achieved by an automatic VHDL interface generation from the Simulink model and Simulink extensions which allow the simultaneous simulation of the system level design with parts thereof implemented in VHDL (simulated with Modelsim and/or emulated on the FPGA). If your interested to know more about this project, write me at mgauckle@ee.ethz.ch. - Michael
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