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Nicholas C. Weaver <nweaver@ribbit.cs.berkeley.edu> wrote: : In article <v8rmpv5vivi8b8@corp.supernews.com>, : Scott <scott_howes@hotmail.com> wrote: :>I'm using the XL mainly because it is convient and I have ax Xess :>development board that is designed for it....but I could use the Spartan I :>suppose. : Life will be SO much happier for you if you use a currently supported : part. But don't go to the other extreme, with BGA or even fine-pitch BGA for prototyping... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54276
rickman <spamgoeshere4@yahoo.com> wrote: >The Webpack does not have a chip editor. It does have a floorplanner, but I'm not sure how much to trust it in this case. If you run a simple design through on the only 5.2i WebPACK-supported Spartan-3 device (3S50) you can see a device with a Virtex-2 style of CLB layout, but with an apparent complete lack of DCMs, BRAMs and multipliers. It does seem to have about 3x the CLBs of the 2V40, though, if I'm counting correctly. I'm not sure I believe that, but as long as we're in rampant speculation mode... Obviously even if the above is true, it doesn't imply the whole family will be like this; it may just be the teeniest one that's just "all CLBs". -- IanArticle: 54277
Ian Young <ian@iay.org.uk> wrote: : rickman <spamgoeshere4@yahoo.com> wrote: :>The Webpack does not have a chip editor. : It does have a floorplanner, but I'm not sure how much to trust it in : this case. If you run a simple design through on the only 5.2i : WebPACK-supported Spartan-3 device (3S50) you can see a device with a : Virtex-2 style of CLB layout, but with an apparent complete lack of : DCMs, BRAMs and multipliers. It does seem to have about 3x the CLBs : of the 2V40, though, if I'm counting correctly. : I'm not sure I believe that, but as long as we're in rampant : speculation mode... : Obviously even if the above is true, it doesn't imply the whole family : will be like this; it may just be the teeniest one that's just "all : CLBs". Download the most recent lib.pdf, and you will find what macros the XC3S has. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54278
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >Ian Young <ian@iay.org.uk> wrote: [...] >: Obviously even if the above is true, it doesn't imply the whole family >: will be like this; it may just be the teeniest one that's just "all >: CLBs". > >Download the most recent lib.pdf, and you will find what macros the XC3S has. Thanks, that's very useful. Yes, the Spartan-3 seems from that manual to have essentially the same set of primitives as the Virtex-2s, so at least some Spartan-3s have the usual collection of bits and bobs like multipliers. That's what I would have expected; the XC3S50 the WebPACK knows about was surprising. Poking around a bit more with the WebPACK software, though, although you can get XST to infer multiplier blocks for Spartan-3, it's pretty clear that the XC3S50 doesn't have any: Number of MULT18X18s: 1 out of 0 0% (OVERMAPPED) I hope Xilinx feel they can open the WebPACK to some of the more generally useful devices by the time the chips actually become available. -- IanArticle: 54279
Ian Young wrote: > rickman <spamgoeshere4@yahoo.com> wrote: > >> The Webpack does not have a chip editor. > > It does have a floorplanner, but I'm not sure how much to trust it in > this case. If you run a simple design through on the only 5.2i > WebPACK-supported Spartan-3 device (3S50) you can see a device with a > Virtex-2 style of CLB layout, but with an apparent complete lack of > DCMs, BRAMs and multipliers. It does seem to have about 3x the CLBs > of the 2V40, though, if I'm counting correctly. > > I'm not sure I believe that, but as long as we're in rampant > speculation mode... > > Obviously even if the above is true, it doesn't imply the whole family > will be like this; it may just be the teeniest one that's just "all > CLBs". According to FPGA Editor in 5.2i SP1, the XC3S50 has no block RAM, no multipliers, and no DCMs. And when I tried to implement a circuit that used a block RAM, it did indeed fail. Only the larger devices (XC3S200+) have block RAMs, multipliers and DCMs. The XC3S50 has the same number of LUTs+FFs as the XC2S50E but no BRAMs, so I wonder how Xilinx can suggest, by the naming, that it is a "50,000 gate" chip, since many of the "50,000 gates" in an XC2S50E are in the BRAMs. And I wonder what a device with 1536 LUTs+FFs and no BRAMs and DCMs can be used for... Karl OlsenArticle: 54280
In article <qhy92n486g.fsf@ruckus.brouhaha.com>, eric-no-spam-for- me@brouhaha.com says... > John Larkin <John.Larkin> writes: > > why not just use a linear LDO (LM1117 or whatever) from +5 or +3.3? > > That's a lot cheaper and simpler. > > Because there's not much 5V available. > > I'm not sure about the LM1117, but the MAX1818 that Xilinx recommends > (due to its current limiting behavior) seems to be made of 100% unobtanium. > I think Maxim makes all of its parts out of "unobtanium". I've quit even trying to use them just for that reason. If DigiKey don't have them in stock don't even try to use them... TI and Micrel make some nice LDO's and you can actually purchase them :) -- Greg Deuerling Fermi National Accelerator Laboratory P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629 FAX (630)840-5406 Electronic Systems Engineering Group Work: egads_AT_fnal.gov, remove '_AT_'Article: 54281
Hello , recently i did a test on the coolrunner 2 , by having all ones
on the output when rising clock input is one and zeros when falling
clock input , i used the coolrunner2 's dualedge feature.
The problem : i notice that all the output do not fall at the same time
, some outputs do match , but others don't match.
Oscilloscope set to 1ns time step
Output as below:
----\
1 \
\
--------------------------
----\
2 \
\ --------------------------
--------\
3->4 \
\-----------------------
----\
5->9 \
\ --------------------------
---------\
10->16 \
\ ---------------------
It seems there is a difference in ralling time of difference output , is
there any ?? or is it a scope problem.
Thanks in advance
Article: 54282Hi. I have a problem to make virtex2 DCM on external input clock. The rising edge of the input clock is stable. The duty cycle of the input clock (i.e the falling edge appearance) is changing. 1. Is there a constraing over the duty cycle of a clock that enter the DCM ? 2. One thing I can do is divide the input clock using a TFF, and then multiply it in the DCM and thus ignore the problematic falling edge. But then how can I compensate for the TFF clock to output delay ? ThankX, NAHUM.Article: 54283
Where can I get the price of fpga chips ? Xilinx: Spartan, Virtex-2 and Virtex-2Pro Altera: Stratix and EscaliburArticle: 54284
The best place is to look is the respective distributor Websites....where they have given prices for low quantities... For Xilinx you can check www.insight.memec.com or www.avnet.com "Nicolas Hervé" <nicolas.herve@enssat.fr> wrote in message news:3E917D5B.3020107@enssat.fr... > Where can I get the price of fpga chips ? > > Xilinx: Spartan, Virtex-2 and Virtex-2Pro > Altera: Stratix and Escalibur >Article: 54285
Allan, Thanks ! -rajeev-Article: 54287
In article <3e915c00$0$253$bc7fd3c@news.sonofon.dk>,
"Karl Olsen" <karl@micro-technic.com> writes:
|> The XC3S50 has the same number of LUTs+FFs as the XC2S50E but no BRAMs, so I
|> wonder how Xilinx can suggest, by the naming, that it is a "50,000 gate"
|> chip, since many of the "50,000 gates" in an XC2S50E are in the BRAMs. And
|> I wonder what a device with 1536 LUTs+FFs and no BRAMs and DCMs can be used
|> for...
Maybe as a cheap replacement for the "fade-to-grey" Spartans? There are still a
lot occasions where you don't need BRAM and 100k gates, but can't use CPLDs
because of distributed RAM etc. I'm currently trying to find a cheap replacement
for a XCS10XL for an older design...
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 54288
In article <3E917D5B.3020107@enssat.fr>,
=?ISO-8859-1?Q?Nicolas_Herv=E9?= <nicolas.herve@enssat.fr> writes:
|> Where can I get the price of fpga chips ?
|>
|> Xilinx: Spartan, Virtex-2 and Virtex-2Pro
|> Altera: Stratix and Escalibur
avnetmarshall.com has a nice search engine, although it seems to be "Temporarily
Unavailable" at the moment...
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 54289For the distibutors of Altera Device Families click on: http://www.altera.com/corporate/contact/sales/na_distis/con-na_distis.html The International Distributors, Domestic and International Reps, and Altera Office Addresses are available on the left of the page. The distributors in France are: EBV Elektronik 29 Avenue des Peupliers Rennes Cesson Sevigne F-35510 France Tel: +33 (0)2 99 83 00 50 Fax: +33 (0)2 99 83 00 60 EBV Elektronik 3 Rue de la Renaissance Paris Antony Cedex F-92184 France Tel: +33 (0)1 40 96 30 00 Fax: +33 (0)1 40 96 30 30 Arrow 21, rue du Jura - Silic 585 Rungis Cedex Rungis Cedex 94653 France Tel: 33 (0) 1 49 78 49 00 Fax: 33 (0) 1 45 60 96 85 Tekelec 17, rue du Jura - Silic 565 Rungis Cedex 94653 France Tel: 33 (0) 1 56 30 24 25 Fax: 33 (0) 1 56 30 25 52 EBV Elektronik Immeuble Hemiris, Bat. A, 115 Rue Nicolas Ledoux Aix-en-Provence Cedex 3 F-13854 France Tel: +33 (0)4 42 39 65 40 Fax: +33 (0)4 42 39 65 50 EBV Elektronik Parc Club du Moulin a Vent, 33 Avenue du Dr Georges Levy Lyon Venissieux Cedex F-69693 France Tel: +33 (0) 4 72 78 02 78 Fax: +33 (0)4 78 00 80 81 EBV Elektronik Immeuble Actys B2, Voie 3, BP348 Toulouse Labege Innopole cedex F-31313 France Tel: +33 (0)5 61 00 84 61 Fax: +33 (0)5 61 00 84 74 - Subroto Datta Altera Corp. "Nicolas Hervé" <nicolas.herve@enssat.fr> wrote in message news:3E917D5B.3020107@enssat.fr... > Where can I get the price of fpga chips ? > > Xilinx: Spartan, Virtex-2 and Virtex-2Pro > Altera: Stratix and Escalibur >Article: 54290
Hi Bill, The OCM is before the caches which in turn is before the PLB. The OCM grabs 16 MByte of address space and the address can be set by an attribute or changing a register though the DCR bus. There is both an instruction side OCM and a data side OCM. Göran Bilski bill wrote: > Hi, > I checked out the Xilinx V2P document and want to know its memory > achitechture. I am new to this, so when I read the OCM chapter, I am > totally confued here. > In the PPC405 diagram, I see OCM cntlr is a sub-module of cache > unit on I- and D- sides. Besides the OCM cntlr, that is PLB interface. > Then I am confused at how to differentiate an address processor issues > is an OCM address or a PLB address. I see some description on OCM > cntlr section that OCM cntlr only uses 14 bit of the 32 bit wide > address line, then does that mean there is a special bit to different > whether an address is OCM or PLB? > Maybe a silly question, totally lost here.Article: 54291
"Neeraj Varma" <neeraj@cg-coreel.com> wrote in message news:b6rva4$8dlcv$1@ID-159439.news.dfncis.de... > The best place is to look is the respective distributor Websites....where > they have given prices for low quantities... > > For Xilinx you can check www.insight.memec.com or www.avnet.com > I've never seen the price of any fpga chips on any distributor websiteArticle: 54292
Alex Gibson <alxx@ihug.com.au> wrote: : "Neeraj Varma" <neeraj@cg-coreel.com> wrote in message : news:b6rva4$8dlcv$1@ID-159439.news.dfncis.de... :> The best place is to look is the respective distributor Websites....where :> they have given prices for low quantities... :> :> For Xilinx you can check www.insight.memec.com or www.avnet.com :> : I've never seen the price of any fpga chips on any distributor website Look at e.g. www.nuhorizons.com Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54293
>I've never seen the price of any fpga chips on any distributor website Digikey's catalog has pricing info. I believe they carry only Xilinx chips. Roberto WaltmanArticle: 54294
Saw that link, but doesn't help. Anyway thanks! Egbert Molenkamp <molenkam_no_spam@cs.utwente.nl> wrote in message news:b6mp5f$msn$1@ares.cs.utwente.nl... > > "Kang Liat Chuan" <kanglc@starhub.net.sg> schreef in bericht > news:3e8e3d27$1@news.starhub.net.sg... > > Hi group, > > > > I inherited a design which was simulated using Viewsim commands (I believe > > it is Foundation 1.5/3.1?). I am converting the "testbench" into full > VHDL. > > At first, I tried to convert to Modelsim do file, but the force statement > is > > just too much. So I am guessing what those Viewsim commands like wfm, > smode, > > bc etc means! > > Viewsim commands are used in the Viewlogic tooling (powerview/Workview) > Maybe the following link helps: > http://www.informatik.tu-cottbus.de/~mwaldman/info/viewsim.html > > Egbert Molenkamp > >Article: 54295
Sounds frightening, how will you get the 409.6 onto the global clock routing resources?Article: 54296
I've gone to the support/documentation link under the "Additional Documentation" section for the "Interactive Data Sheets" and used the "Spartan-IIE Pin Compatability Tool" (http://xilinx.com/applications/web_ds_sp2e/pin_comp/) to generate a list of the Spartan-IIE pins. If you save the HTML page, Excel does a superb job of formatting the HTML into a useable table (once all the graphics junk is deleted). This HTML import into Excel has been helpful in my own pinout definitions. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3E9086DF.7B713CC@yahoo.com... > Leon Heller wrote: > > > > "Leon Heller" <leon_heller@hotmail.com> wrote in message > > news:b4huqe$ks4$1@venus.btinternet.com... > > > I've searched the Xilinx web site but can't seem to find the Excel > > > spreadsheets for the Spartan-IIE pinouts. I've previously downloaded them > > > for the Spartan-II, but can't remember where they came from, which would > > > help. > > > > Someone from Xilinx very kindly provided me with these. It looks like they > > are not available via the web site. If anyone else needs them, I can email > > it to them. > > Odd. I seem to recall that they used to make these available on the web > site, but maybe I am remembering an FAE posting here that they would > look into doing that. In any event, I would appreciate copies of the > files. > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54297
Ian Young wrote: > > rickman <spamgoeshere4@yahoo.com> wrote: > > >The Webpack does not have a chip editor. > > It does have a floorplanner, but I'm not sure how much to trust it in > this case. If you run a simple design through on the only 5.2i > WebPACK-supported Spartan-3 device (3S50) you can see a device with a > Virtex-2 style of CLB layout, but with an apparent complete lack of > DCMs, BRAMs and multipliers. It does seem to have about 3x the CLBs > of the 2V40, though, if I'm counting correctly. > > I'm not sure I believe that, but as long as we're in rampant > speculation mode... > > Obviously even if the above is true, it doesn't imply the whole family > will be like this; it may just be the teeniest one that's just "all > CLBs". I have not downloaded the current webpack since it is such a large download. At one time you could get Insight to send you a CD, but they don't even anwser their emails at this point. I am finding that when it comes to doing anything other than giving you a link to click, most vendors are becoming very lame when it comes to customer support. I would rant on, but I really am trying to get a little info on these parts... :) Just don't mention the name Sharp to me, ok? I will try to download Webpack tonight and let it crank for the 10 to 15 hours it will take over this modem link. In the meantime, is there any info in the floorplanner for the 3S200, or 3S400 device? Does the floorplanner show how many IO pins can be used? I need a part with about 230 or more IOs. The 2S150 will do the job well with 260 IOs in the FG456. I am looking for something like this. My supply voltages have changed, so I am going to take a new look at the Cyclone parts. But they seem to have the same power on surge as the 2S parts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54298
In article <3E91C32B.589B2AF8@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >I will try to download Webpack tonight and let it crank for the 10 to 15 >hours it will take over this modem link. Is there some net cafe, university, or kinkos where you could sneakernet it through? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54299
Eric Smith wrote: > > I'm thinking about using a Linear Technology LTC3406B synchronous buck > regulator for the 2.5V core Vdd for an XC2S150. Has anyone else used > this? It's rated for 600 mA, so it should be able to handle the 500 mA > required current at power-on (and my application will need less than > that when operating), but I'm concerned about whether the ramp will be > too fast, too slow, non-monotonic, or otherwise make the FPGA unhappy. > > It's not too expensive, and requires few external components. Since it > operates at 1.6 MHz, it can use a very small inductor. I would recommend the TI TPS54315PWP. This is a 3 Amp, 2.5 volt switcher in a TSSOP20 package <7mm sq. The fixed voltage versions only require three small passives other than the main components. They have been tested (don't remember if it was by Xilinx or TI) to meet the power on surge requirements of the Xilinx chips without dropping voltage. They did the test by running the supply into a bank of parallel diodes. So the current was at max once the voltage got up to .8 volts or so. I belive the part is about $4. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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