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Hello all, I have got the parallel cable III from Insight and the spartan 2 board (the one with the 2s100 and the lc-display). I have very often problems to initialize the jtag chain in iMPACT (I use ISE 4.2 sp3 and win2k sp2) in order to download the bitstream via jtag. Sometimes it works fine, sometimes it doesn't even recognize the correct devices in the chain. For example it recognizes 16 devices of "unknown" instead of my 2s100 and 18v01 isp eeprom. I have already tried a different computer, an other cable and a different development board but it didn't help. Sometimes it helps, when I "reroute" the parallel cable on my desktop. Perhaps it could help to slow down the jtag signals in iMPACT. How can this be done? Please help me - this problem is really ugly. Best regards MarkusArticle: 52426
Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote: > On 7 Feb 2003 03:42:28 -0800, serebr@mailandnews.com (Valeri > Serebrianski) wrote: >>Is this possible to store both the program and data tables solely in >>those caches without any use of Virtex-II Pro SelectRAM or external >>RAM? It assumes that initial content for both caches will be stored in >>main Virtex-II Pro configuration RAM and will be loaded at startup. > > No. You cannot initialise the caches from the bitstream used to > download the FPGA; they must be read from a memory outside the PPC > core :( Does that include a block RAM initialised by the bitstream though? From memory I think it does. Then you have your solution for the cost of a couple of block RAMs. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 52427
"Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message news:<3E431E87.905ECF6F@egr.msu.edu>... > Hi, > I am looking at design upgrade of an existing instrumentation > project. Currently the design talks over a high speed bus to a rather > expensive (~$1600 US) parrallel digital input board. The data rate > would be on the order of 50M bits per second not including any > overhead. I do not think I want to go to an all FPGA based solution. > Currently the FPGA in the system is the smallest Spartan2e series > device. By the way, quantities are very small, on the order of less > than 50 pieces per year. > > So here are my questions... > > 1. Does anyone happen to know what the USB2 or firewire is rated for > in terms of the longest cable length? I had thought USB2 was limited to > about 2 meters but I have seen USB cables about 5 meters long recently. > A longer length interconnect would appear to be desireable. I know that > ethernet is good for several hundred meters. That would be far beyond > my needs. > > 2. Has anyone had any experience with either USB2 or 100mB or > firewire as an interconnect to an FPGA based design? > > 3. Do you happen to have any recommendations as to a possible > off-the-shelf solution (either a small board or a 1 or two chip > solution, ideally something with a demo board available)? > > Thanks, > Theron Hicks Another alternate much simpler std is IEEE1355, this has its origins in the pt to pt links of the T9000 Transputer, but has moved on to industrial, space networking. This is also related to the SpaceWire std. It is low cost to impliment and starts at 100MBits. Boards/stuff available from 4links. This interface should easily fit in a Spartan since it is in order of 16550 uart. JJ Google IEEE1355, 4links, spacewireArticle: 52428
Markus Knauß <M.Knauss@web.de> wrote: > Sometimes it works fine, sometimes it doesn't even recognize the correct > devices in the chain. > For example it recognizes 16 devices of "unknown" instead of my 2s100 > and 18v01 isp eeprom. Make sure that the high speed JTAG wires (TDO, TDI, TCK) from the pod to the devices on the PCB are short in length. Short mean around 10cm to 15cm. In special if you dont use the original JTAG connector cable. WD --Article: 52429
Hi Walter, on the pcb's I used the JTAG wires are about 6 cm from the 2s100 to the JTAG connector. From the pod to the connector I use the original cable from Insight which is about another 6cm. I think th original equipment from Insight should work? Thank for the answer! > Make sure that the high speed JTAG wires (TDO, TDI, TCK) from the >pod to the devices on the PCB are short in length. Short mean around >10cm to 15cm. In special if you dont use the original JTAG connector cable. > >WD > >Article: 52430
Hi All,
Is there any published algorithmic approach to quickly estimate
the area and delay of RTL constructs (Verilog/VHDL, assuming
a target FPGA liby is given) such as if-then-else, case etc?
thanks,
regards,
Srini
Article: 52431Petter Gustad <newsmailcomp4@gustad.com> writes: > Chen Wei Tseng <chenwei.tseng@xilinx.com> writes: > > > Petter, > > > > If you have Win2K sp3, then please take a look at the link below. > > > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15380 > > Thanks a lot. I'll check it out. In my case I had a PC with SP3 at the > time when I installed ISE 4.2. The patch worked. I was able to boot my system after I installed ISE 4.2. I then installed ISE 4.2 SP3. Whenever I try to start any of the programs I get a message saying something like: The procedure entry point ?printMsg@Port_MsgManDefault@@UAXW4MsgType@Port_MsgMan@@PBGHPBD2H2@Z could not be located in the dynamic link library libPortability.dll Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52432
Ray Andraka <ray@andraka.com> writes: > 4.2 also has issues with win2K with big designs. We never really were able > to get a big design through 4.2 on the win2K box, wound up doing it on an > NT4 box instead. The official solution seems to be upgrade to 5.1. In our > case, there were even more issues with the design under 5.1, so we were > forced to use the slower NT box with 4.2. I have been using ISE 4.2SP3 under Solaris which works fine, except with some problems with the Java GUI's. However, our SUN's are getting a little old and I don't feel like spending $20,000 to get the performance of a $3,000 PC. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52433
As described in an earlier posting to the group I'm having a weird problem with the Quartus simulator (when it doesn't hang up) so I've looked at the ModelSim tool for the first time that ships with Quartus. I'm not really sure what it does that the Quartus simulator should do. What extra functionality does it have? Also do the input signals need to be defined using "force" commands or can it read .vwf files from Quartus or is there some other graphical way to achieve the same thing? I've not been able to run ModelSim from Quartus for some unknown reason. I would have thought that installing from the CDs would have performed all the configuration required to allow the two packages to run but it seems not. I get a couple of messages in Quartus that say the VHDL failed to compile (ModelSim) and something about vcom failing (is this the compiler again?). If anyone can shed any light on what's going on, I'd be grateful. Thanks. Rog.Article: 52434
"John_H" <johnhandwork@mail.com> wrote in message news:<AEU0a.16$As2.405@news-west.eli.net>... > You can sample an input at 1 bit (on or off) but produce a filtered result > that's accurate to 16 bits. No problem. It seemed the original post was > talking about decimation by a factor of 2. Decimation is a typical > application where the output resolution is greater than the input > resolution. > > It sometimes seems odd, trying to get more bits out than are put in, but > when you're trying to isolate a smaller portion of the spectrum you can end > up with "processing gain" that increases your fidelity. > > You can even take a 1 bit input from an RF stream and extract 16 bits worth > of audio with a software radio system. > > > "jetmarc" <jetmarc@hotmail.com> wrote in message > news:af3f5bb5.0302061419.3677f3cd@posting.google.com... > > > input data is 9 bit samples at 33.325714 MHz (or possibly 31.104 MHz) > > > 1 dB ripple allowed in pass band (0 - 7MHz), minimum of 65 dB down in > > > the stop band. (8 MHz) > > > > Last time I checked, 9 bits don't offer 65dB dynamics so the spec looks > > flawed. You can blame marketing for the 65dB of spec. We will be using 9 bit samples through the system and oversampling , filtering and decimating to try and prevent aliasing effects from appearing in the output. The feedback that I have received has been very useful in trying to refine the requirements for the filter and to determine what is achievable. I would like to thank everybody for their input. Garry AllenArticle: 52435
How big is big? I have been doing XC2V1000 designs with no trouble, using 4.2 & Win2K, but I may soon be doing larger ones. I'd like to know where I am likely to hit this? :Ray Andraka <ray@andraka.com> writes: : :> 4.2 also has issues with win2K with big designs. We never really were able :> to get a big design through 4.2 on the win2K box, wound up doing it on an :> NT4 box instead. The official solution seems to be upgrade to 5.1. In our :> case, there were even more issues with the design under 5.1, so we were :> forced to use the slower NT box with 4.2.Article: 52436
Hi, I'm looking for a table that lists the typical delays (or maximum clock frequencies) of often-used structures in FPGAs. It should look about like this: 8 to 1 MUX / Virtex-II (speed 5): XX ns 16 bit Adder / Spartan-II (speed 4): XX ns 24 bit Adder / Virtex-II (speed 4): XX ns 24 bit par. multiplier / VirtexE (speed 5): XX ns Of course, I could describe everything, synthesize it and look at the reports. But isn't there somebody who has done that before (Xilinx maybe?) The reason is that I am building a design, and I am not sure if I should use for example a parallel 24bit Adder or rather split this up into 2 clock cycles for speed reasons. I have not much experience, but it would be a lot of work to try every possible implementation by myself... is there such a table somewhere? Thanks! KevinArticle: 52437
The design that broke it was a pretty full XCV6000. The floorplan is in the
gallery on my website at http://www.andraka.com/sonar_processor.htm One of the
breaking items was the large RPM, seems they didn't expect anyone making big RPMs
in 5.1. The work around for the RPM is to do the top level placement as RLOC
origins instead of RLOCs. There were a number of other issue that came up, and
even a work-around that went out of the tool flow via xdl broke xdl.
David R Brooks wrote:
> How big is big? I have been doing XC2V1000 designs with no trouble,
> using 4.2 & Win2K, but I may soon be doing larger ones. I'd like to
> know where I am likely to hit this?
>
> :Ray Andraka <ray@andraka.com> writes:
> :
> :> 4.2 also has issues with win2K with big designs. We never really were able
> :> to get a big design through 4.2 on the win2K box, wound up doing it on an
> :> NT4 box instead. The official solution seems to be upgrade to 5.1. In our
> :> case, there were even more issues with the design under 5.1, so we were
> :> forced to use the slower NT box with 4.2.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52438Thanks to all who responded. So, I have to spend couple of Virtex-II Pro block RAMs to store initial program/data memory content. It will cost about 57% of available XC2VP4 Block RAM (32 KByte out from ~56 KByte total). Regards, Valeri Serebrianski.Article: 52439
Petter Gustad <newsmailcomp4@gustad.com> writes: > The patch worked. I was able to boot my system after I installed ISE > 4.2. I then installed ISE 4.2 SP3. Whenever I try to start any of the > programs I get a message saying something like: > > The procedure entry point > ?printMsg@Port_MsgManDefault@@UAXW4MsgType@Port_MsgMan@@PBGHPBD2H2@Z > could not be located in the dynamic link library libPortability.dll I repeated the install of ISE 4.2 and downloaded SP3 again. Then I installed on top of the old version (replying no to overwrite of windrvr) and my installation seem to work!? Could be that my previous version of ISE4.2-SP3 was corrupted somehow. BTW, what is windrvr? Is this where the device driver for the download cables reside? IIRC I got into the same endless boot loop when I selected no for both the parallel cable and the MultiLinx cable. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52440
I fix a similar problem with IJC-2 JTAG cable in the follow mode: In my board I've put a capacitor of 100pF nearest the TDO pin. Then I've open the JTAG interface and remove the capacitor labeled C1. In my opinion the R9-C1 filter is too big. Hope to be usefull Giuseppe "Markus Knauß" <M.Knauss@web.de> ha scritto nel messaggio news:b25el5$196dmk$1@ID-152093.news.dfncis.de... > Hello all, > > I have got the parallel cable III from Insight and the spartan 2 board > (the one with the 2s100 and the lc-display). > I have very often problems to initialize the jtag chain in iMPACT (I use > ISE 4.2 sp3 and win2k sp2) in order to > download the bitstream via jtag. > > Sometimes it works fine, sometimes it doesn't even recognize the correct > devices in the chain. > For example it recognizes 16 devices of "unknown" instead of my 2s100 > and 18v01 isp eeprom. > > I have already tried a different computer, an other cable and a > different development board but it didn't help. > Sometimes it helps, when I "reroute" the parallel cable on my desktop. > > Perhaps it could help to slow down the jtag signals in iMPACT. How can > this be done? > > Please help me - this problem is really ugly. > > Best regards > > Markus >Article: 52441
Hi, Can anyone tell me what is sysnthesis scripts? And why is it necessary? Thanks LijoArticle: 52442
On 9 Feb 2003 21:24:02 -0800, serebr@mailandnews.com (Valeri Serebrianski) wrote: >Thanks to all who responded. > >So, I have to spend couple of Virtex-II Pro block RAMs to store >initial program/data memory content. It will cost about 57% of available >XC2VP4 Block RAM (32 KByte out from ~56 KByte total). ... but once the program has been read from the block ram into the PPC cache, it may be possible to reuse the block ram for something else. Allan.Article: 52443
I've been searching around google and had not found a link to somewhere that described how to translate the polynomial from one architecture to another, not sure how I missed it. That link's just what I was looking for though. Thanks. Chris. "Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message news:lcub4vs3qagb47gdnn80hb88ekv1pkpg7u@4ax.com... > On Fri, 07 Feb 2003 18:37:00 GMT, Bob Perlman > <bobsrefusebin@hotmail.com> wrote: > > >Hi - > > > >On 7 Feb 2003 08:46:28 -0800, chris.p.ward@ntlworld.com (Chris Ward) > >wrote: > > > >>I am correct in thinking Galois and Fibonacci LFSRs are mathematically > >>equivalent? > >> > >>If I have a generator polynomial and I implement the two architectures > >>do I need to do anything different to obtain the same sequences from > >>the two? > >> > >>Thanks > >>Chris > > > >A Google search for "Fibonacci LFSR" returns the following link: > > > >http://www.newwaveinstruments.com/resources/articles/m_sequence_linear_feed back_shift_register_lfsr.htm > > > >There's a very nice explanation of Fibonacci and Galois LFSRs that > >seems to answer your question. > > The program that you can download from this page: > http://www.logiccell.com/~jean/LFSR/ > also shows the equivalence between the two forms of LFSR. > > Regards, > Allan.Article: 52444
Allan Herriman wrote: > Valeri Serebrianski wrote: > > >In Virtex-II Pro datasheet stated that PowerPC processor has 16 KByte > >of instruction and 16 KByte of data cache onboard. For my application > >that amount of memory is more than enough (processor speed is far more > >valuable). > >Is this possible to store both the program and data tables solely in > >those caches without any use of Virtex-II Pro SelectRAM or external > >RAM? It assumes that initial content for both caches will be stored in > >main Virtex-II Pro configuration RAM and will be loaded at startup. > > No. You cannot initialise the caches from the bitstream used to > download the FPGA; they must be read from a memory outside the PPC > core :( So would the cheapest solution be to us a tiny piece of logic to initialise from an external serial memory?Article: 52445
Hello everybody, I have nearly the same question but more subtil ... and I would very much appreciate your input. I get the following warnings: Design Doctor Warning: Flipflop or synchronous memory 'sa_q_help1' receives data that is synchronized by another Clock at flipflop or synchronous memory 'sa_q1' and the same for sa_q_help2, which receives data from sa_q1 and sa_q2, sa_q_help3, which receives data from sa_q1, sa_q2, and sa_q3 and so on ... Code structure: > lclk : input; --local clock > sa_q[18..0] : dffe; > sa_ena_help : DFF; > sa_d_help[18..0] : DFF; > sa_q_help[18..0] : DFF; > sa_q[].clk = global (lclk); > sa_q[].clrn = lresetn_q.q; > sa_q[].prn = vcc; > sa_q[].ena = sa_ena_help.q; > sa_q[].d = sa_d_help[].q; > sa_q_help[].clk= global (lclk); > sa_q_help[].clrn = lresetn_q.q; > sa_q_help[].prn = vcc; > sa_q_help[].d = sa_q[].q + 1; and what is strange: No warning when > sa_q_help[].d = sa_q[].q; Induces the increment a delay, such that the expression "sa_q[].q + 1" is no more synchronized with "sa_q[].q" ? I have the same construct with other counters without problem. Or is it the length of the counters which makes the difference? The other counters have up to 4 bits and this one has 19 bits. How can I solve the problem?? Thanks MaxArticle: 52446
Uwe Bonnes wrote: > > Tan Peng Khiang <tpkcbq@singnet.com.sg> wrote: > : Hello , i designed a VHDL program with XC2C256 coolrunner 2 and the > : timing analysis of Xilinx ISE5 says eg. Max internal clock frequency > : 44Mhz ,min period 22ns . > > : Therefore does this imply that i can use a oscillator as a clock input > : for a max of 44Mhz , anything exceeding that would cause the design to > : be unstable ? > > Yes. > > Look at the timing report and rethink the logic with the longest pathes. > > : BTW: any advice on double -edge clocking? > > Whats your question? Double -edge clocking with XC2C works as expected... > > Bye > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Thanks for the reply . I will look through me design again. ThanksArticle: 52447
Hello Sirs/friends I wanted to know the difference between latency timer, min_gnt register and max_lat_register in the configuration register. This all are with regard to master. what is the weightage of each bit in that register. please reply waiting for reply Thanks in advance praveenArticle: 52448
In article <ff5ada4a.0302060845.bb262bc@posting.google.com>,
ruthsims@hotmail.com says...
> Hi,
>
> After creating a symbol from a piece of vhdl in Quartus, in the block
> symbol editor, how can you move a port that appears on one side of the
> block symbol to the other side? I only seem to be able to move/drag
> the port vertically, it won't let me drag it around the edges of the
> block to the other side or top of the block?
The only way I've found is to delet the port then manually add
the port to the other side. One of the MANY things I hate
about Quartus.
--
gad
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
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= Greg Deuerling, Fermi National Accelerator Laboratory
=
= P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629, FAX (630)840-
5406 =
= Electronic Systems Engineering Group
=
= Work: egads@fnal.gov Personal: gad@elnet.com
=
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Article: 52449Does anyone know how to reliably disable the write protect bits on XC9500XL series CPLDs without using Xilinx's Impact software? The idea is that a microcontroller is supposed to reconfigure the CPLD with a design update, using its own JTAG routine. This works ok, except on devices where the read or write protect bits have been set (foolishly!). A method has been found to clear these protection bits so a bulk erase can be done, but unfortunately it is very unreliable. Has anyone else overcome this problem? Cheers, John.
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