Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Roger <rogerwilson@hotmail.com> wrote in message news:Qi22a.40$hu2.6@newsfep3-gui.server.ntli.net... > So basically the only way of graphically describing input waveforms for a > simulation is via the Quartus simulator?! > > Rog Yes, but it _really_ is worth while working out how to write a testbench around your design and using that for verification. This way you can write complex behavioural models which make testing final designs far easier. An example would be a dummy traffic generator feeding a design input, with a traffic checker looking at the output and counting errors, and a bus model reading a text file which tells it which regsiters to write to/read from to set the whole thing up. Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 52476
Hello first of all! For more than a week I try to get a valid license file for my NIOS upgrade. I filled out the form at least 50 times over the days. All the stuff they send to me was useless... At the moment even the Altera websever does not replay a simple ping. I realy think to stop the Altera platform. Are there more people around with simular problems? regards dirkArticle: 52477
Dirk Koch napisal(a): >At the moment even the Altera websever does not >replay a simple ping. I have just tried and their www works Ok. -- Pozdrowienia, Marcin E. Hamerla "Every day I make the world a little bit worse."Article: 52478
Well, there IS a hazard case in which it WILL go wrong: if one port is writing to an address, and the other port is reading from that same address at the same clock cycle (or shortly after), the reading port WILL read garbage. If you can guarantee that this never happens in your design, you have no problem :) I've designed a similar thing which is pipelined and you never know... Solutions: - this applies to Spartan-II. If you use Virtex-II instead, you can configure the RAM to "read first" mode. That way, you'll read the old data for one clock cycle, later the new data. Better than garbage :) But Spartan-II RAMs don't support that feature. - you could build a logic that catches this hazard case and multiplexes the output. I once did this. It works fine, but in your case, having a dummy location for dump writing would probably be faster and require less logic. Regards, DennisArticle: 52479
Steve Casselman <sc@vcc.com> wrote: > 161406 yes, that works :-) Thank you, AndyArticle: 52480
RISC taker <RISC_taker@alpenjodel.de> wrote in message news:18c289aa.0302110504.5bdce060@posting.google.com... > Well, > > there IS a hazard case in which it WILL go wrong: > > if one port is writing to an address, and the other port is reading > from that same address at the same clock cycle (or shortly after), the > reading port WILL read garbage. Does this apply if the writing port has 'stopped' previously and is continuously writing the same data to the address that's about to be read? Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 52481
Hi all,
I have a small piece of code that the XST synthesis tool in Xilinx ISE
5.1 Webpack chokes on:
signal W: std_logic_vector(n+1 downto 0); -- generic n=15
signal nz: std_logic;
...
cond: process(W) begin
nz <= '0';
for i in W'range loop
nz <= nz or W(i);
end loop;
end process cond;
FATAL_ERROR:Xst:Portability/export/Port_Main.h:126:1.13 - This
application has discovered an exceptional condition from which it
cannot recover.
Meanwhile, this version of it works:
nz <= W(16) or W(15) or W(14) or W(13)
or W(12) or W(11) or W(10) or W(9)
or W(8) or W(7) or W(6) or W(5)
or W(4) or W(3) or W(2) or W(1) or W(0);
Does anyone know why this happens?
--
Brad Eckert
Article: 52482Hi, Ken is correct in what he writes. In particular, the organisation of the memory is the important issue to analyze. I've designed a FFT that does not use any "RAM" at all - at least not in the classical way. The system required a pretty fast FFT (256 ns), which didn't allow the data to be written and read to and from a RAM in the given time. The system is described in the article at http://www.polar-design.de/dsp.html (sorry, no english version available today, only german - but the drawings should explain the concept). I would recommend to study the application you want to implement in some detail and maybe even try a couple of implementations to figure out which one best suits your requirements (I usually do it on paper, but that's just my way to work these things out ;-)). In the above mentioned FFT I had to analyze each stage of the FFT to see which strategy of building multipliers and storing the results fits best. It takes some time upfront, but this is easily paid for at the end, because you know exactly how to build your design. Good luck, Britta Fuhrmann Ken Chapman wrote: > Dear Alan, > > The main thing is to implement an FFT that just does what you require. I > know of one customer that implemented an FFT that had a transform time > of 10ns - Yes I mean that! The whole transform in 10ns is seriously fast > but it comes at a price as it requires a lot of silicon and a lot of > I/O! > > For most applications, the transform time doesn't need to be anywhere > near as fast as 10ns. So start with some simple calculations. 1024 > points requires 20480 multiplication's using a simple radix-2 > architecture. How fast do you want to clock your design? Let's just say > 100MHz for now and get some estimates... > > 1 multiplier = Transform time of 204.8us > 2 multipliers = Transform time of 102.4us > 4 multipliers = Transform time of 51.2us > 8 multipliers = Transform time of 25.6us > 16 multipliers = Transform time of 12.8us > 32 multipliers = Transform time of 6.4us > > If we look at the Virtex-II devices, then the XC2V40 (smallest) has 4 > multipliers and the XC2V1000 has 40 multipliers. > > But simply having more multipliers to do the 'work' doesn't solve the > problem. You have to organise the memory in such a way that you can feed > all those compute engines with data. At the same time you need to be > collecting the next set of samples. > > This type of study is covered in the DSP Techniques Course which I wrote > for Xilinx. Find out when it is running near you and I hope you find it > useful. Here's the pointer to the course description (note the section > at the end of day 3). > > http://support.xilinx.com/support/training/abstracts/v4/atp-dsp.htm > > You may find it useful to consider alternative approaches to transforms > such as the work by RF Engines. > > http://www.rfel.com/ > > Hope this is useful and you get the opportunity to attend the course. > > Yours sincerely, > > Ken ChapmanArticle: 52483
I look at being able to define inputs only through waveforms negatively. If you are trying to give inputs in the order of 1000's of numbers, it would be crazy to define that thru input waveforms (as in Quartus). Modelsim will allow you to be able to read from a txt file. That feature itself is just motivation enough to use Modelsim for pre-synthesis simulation. For bigger designs, Q2 will first synthesize the code (time consuming !!) and then run the simulations(time consuming). There is no time wasted in synthesis in Modelsim. This is what I do for my designs. 1. Write RTL and simulate in Modelsim. 2. Then, synthesize code in Q2 and use the Q2 simulator to check synthesized output. There is a way to use a .vec file to be able to write a txt file of numbers into input waveforms in Q2. Let me know if you need more information on that. Prashant "Roger" <rogerwilson@hotmail.com> wrote in message news:<Qi22a.40$hu2.6@newsfep3-gui.server.ntli.net>... > So basically the only way of graphically describing input waveforms for a > simulation is via the Quartus simulator?! > > Rog. > > "Roger" <rogerwilson@hotmail.com> wrote in message > news:VLJ1a.174$YF2.23664@newsfep1-win.server.ntli.net... > > As described in an earlier posting to the group I'm having a weird problem > > with the Quartus simulator (when it doesn't hang up) so I've looked at the > > ModelSim tool for the first time that ships with Quartus. I'm not really > > sure what it does that the Quartus simulator should do. What extra > > functionality does it have? Also do the input signals need to be defined > > using "force" commands or can it read .vwf files from Quartus or is there > > some other graphical way to achieve the same thing? > > > > I've not been able to run ModelSim from Quartus for some unknown reason. I > > would have thought that installing from the CDs would have performed all > the > > configuration required to allow the two packages to run but it seems not. > I > > get a couple of messages in Quartus that say the VHDL failed to compile > > (ModelSim) and something about vcom failing (is this the compiler again?). > > > > If anyone can shed any light on what's going on, I'd be grateful. > > > > Thanks. > > > > Rog. > > > >Article: 52484
This is what I was referring to. For verilog type folks, always @(posedge clk) // slower write performance due to .WE begin reg_data_placed[15:0] <= in_data; reg_addr_placed[7:0] <= in_addr; write_ctrl <= in_data_valid; // pipeline matching if( write_ctrl ) mem[reg_addr_placed] <= reg_data_placed; end always @(posedge clk) // faster write performance with "effective" write enable begin if( in_data_valid ) reg_data_placed[15:0] <= in_data; if( in_data_valid ) reg_addr_placed[7:0] <= in_addr; mem[reg_addr_placed] <= reg_data_placed; end No garbage location required. The concern I had was that the data bypass ciruitry might mess things up. From one port to the other, it probably doesn't care what the address on port A is when reading from port B as long as the clock to clock constraints are met. If the address "goes away" on the other port, as long as the the old address is on the old clock and the new address is on the new clock and the old data stays the same, the old data will be read. I don't know if this is guaranteed. A garbage location would eliminate the match of a read address to the last-written write address many cycles before but I can get better utilization if the bypass works. I certainly won't try to read data that's freshly changing on the write port but I'd continue to write at the same port over and over even when reading the last value written (e.g. an empty FIFO condition). I won't have an address match on the read and write when the value is first written, but I will afterwards and it's the behavior of the BlockRAM at this tail end I'm concerned about. "Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message news:3e48c33f$0$29909$fa0fcedb@lovejoy.zen.co.uk... > Ray Andraka <ray@andraka.com> wrote in message > news:3E486125.AC4E29E3@andraka.com... > > That works just fine as long as you don't mind overwriting the data at the > > current address with garbage. In FIFOs and other similar buffers this is > rarely > > a problem. In random access buffers, you might need valid data present at > all > > normal write locations at all times, in which case you will need to either > use > > the enable ( :-( ) or you'll have to substitute an address where it is > > acceptable to push the garbage. > > Ray, > > You could also push the enabling back one level to a set of registers > which would store the last valid address/data combination. > > > Nial. > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.uk > > > >Article: 52485
There are all sorts of reasons to do this. Just go and look up all the paper written about JBits. Most of it has to do with using the configuration infrastructure to change and update a small part of a devices configuration often at runtime. If you think about it there are a lot of resources that go into configuring these devices and it is a waste to only use that once. At one time Altera and Xilinx had the same market cap (number of shares times share price) and that changed the day EETimes ran the headline "Xilinx believes in reconfigurable computing and Altera thinks it is a red herring." It told investors and engineers that Xilinx believed in a future and Altera did not. JBits gives users a direct programming model, something that Altera does not have. In my opinion if Altera wants to capture the imagination of the top engineers in the world they should design a part starting with a bit level programming model that makes sense and then make that public. It would be great if there were a part that I could give a partial bitstream that would just program the lookup tables and not have to include any routing bits. We are coming into the age where 10's of thousands of programmers are going to start using FPGA's. Access to, and knowledge of, the bitstream will allow companies to be successful quicker and add value beyond what HDLs and standard programming models of today can offer. I think the biggest challenge that faces FPGA companies is not more gates or bigger ram or faster embedded processors those things all come with more transistors. But rather how to design a part that starts with a straight forward, well documented, bit level programming model that will allow programmer to write software that can manipulate the hardware during runtime. Steve "Eric Pearson" <epearson@lsil.com> wrote in message news:b28bov$6od$1@news.lsil.com... > Hi Pete... > > How does Jbits help one get better Altera designs? > > Eric Pearson > > > "Peter Sommerfeld" <petersommerfeld@hotmail.com> wrote in message > news:5c4d983.0302081113.48392c92@posting.google.com... > > Is there anything equivalent to JBits for Altera devices? I'm dearly > hoping so ... > >Article: 52486
Prashant <prashantj@usa.net> wrote in message news:ea62e09.0302110831.57287c8e@posting.google.com... > This is what I do for my designs. > > 1. Write RTL and simulate in Modelsim. > 2. Then, synthesize code in Q2 and use the Q2 simulator to check > synthesized output. You should be able to use the same testbench in Modelsim to test RTL and post P+R designs. The results should be identical. The post P+R simulations are an order of magnitude [or two] slower than the RTL so these are normally just done as a final check. Some would argue that if designs are properly synchronous and the static timing report is OK then post P+R simulation is not necessary. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 52487
sadik wrote:
> set design wronmove
> set filepath [pwd]
> proc compile {} {
> set status [cmp start true]
> if {$status == 1} {
> puts "compilation started"
> }
> while { [cmp is running] } {
> set x 0
> after 10 set x 1
> vwait x
> FlushEventQueue
> }
> }
> project open $filepath/$design
> project set_active_cmp $design
> compile
> project close
> Above script i fire from UNIX command prompt using quartus_cmd -f
> filename.tcl
> what is the exact problem??
The tcl "server" quartus_cmp won't start.
> cause this scripts i am running since more than 3 months without any problem
> suddenly it had problem started giving error of Can't start Server as I
> mentioned previous mail.
Something changed.
> For this script every time copy previous created database and changes
> only edf which will be different every time.
> Since this problem comes in script I tried to fire in GUI , then the
> same database works fine.
> As I wanted to fire at night so written this script.
> do u think this is script problem???
> do u think this is any database mismatch or wrong database created
> problem????
May be due to a unix patch:
http://www.altera.com/support/kdb/rd04022001_9694.html
Consider upgrading quartus.
-- Mike Treseler.
Article: 52488In article <KDU1a.1753$1P5.362@newsfep1-gui.server.ntli.net>, Andre Powell <andre.powell@ntlworld.com> writes > >There is a 'generic' format for commands called TCL (Tool Command Language, >pronounced Tickle) that aids the transfer of scripts from one tool to >another, AMBIT from Cadence uses it and I now believe Synopsis does also. >I'm not too sure if the >FPGA tools use TCL specifically but there will be similar commands in their >instruction set. > Is TCL part of the individual tools or is it a separate language? -- Andy BotterillArticle: 52489
Hi Andy, Tcl is from what I understand a separate language, it has a partner element called Tk which I think you create graphics with.Modelsim is Tcl compliant and from one of the recent seminars I went to allows you to create some fancy graphic front ends. You can down load a Tcl development package for free from http://aspn.activestate.com/ASPN/Downloads/ActiveTcl and get more information from http://www.tcl.tk/ I hope that helps André "Andy Botterill" <csm@plymouth2.demon.co.uk> wrote in message news:hScRUIALkTS+EwlM@plymouth2.demon.co.uk... > In article <KDU1a.1753$1P5.362@newsfep1-gui.server.ntli.net>, Andre > Powell <andre.powell@ntlworld.com> writes > > > > >There is a 'generic' format for commands called TCL (Tool Command Language, > >pronounced Tickle) that aids the transfer of scripts from one tool to > >another, AMBIT from Cadence uses it and I now believe Synopsis does also. > >I'm not too sure if the > >FPGA tools use TCL specifically but there will be similar commands in their > >instruction set. > > > > Is TCL part of the individual tools or is it a separate language? > -- > Andy BotterillArticle: 52490
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<b29o11$u7k$1@agate.berkeley.edu>... > In article <adb3971c.0302101830.2a79a036@posting.google.com>, > john jakson <johnjakson@yahoo.com> wrote: > >Certainly a single cycle change would have given a large power spike > >that might have been difficult to cope with. If I were paying for (or > >even designing in) this feature I could live with a few clock cycles > >to bank change say 16 clocks to serially rewrite each LUT. Such a LUT > >serial swap out would also be alot easier on the Si area budget than > >par swap. > > The Xilinx one was killed not because of the power cost of A context > switch, but that it was designed to context switch every cycle. As > such, it would overheat a plastic package. So what if it was designed to context switch every cycle & burn off the packaging! Why would anyone ever do that? If used in the manner that RC folks would want changing HW every N us or less often, the extra power would be nada. The more likely reason is the demand isn't there yet for any type of volume RC use and other features were more pressing.Article: 52491
In article <adb3971c.0302111201.735c1bc5@posting.google.com>, john jakson <johnjakson@yahoo.com> wrote: >So what if it was designed to context switch every cycle & burn off >the packaging! Why would anyone ever do that? Because if the multicontext structure is to automatically virtualize arbitrary circuits intended for larger FPGAs, you need to context switch several times for each "virtual" design clock. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52492
In article <Iuc2a.5108$GX6.245@newsfep1-gui.server.ntli.net>, Andre Powell <andre.powell@ntlworld.com> writes >Hi Andy, >Tcl is from what I understand a separate language, it has a partner element >called Tk which I think you create graphics I am thinking about doing mixed-signal test automation. It would be simplest for me to use perl. But if it could be interfaced into EDA tools to make a better tool I may use Tcl/tk. >with.Modelsim is Tcl compliant and from one of the recent seminars I went to >allows you to create some fancy graphic >front ends. >You can down load a Tcl development package for free from > >http://aspn.activestate.com/ASPN/Downloads/ActiveTcl I'll have a go. > >and get more information from http://www.tcl.tk/ > >I hope that helps Thanks > >André > >"Andy Botterill" <csm@plymouth2.demon.co.uk> wrote in message >news:hScRUIALkTS+EwlM@plymouth2.demon.co.uk... >> In article <KDU1a.1753$1P5.362@newsfep1-gui.server.ntli.net>, Andre >> Powell <andre.powell@ntlworld.com> writes >> >> > >> >There is a 'generic' format for commands called TCL (Tool Command >Language, >> >pronounced Tickle) that aids the transfer of scripts from one tool to >> >another, AMBIT from Cadence uses it and I now believe Synopsis does also. >> >I'm not too sure if the >> >FPGA tools use TCL specifically but there will be similar commands in >their >> >instruction set. >> > >> >> Is TCL part of the individual tools or is it a separate language? >> -- >> Andy Botterill > > -- Andy BotterillArticle: 52493
Andy Botterill <csm@plymouth2.demon.co.uk> writes: > Is TCL part of the individual tools or is it a separate language? I would say both. Tcl is a separate shell (tclsh and wish which also contain tk for graphics). It's very easy to incorporate the Tcl command line interpreter into your own programs. I've included Tcl in a shell used to write Tcl scripts which call C routines (liked into the shell) which again call the device driver which interacts with my ASIC. Tcl is a pretty bad programming language, but it's a great scripting language (IMHO). Writing your own command line interpreter is a waste of time when you can use Tcl, Guile etc. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52494
Steve,
You are scaring me! I've had to clean up after too many of these
software-cum-hardware types to be complacent about it. The fact of the matter
is that there are issues that hardware designers deal with as a matter of course
(timing analysis, power considerations, asynchronous interfaces and the like)
that are foreign to software. Some of these, such as behavior of a circuit with
asynchronous inputs are insidious and may allow systems to be shipped with
inherent design flaws. I've yet to see any tool that will keep an unwary user
from unknowingly tripping over them. Frankly, I don't want to be on an airplane
with control hardware designed by a software engineer.
Are you planning to attend FPGA2003 at the end of this month? I'd love to
debate this over a beer with you.
Steve Casselman wrote:
>
>
> We are coming into the age where 10's of thousands of programmers are going
> to start using FPGA's.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52495...they envisionsed multicontext being used to virtualize larger circuits. Solving this "Big Hairy Problem" will change the architectural landscape of the reconfigurable technology platform. RC - try www.algotronix.com link for some background and history on the technology; they held (sold) the first patent in the field I believe. Alex MartinArticle: 52496
Hi all, I work with the Spartan II and I need a small RAM (16x8). Due to the fact that one LUT provides a 16x1 synchronous RAM I only need 8 LUTs (2 CLBs) for the 16x8 RAM. By using this distributed LUT RAM I have all on-chip Block RAMs unused and that's what I want. But now my question: "Do other FPGAs, e.g. Altera, also provide this kind of LUT based RAM or is this feature Xilinx specific? Next I also need a ROM and as before I would like to implement it as a distributed ROM instead of using a Block RAM. During synthesis (ISE Webpack) XST detects the Rom but during optimization the ROM is replaced by Logic (MUXs). This depends on which values I define within the ROM. How can I turn off the optimisation for a single component in my VHDL code? Has somebody experience with Dual Port RAMs? I heard that concurrent reading and writing from/to the same address is problematic (not for simulation but for implementation)? Thx -Norbert -- Norbert Hermann Pramstaller, Bakk.techn. Information and Communications Technology (ICT) Graz University of Technology Cell +43 664 1528612 Cell +39 340 9833726Article: 52497
Briefly, nz needs to be a variable, not a signal. Use a variable in the FOR loop, then copy it to a signal to export from the process. brad@tinyboot.com (Brad Eckert) wrote: :Hi all, : :I have a small piece of code that the XST synthesis tool in Xilinx ISE :5.1 Webpack chokes on: : :signal W: std_logic_vector(n+1 downto 0); -- generic n=15 :signal nz: std_logic; :... : cond: process(W) begin : nz <= '0'; : for i in W'range loop : nz <= nz or W(i); : end loop; : end process cond; : :FATAL_ERROR:Xst:Portability/export/Port_Main.h:126:1.13 - This :application has discovered an exceptional condition from which it :cannot recover. : :Meanwhile, this version of it works: : : nz <= W(16) or W(15) or W(14) or W(13) : or W(12) or W(11) or W(10) or W(9) : or W(8) or W(7) or W(6) or W(5) : or W(4) or W(3) or W(2) or W(1) or W(0); : :Does anyone know why this happens?Article: 52498
Hello, can we estimate the area/speed effect on an FIR implementation when the input wordlength is increased say by one bit either for parallel or serial arithmetic for a multiplier, we can assume that if a coefficient wordlength is N, when increasing the multiplicand wordlength by 1, we need to allocate roughly one LUT for each partial product. therefore we can deduce that the area increase in the multiplier implementation is is N+log2(N).... is that true Regards -- Ce message a ete poste via la plateforme Web club-Internet.fr This message has been posted by the Web platform club-Internet.fr http://forums.club-internet.fr/Article: 52499
Andy Botterill <csm@plymouth2.demon.co.uk> wrote in message news:<hScRUIALkTS+EwlM@plymouth2.demon.co.uk>... > > Is TCL part of the individual tools or is it a separate language? Hi Andy, I am maintaining Web project called TCL for EDA (www.TCLforEDA.net) Here you can find free TCL-based applications, scripts and methodological articles & presentations. Regards, Alexander
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z