Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi everyone, How can I read back the configuration of a Virtex-II device (SelectMAP interface)? Writing a configuration into the FPGA (XC2V1500) works fine, but I don't know the command sequence to start readback. In XAPP138, p. 26, I find that information for the Virtex XCV devices, but not for Virtex-II. I assume the write to FAR and CMD are the same as for Virtex, but what is the frame word count for an XC2V1500? Thank you for reading, AndyArticle: 52376
Harris, There is a Xilinx program called DATA2BRAM that allows you to change the block RAM initialization in the bitstream. It was designed for updating the object code of embedded processors without having to rerun place and route, but can be used for any block RAM. http://toolbox.xilinx.com/docsan/xilinx5/data/docs/dev/dev0184_27.html Steve Alphaboran wrote: > Hello all, > > I generate a blockram by using the Xilinx core generator. I edited a coe > file for the memory initalization values and works fine, if I want to change > the values of the blockram can I change the values directly in the edf file > or I must generate the core again but with other coe file? > > Thanks in advance. > > Best Regards, > HarrisArticle: 52377
Does anyone out there have the latest drivers for their Wildcard (The CardBus one with a V300)? I can't seem to find them on their website or anywhere else on the web. Thanks AArticle: 52378
The article stated that the incoming clock is assumed to have 50% duty cycle. Also, your frequency is fairly high, and you may see the effect of certain propagation delays. I doubt that you have exactly 33%. To analyze this, try running at a much lower frequency... Peter Alfke llaa57 wrote: > I implemented the circuit described in the application note "Unusual > clock dividers" written by Peter Alfke: > http://www.xilinx.com/xcell/xl33/xl33_30.pdf. > I used a Xilinx XC9536 and the input clock is generated by an > oscillator (SCO-061S 48MHz) by Sunny. > My problem is that the output clock's duty cycle is 33% and not 50% as > expected. Why? Is the CPLD unsuitable for this circuit? > > Many thanks in advance.Article: 52379
The Xilinx Web site Support section will return a list of over four thousand document references if you search on "fanout reduction"!! There are dozens of applicable techniques there, both for retaining duplicate logic nets and reducing fanouts... "Jim Raynor" <chris_cheung66@hotmail.com> wrote in message news:6YC0a.122087$Ui4.4092324@news1.telusplanet.net... > hi, > > does anyone know how to tell the synthesis tool not to remove the > duplicate logic? I am using Xilinx Foundation and synthesis tool is > XST....the target device is Virtex-E.. > > Also I have a very high fanout signal in my design...does anyone have > any suggestion to deal with the high fanout signal? I can't have that route > to ibufg because the PCB is already done...The phyiscal pin location of that > signal make it impossible to route to ibufg... so please advise.. > > Thanks > > Chris > >Article: 52380
John,
We are just piping data from a remote device to a PC. I am trying to
get rid of a proprietary board in the PC. The board is expensive ($1600
US) and requires a full length PCI slot. Perhaps that will clarify my wish
list? The data rate is about 51.2 Megabits per second so I have _some_
wiggle room as far as overhead.
Thanks,
Theron
John_H wrote:
> Are you looking at just a direct point-to-point connection between your
> proprietary hardware? If you use USB2 or Ethernet, there's overhead
> involved that you don't need if all you're doing is piping data.
>
> "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message
> news:3E431E87.905ECF6F@egr.msu.edu...
> > Hi,
> > I am looking at design upgrade of an existing instrumentation
> > project.
>
> [snip]
Article: 52381Hello all, first of all I like to thank you for your answers! I installed the 5.1 version of ISE (the sp3 also) and I noticed that the ucf is case sensitive (..a really bad idea this one). Do I have to change my constraints to lower case or there is another solution? Greetings, Harris "Patrick Mullarky" <pat@nwce.com> wrote in message news:3e42b055$1@news.microsoft.com... > The usefulness of the incremental design feature, in my opinion, is quite > subjective. I usually prefer complete reroutes for most designs. Others like > the feature. It does have a bit of a steep learning curve. > > One really good reason to upgrade to ISE 5.1: > > Xilinx's synthesizer in ISE 5.1, XST, does a surprisingly excellent job at > synthesis...and it comes included in the standard ISE package. It replaces > the FPGA Express synthesizer. > > For the Xilinx parts I work with, XST seems to synthesize pretty much as > well as Synplicity's basic Synplify...and even basic Simplify costs a LOT ! > > I have run both synthesizers side-by-side for quite a while, and the > differences in gate synthesis, speed, and area are minimal...at least in my > current 1400 slice Spartan IIE design. > > "Alphaboran" <alphaboran@yahoo-no-spam.com> wrote in message > news:b1rahs$1fa7$1@ulysses.noc.ntua.gr... > > Hello all, > > > > I just received the new version of the Xilinx Foundation tool. I now use > the > > 4.1 sp3 for my implementations, in the synthesis phase I use FPGA Express > > 3.6.1. My target devices are Virtex-EM. > > > > Are there any good reasons to upgrade my system? Does the new tool offer > > something really new and useful? > > > > I heard that with the new version you can keep the place AND routing of an > > implemented design and use it on later on altered design. If that's true > it > > seems very nice because with the 4.1 version even I make minor changes the > > only thing I can do is to keep the placement and not the routing. Is this > > the case or a rumor? > > > > Thanks in advance for your help. > > > > Best Regards, > > Harris > > > > > > > >Article: 52382
Hi - On 7 Feb 2003 08:46:28 -0800, chris.p.ward@ntlworld.com (Chris Ward) wrote: >I am correct in thinking Galois and Fibonacci LFSRs are mathematically >equivalent? > >If I have a generator polynomial and I implement the two architectures >do I need to do anything different to obtain the same sequences from >the two? > >Thanks >Chris A Google search for "Fibonacci LFSR" returns the following link: http://www.newwaveinstruments.com/resources/articles/m_sequence_linear_feedback_shift_register_lfsr.htm There's a very nice explanation of Fibonacci and Galois LFSRs that seems to answer your question. I'm continually amazed at how useful Google is. Bob Perlman Cambrian Design WorksArticle: 52383
no suggestions, but I have the same problem with it hanging during simulation and compilation......quite often at the very end when it seems to have got to 100% finished.Article: 52384
So generally speaking -- Synplify is good if you're looking for QOR, Leonardo Spectrum for better VHDL support, right? Is there anything at all that you feel FC2 is good at (compared to the others, I mean)?? - Nick "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> wrote in message news:<b1t8of$50p$1$8302bc10@news.demon.co.uk>... > "Ray Andraka" <ray@andraka.com> wrote: > > Synplify does a much better job at mapping RTL to the special features of > > the FPGA. Xilinx's XST does well in that regard too, but it is restricted > > to Xilinx only. > > I don't in any way disagree, but to try to keep the discussion > balanced it might be worth mentioning my experience that Leonardo > Spectrum seems to have the widest understanding of VHDL language > constructs of any synthesis tool. Not necessarily the best quality > of results, though - that's a "your mileage may vary" issue that > you will need to evaluate case-by-case. > > Also, don't try to evaluate these tools just by throwing one > standard piece of "benchmark" code at them to see which gives > the densest/fastest/prettiest result. Each of the major tools > has specific HDL coding styles that it doesn't like and won't > optimise effectively; details differ for each tool. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 52385
161406 Steve "Andreas Schweizer" <aschweiz@iiic.ethz.ch> wrote in message news:3e43e4fc@core.inf.ethz.ch... > Hi everyone, > > How can I read back the configuration of a Virtex-II > device (SelectMAP interface)? > > Writing a configuration into the FPGA (XC2V1500) works > fine, but I don't know the command sequence to start > readback. In XAPP138, p. 26, I find that information for > the Virtex XCV devices, but not for Virtex-II. > > I assume the write to FAR and CMD are the same as for > Virtex, but what is the frame word count for an > XC2V1500? > > Thank you for reading, > Andy >Article: 52386
Steve Lass <lass@xilinx.com> writes:
> Harris,
>
> There is a Xilinx program called DATA2BRAM that allows you to change
> the block RAM initialization in the bitstream. It was designed for updating
> the object code of embedded processors without having to rerun place and
> route, but can be used for any block RAM.
Another possibility is to use jbits. Its a ten-liner in java to modify
the BRAM, and if the value are somehow calculated, you can easily do
this in java too (So you can put the calculation of the values and the
modification of the bitstream into one programm).
Florian
--
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
Article: 52387nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > The CS150 class at Berkeley uses 100 Mb ethernet to communicate to an > FPGA board as part of the student projects. They used a simplified > RTP over Ethernet implementation. Are they using a 100Mb MAC core in the FPGA? If so, are they using a freely available core?Article: 52388
You can sample an input at 1 bit (on or off) but produce a filtered result that's accurate to 16 bits. No problem. It seemed the original post was talking about decimation by a factor of 2. Decimation is a typical application where the output resolution is greater than the input resolution. It sometimes seems odd, trying to get more bits out than are put in, but when you're trying to isolate a smaller portion of the spectrum you can end up with "processing gain" that increases your fidelity. You can even take a 1 bit input from an RF stream and extract 16 bits worth of audio with a software radio system. "jetmarc" <jetmarc@hotmail.com> wrote in message news:af3f5bb5.0302061419.3677f3cd@posting.google.com... > > input data is 9 bit samples at 33.325714 MHz (or possibly 31.104 MHz) > > 1 dB ripple allowed in pass band (0 - 7MHz), minimum of 65 dB down in > > the stop band. (8 MHz) > > Last time I checked, 9 bits don't offer 65dB dynamics so the spec looks > flawed.Article: 52389
See http://www.altera.com/products/ip/altera/m-ham-fft.html for lots of specs on Altera's FFT megafunctions. > Hi > > Can anyone give me an estimate of the size of > a 1024 pt FFT and the maximum frequency that > it can run ? > > Will it fit on a 200K logic element fpga which does not > have any onboard multipliers ? > > Is their any good rules of thumb for estimating the size of > these FFTs ? > > Thanks > AlanArticle: 52390
I knew format will be screwed up. Well Here's the verilog code for the circuit.
I hope it works !!!
module cen(din, clk, ce, dout);
input din, clk, ce;
output dout;
reg dout; reg ce_reg;
wire clk_ce;
assign clk_ce = ce_reg ? clk : 1'bz;
always @(posedge clk)
begin
ce_reg <= ce;
end
always @(posedge clk_ce)
begin
dout <= din;
end
endmodule
-Jay
jabayja@yahoo.com (Jay) wrote in message news:<f3f2b20d.0302061933.2b4608d5@posting.google.com>...
> Wow its becoming intresting.
>
> Well How about the following circuit ? I hope my format wont get
> screwed up.
> If you can find a flop with zero c2o or match it with the delay of CLK
> signal to tri-buf (very easy I guess), then I think we can produce
> TRUE CLOCK ENABLE circuit (may be) :-) and we can say CE is
> Synchronous.
>
> _________
> | |
> CE -----| |-------
> | | |
> CLK ____________| | |
> | --------- |
> | |\|
> | | \
> |___________________| \______
> | / |
> | / |
> |/ |
> | _________
> | D ---| | | | |----- Q
> ------- | |
> | |
> ---------
>
>
> - Jay
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3E42C36A.3375B035@andraka.com>...
> > Not entirely true. The synchronous set/reset in Virtex is not affected by the
> > clock enable, yet it happens as a result of the clock edge. I know...I am
> > splitting hairs now. For an edge triggered flip-flop, which is how they are
> > generally used in FPGAs, 'clock' infers 'clockedge'
> >
Article: 52391I've tried a couple times to install Xilinx ISE 4.2i on a fresh Windows 2000 installation and it causes the PC to restart on next reboot when connecting to the network. If I don't install ISE 4.2i the PC is working fine. I used it for a couple weeks and then I tried to install ISE 4.2i again and the machine just went into an endless boot loop... Have anybody else experienced this problem? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52392
On 7 Feb 2003 11:01:27 -0800, hereisjunk@yahoo.com (Nicholas Girde) wrote: >So generally speaking -- Synplify is good if you're looking for QOR, I absolutely did NOT intend to say that, and I must take the blame if it sounded as if I did. We've seen each of those tools out- performing the other on QOR, depending on precisely what you ask them to do. And as I hope I pointed out, there are still some significant sensitivities to coding style in both tools. As the tools get more and more sophisticated, so those sensitivities become more and more subtle and hard to pin down with a simple example :-( The problem this leaves for "real" users, of course, is how to decide. It's not even any good throwing your own reference design at an eval copy of the tool, because after living with the tool for a few months you will learn how to care for and feed it effectively - so as I tried to say, simple benchmark comparisons are not really very helpful. >Is there anything at >all that you feel FC2 is good at (compared to the others, I mean)?? I haven't used it for ages, so I can't really comment. Sorry I can't be more specific! -- Jonathan BromleyArticle: 52393
Petter, If you have Win2K sp3, then please take a look at the link below. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15380 Regards, Wei Petter Gustad wrote: > I've tried a couple times to install Xilinx ISE 4.2i on a fresh > Windows 2000 installation and it causes the PC to restart on next > reboot when connecting to the network. > > If I don't install ISE 4.2i the PC is working fine. I used it for a > couple weeks and then I tried to install ISE 4.2i again and the > machine just went into an endless boot loop... > > Have anybody else experienced this problem? > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52394
You could try synthesising the www.opencores.org fft core "gallenm" <gallenm@ic24.net> wrote in message news:v47lvmt36uj1ef@corp.supernews.com... > Hi > > Can anyone give me an estimate of the size of > a 1024 pt FFT and the maximum frequency that > it can run ? > > Will it fit on a 200K logic element fpga which does not > have any onboard multipliers ? > > Is their any good rules of thumb for estimating the size of > these FFTs ? > > Thanks > Alan > > >Article: 52395
"Paul Baxter" wrote > You could try synthesising the www.opencores.org fft core >From their site (may not be exactly up-to-date or even appropriate): sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144 registers (about 47%) of the deviceArticle: 52396
Chen Wei Tseng <chenwei.tseng@xilinx.com> writes: > Petter, > > If you have Win2K sp3, then please take a look at the link below. > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15380 Thanks a lot. I'll check it out. In my case I had a PC with SP3 at the time when I installed ISE 4.2. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52397
How fast do you need it? That will determine how many passes
it does through the data, how much parallelism, etc. One of
the limiting factors is the amount of memory available on the
chip. We have a paper design for a 1024 point design based on
a radix 4 kernel that fits in an XC2V40, but it requires 5
passes through the data and the speed in 'stepping 0' devices
is limited to the speed of the multipliers, about 130 MHz.
Should be good for about 200 MHz in a stepping 1 device. We've
also got 8 and 16 point kernels that will run at 250 MHz in
VirtexE-8 parts, and those are relatively small (20x25 CLBs for
the 16 point by 16 bit). You'll only get one radix16 kernel
plus a phase rotator into one 200K part. Getting into larger
parts, you have more leeway. We did a 4k block floating point
FFT in a Virtex XCV1000 at 100 MHz (this is in the slowest
speed grade of the original part), which does a 4K complex FFT
in 68 uS. If migrated to a VirtexE-8 1M gate part, that speed
could be nearly quadrupled because it can be clocked faster and
there is much more memory available.
The size comes down to the efficiency of the core (there is a
lot of variation there), the amount of parallelism, clock rate
and so on. So the question is how fast do you want it to go,
and how much are you willing to pay for it in terms of device
size and quality of design?
gallenm wrote:
> Hi
>
> Can anyone give me an estimate of the size of
> a 1024 pt FFT and the maximum frequency that
> it can run ?
>
> Will it fit on a 200K logic element fpga which does not
> have any onboard multipliers ?
>
> Is their any good rules of thumb for estimating the size of
> these FFTs ?
>
> Thanks
> Alan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 52398
A missing parameter is how long it takes to execute the FFT. One could do a
bit serial radix 2 butterfly in an XC2S15 with room to spare plus an external
memory and run it at better than 150 MHz, but it would take quite a while
(more than 1ms) to do a 1K FFT.
Paul Baxter wrote:
> "Paul Baxter" wrote
> > You could try synthesising the www.opencores.org fft core
>
> From their site (may not be exactly up-to-date or even appropriate):
> sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a
> Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144
> registers (about 47%) of the device
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52399
4.2 also has issues with win2K with big designs. We never really were able
to get a big design through 4.2 on the win2K box, wound up doing it on an
NT4 box instead. The official solution seems to be upgrade to 5.1. In our
case, there were even more issues with the design under 5.1, so we were
forced to use the slower NT box with 4.2.
Petter Gustad wrote:
> I've tried a couple times to install Xilinx ISE 4.2i on a fresh
> Windows 2000 installation and it causes the PC to restart on next
> reboot when connecting to the network.
>
> If I don't install ISE 4.2i the PC is working fine. I used it for a
> couple weeks and then I tried to install ISE 4.2i again and the
> machine just went into an endless boot loop...
>
> Have anybody else experienced this problem?
>
> Petter
> --
> ________________________________________________________________________
> Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z