Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
In article <78435b72.0302262149.2d4eb317@posting.google.com>,
rita_conaty@yahoo.com (Rita_Conaty) wrote:
| I have seen a lot of press on picoChip.
|
| They certainly seem to have some impressive claims (30 GigaMACs,
| easier to program, as fast as FPGA but with the programming model of
| DSP etc) but is it real ?
On their web site they say they are sampling their first chip (PC101).
| How usable is it ?
| Is it realistic to get this performance ? Do 30giga-MACs mean
| anything ?
| Do these picoArray devices actually exist, or is it hype ?
| What are the strings ?
| Is this the fasdtest DSP ?
I can't answer the other questions, but as far as 16-bit GMACS goes,
Intrinsity's FastMATH is slightly faster at 32 GMACS or 64 GOPS at 2
GHz. Of course, "fastest" really depends upon what your application is
and how it fits the various architectures.
The architectures and programming models of the PicoChip and the
FastMATH are quite different -- the PicoChip is a heterogeneous array of
430 16-bit processors (specialized for different applications) running
at 160MHz, while the FastMATH is a more traditional scalar/vector
processor (32-bit MIPS core with a 4x4 32/16-bit SIMD matrix unit),
running at 2GHz.
-- Tim Olson
Intrinsity, Inc.
--
-- Tim Olson
Article: 52976
"Peter Alfke" <peter@xilinx.com> wrote in message
news:3E5CFEA9.196783C3@xilinx.com...
>
>
> Stamatis Sotiropoulos wrote:
> >
> > Hi all,
> > I am designing a PCB based on a Xilinx SpartanII FPGA (XC2S100 -
TQFP144
> > package) and on an AVR Microcontroller. A clock of 8 Mhz will be used.
In
> > this frequency are high frequency bypass capacitors necessary?
> >
> As has been mentioned here many times:
> Decoupling capacitors are needed to support the short rise and fall
> times inside and outside the chip. The clock frequency has almost
> nothing to do with that. So, yes, you need good decoupling even at 8 MHz
> ( or even at 100 kHz clock rate).
>
> Peter Alfke
Peter,
I am sure you are right about using proper bypass capacitors. The
question I have is exactly what is recommended. I have a Spartan2E design
working using two 0.1 uF capacitors on each bank. One is on the internal
1.8 volt supply and one is on the external supply (3.3 volt in this case).
The capacitors are Y5V dielectric parts in a 0603 case. I have the same
design working in both a 4 layer and a 6 layer board. The six layer board
has a good bit of very low noise analog stuff on it. I found that puting a
10uf 6v tantalum in parallel with each 0.1uf substantially reduced the
digital feedthrough into the analog stuff. I know that this is gross
overkill in terms of the bulk capacitors but it did make a substantial noise
improvement. The real question is "Are the Y5V parts suitable?" or should I
get a better capacitor for the 0.1uF part?
Thanks,
Theron
Article: 52977Hi. Several questions. 1. What Altera fpga family is an alternative to Spartan-IIE family ? 2. I want to design an interface to Micron's RLDRAM device - that is I/O bandwidth of 640 Mbps (HSTL). what fpga can I use ? 3. Next generation of Micron's RLDRAM device will have a bandwidth of 800 Mbps (HSTL). Do I have an fpga today that will be able to support this bandwidth ? Bye, NAHUMArticle: 52978
I think both should be used schematic design and HDL programming and by combining blocks of both in a big schematic will make the job easier. use the divide and conquer principle divide ur problem to small blocks and decide for each block wether to be a cct. diagram or a code. best regards proskiArticle: 52979
"Rita_Conaty" <rita_conaty@yahoo.com> wrote > Is it really as fasdt as an FPGA ? I sent the following to the fpga-cpu list some months back: [http://groups.yahoo.com/group/fpga-cpu/message/1411] (((6 GMAC/s => 12 Gops))) "The high end FPGA CPU is only ~150 MHz. But you can multiply instantiate them. I have an unfinished 16-bit design in 4x8 V-II CLBs that does about 167 MHz and includes a pipelined single-cycle multiply-accumulate. You can put 40 of them in a 2V1000 for a peak 16-bit computation rate (never to exceed) of 333 Mops * 40 = ~12 Gops. In a monster 2VP100 or 2VP125 you're looking at up to 10X that -- over 50 Gmacs (100 Gops). (Whether your problem can exploit that degree of parallelism, or whether the part can handle the power dissipation of such a design, I just don't know.)" The above design is not and will not be for sale. But it (V-II-based parallel processor (chip or multi-chip mesh of same) consisting of tens/hundreds of 4x8 V-II-CLB 167 MHz pipelined 16-bit soft RISC+MAC tiles) seems perfectly feasible. So where cost is no object, big FPGAs can hold their own in the 50 GMAC/s C-programmable parallel processor space. I believe putting an austere 16-bit soft RISC in front of each of the tens/hundreds of multiplier+BRAM blocks can be an effective way to map many signal processing algorithms onto an FPGA fabric. And where memory bandwidth or inter-node (inter-chip) interconnect is of concern, modern FPGAs can also hold their own, with fast DDR-DRAM interfacing and with a rich variety of high speed serial and parallel link options. No doubt we will eventually see commercial FPGA-based massively parallel processor designs following in these footsteps. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 52980
Jerry wrote: > Has anyone ran place and routes for a FPGA design > under linux and then under windows on teh same machine? I was wondering just > what > kind of performance gain there is under one OS vs the other. I have not attempted to get an exact measure, which is rather hard to do anyway. Assuming the Xilinx tools under Wine, I have found the performance to be roughly equal, assuming that Wine is configured to use a Windows native version of msvcrt.dll. -- My real email is akamail.com@dclark (or something like that).Article: 52981
Theron, We recommend X7R or next best is X5R ceramics (last is Y5V - but read on). One per power/ground pin pair for Vcco's and Vccints. This is if you want to use the device at its maximum SSO guidelines, and at its max toggle rate/junction temperature/frequency. If you back off of the SSO's you may use less bypassing. If you back off of the core usage, you may get away with less core bypassing. All of our simulations, models, jitter predictions, app notes, applications and demo boards follow these rules which assume the peak to peak ground bounce/vcc bounce is never worse than 200 mV. As we go to even lower voltages for Vccint in the future, this may have to be even more stringent, requiring special laminate pcbs, special caps, etc. We try to avoid this as best we can, and have suceeded to date. Y5V is fine, but you have to carefully watch the ambient temperature, and also be sure the ESR and self inductance is comparable with the X7R, or at least taken into account. Remember that twice the self inductance doubles the noise! The avx website has lots of good graphing utilities to compare capacitors and types. Some bulk tantalums are good, as well as other values -- see xapp623 for all of the details of proper bypassing. Even though this is written for Virtex II and II Pro, it applies to Spartan IIE, and Virtex E as a best practice to follow. Austin Theron Hicks wrote: > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3E5CFEA9.196783C3@xilinx.com... > > > > > > Stamatis Sotiropoulos wrote: > > > > > > Hi all, > > > I am designing a PCB based on a Xilinx SpartanII FPGA (XC2S100 - > TQFP144 > > > package) and on an AVR Microcontroller. A clock of 8 Mhz will be used. > In > > > this frequency are high frequency bypass capacitors necessary? > > > > > As has been mentioned here many times: > > Decoupling capacitors are needed to support the short rise and fall > > times inside and outside the chip. The clock frequency has almost > > nothing to do with that. So, yes, you need good decoupling even at 8 MHz > > ( or even at 100 kHz clock rate). > > > > Peter Alfke > > Peter, > I am sure you are right about using proper bypass capacitors. The > question I have is exactly what is recommended. I have a Spartan2E design > working using two 0.1 uF capacitors on each bank. One is on the internal > 1.8 volt supply and one is on the external supply (3.3 volt in this case). > The capacitors are Y5V dielectric parts in a 0603 case. I have the same > design working in both a 4 layer and a 6 layer board. The six layer board > has a good bit of very low noise analog stuff on it. I found that puting a > 10uf 6v tantalum in parallel with each 0.1uf substantially reduced the > digital feedthrough into the analog stuff. I know that this is gross > overkill in terms of the bulk capacitors but it did make a substantial noise > improvement. The real question is "Are the Y5V parts suitable?" or should I > get a better capacitor for the 0.1uF part? > > Thanks, > TheronArticle: 52982
Nahum, Go the the supplier websites, download their IBIS models, and simulate the IOs you wnat to use at the frequencies you desire. This will answer your questions. Austin Nahum Barnea wrote: > Hi. > Several questions. > > 1. What Altera fpga family is an alternative to Spartan-IIE family ? > 2. I want to design an interface to Micron's RLDRAM device - that is > I/O bandwidth of 640 Mbps (HSTL). what fpga can I use ? > 3. Next generation of Micron's RLDRAM device will have a bandwidth of > 800 Mbps (HSTL). Do I have an fpga today that will be able to support > this bandwidth ? > > Bye, > NAHUMArticle: 52983
hmurray@suespammers.org (Hal Murray) wrote in message news:<v5rigbpb625186@corp.supernews.com>... > >I have just bought an FPGA development board and it must be attached to = > >the PC's PCI slot. As it is attached inside the PC, so it's hard to tap = > >the jumper or FPGA pin and moreover it is not flexible. I am willing to = > >extend this PCI slot to outside of the PC, using cables and so on. > Check http://www.adexelec.com. I used their cable version with great success. I think each signal is interleaved with a ground to allow for better signal integrity.Article: 52984
Thanks, I ran it on Win2000 too, and here is the error message that I am getting from win2000. I should the say one of the messages. Can't locate File/DummyUtils.pm/ in @INC (@INC contains: C:\Xilinx/bin/nt/perllib .) at C:\MicroBlaze\\bin\libgen.pl line33 ... I guess I can hack it if I have too, but pretty ugly and big undertaking without knowing if the thing is going to work or not on my systems. Do you know if MDK works with win98/ME? - without doing all that hacking? many thanks, -Junyi jling@cs.tamu.edu "John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:b3jvmu$vfl$1@bunyip.cc.uq.edu.au... > Gaga wrote: > > > > In cygwin, this is the newest error message on the list: > > "C:\MicroBlaze\bin\gnu\cpp0.exe: *** Couldn't reserve space for cygwin heap > > (0x2420000) in child, cygheap, Win32 error 487" > > Let me guess, you're running WinXP? The version of Cygwin that Xilinx > used for MDK was released before Cygwin ran under WinXP. So, strictly > speaking, it's a legacy Cygwin problem (fixed in newer versions of Cygwin). > > > Do any of you wise sages out there have had any previous experiences with > > and solutions to these problems? Whom we should contact? What patch to > > apply...? Please help! Thanks. > > You have several choices: > > (1) Lobby Xilinx for an upgrade to EDK, install it and patch up to SP3, > then it will run under WinXp. Note however that the EDK requires ISE > 5.1, which you may not have. > > (2) Hack it. Grab the latest version of Cygwin from www.cygwin.com, > install into c:/cygwin or wherever, then use a binary editor to modify > all of Xilinx's tools replacing references of "xygwin1.dll" to > "cygwin1.dll". Finally, put the MDK tool directories (but not the > /xygwin dir) into the Cygwin path, and off you go (doing all your work > under Cygwin, not Xygwin). Ugly, but it works. > > I've actually got a combination of both - I'm using EDK with SP3, and > have hacked it to work under regular Cygwin instead of the Xygwin shell. > Makes life a lot easier. > > Rgds, > > John >Article: 52985
Joze Dedic <joze.dedic@fe.uni-lj.si> wrote in message b3dfgt$a6i$1@planja.arnes.si... > Hi! > > In order to connect several parts of design I use some form of internal bus > with many sources and many sinks. > Should I pay any attention to keep bus values defined all the time (i.e. > occasions when bus is not driven by any device exists)? > Hi Joze, In one of my design I experienced some problems when the control signals of a Block RAM (Clk, We) where not driven by any source (i.e. their value was 'Z'). I'm not sure that the problem arose from this, but when I implemented the control bus with muxes instead of tri-states all worked fine... Bye Dr. JonesArticle: 52986
> The real question is "Are the Y5V parts suitable?" or should I > get a better capacitor for the 0.1uF part? I would like to know that, too. I had a look at some Kemet datasheets, and the Y5V seem to have the widest bandwidth. (Well, here are some capacitors with a better bendwidth: http://www.dilabs.com/Products/DCBlocks/DCBlocks.html) Is there anybody who has some knowledge about what dielectric to choose? Kolja SulimmaArticle: 52988
Austin,
My impression is that the actual capacitance value and the
self-resonant frequency are the most critical factors between X7R, X5R,
and Y5V. In my case the temperature range is primarily ambient so the
temperature coeficient is not a big issue. The AVX site shows the Y5v
as having a self-resonant frequency of about 5 MHz vs. 20 MHz for the
X7R series. However, my part is from Murata. They show both the X7R
and the Y5V as having almost the same frequency vs. impedance
characteristic. I assume the Frequency vs. Impedance plot shows the
range of frequencies at which the capacitor is appropriate for by-pass.
I was always taught that the Y5V is _not_ the capacitor of choice for
bypass. However, unless they have somehow used the wrong plot for
Frequency vs. impedance for the Y5V part, it looks like the only issue
is temperature coefficient (which is not an issue for room temperature
applications, correct?). By the way, both of Murata's plots
approximately match the X7R plot from AVX. Have I missed something
obvious (or not so obvious)? Ultimately, my design works (at least for
now.) I just hope that I have not designed any gremlins into the unit.
Thanks,
Theron
Austin Lesea wrote:
> Theron,
>
> We recommend X7R or next best is X5R ceramics (last is Y5V - but read
> on). One per power/ground pin pair for Vcco's and Vccints. This is
> if you want to use the device at its maximum SSO guidelines, and at
> its max toggle rate/junction temperature/frequency.
>
> If you back off of the SSO's you may use less bypassing.
>
> If you back off of the core usage, you may get away with less core
> bypassing.
>
> All of our simulations, models, jitter predictions, app notes,
> applications and demo boards follow these rules which assume the peak
> to peak ground bounce/vcc bounce is never worse than 200 mV.
>
> As we go to even lower voltages for Vccint in the future, this may
> have to be even more stringent, requiring special laminate pcbs,
> special caps, etc. We try to avoid this as best we can, and have
> suceeded to date.
>
> Y5V is fine, but you have to carefully watch the ambient temperature,
> and also be sure the ESR and self inductance is comparable with the
> X7R, or at least taken into account.
>
> Remember that twice the self inductance doubles the noise!
>
> The avx website has lots of good graphing utilities to compare
> capacitors and types.
>
> Some bulk tantalums are good, as well as other values -- see xapp623
> for all of the details of proper bypassing. Even though this is
> written for Virtex II and II Pro, it applies to Spartan IIE, and
> Virtex E as a best practice to follow.
>
> Austin
>
> Theron Hicks wrote:
>
>> "Peter Alfke" <peter@xilinx.com> wrote in message
>> news:3E5CFEA9.196783C3@xilinx.com...
>> >
>> >
>> > Stamatis Sotiropoulos wrote:
>> > >
>> > > Hi all,
>> > > I am designing a PCB based on a Xilinx SpartanII FPGA
>> (XC2S100 -
>> TQFP144
>> > > package) and on an AVR Microcontroller. A clock of 8 Mhz will be
>> used.
>> In
>> > > this frequency are high frequency bypass capacitors necessary?
>> > >
>> > As has been mentioned here many times:
>> > Decoupling capacitors are needed to support the short rise and
>> fall
>> > times inside and outside the chip. The clock frequency has almost
>> > nothing to do with that. So, yes, you need good decoupling even at
>> 8 MHz
>> > ( or even at 100 kHz clock rate).
>> >
>> > Peter Alfke
>>
>> Peter,
>> I am sure you are right about using proper bypass capacitors.
>> The
>> question I have is exactly what is recommended. I have a Spartan2E
>> design
>> working using two 0.1 uF capacitors on each bank. One is on the
>> internal
>> 1.8 volt supply and one is on the external supply (3.3 volt in this
>> case).
>> The capacitors are Y5V dielectric parts in a 0603 case. I have the
>> same
>> design working in both a 4 layer and a 6 layer board. The six layer
>> board
>> has a good bit of very low noise analog stuff on it. I found that
>> puting a
>> 10uf 6v tantalum in parallel with each 0.1uf substantially reduced
>> the
>> digital feedthrough into the analog stuff. I know that this is
>> gross
>> overkill in terms of the bulk capacitors but it did make a
>> substantial noise
>> improvement. The real question is "Are the Y5V parts suitable?" or
>> should I
>> get a better capacitor for the 0.1uF part?
>>
>> Thanks,
>> Theron
>
Article: 52989To the nay-sayers out there, I humbly offer the following link of similarly enlightened "expert" views. http://www.airbornelaser.com/special/abl/fun/ This posting is my personal opinion may not represent the views of my employer. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division E-mail: steve.knapp@xilinx.com --------------------------------- jsmith wrote: > > I see some new spartan family on my latest Synplicity tools. I hear > that its on 90nm IBM. Why would anyone try and build a low cost FPGA > family on an aggressive new process technology? They can't make 0.13um > VII pro, what hope do they have in building 90nm any time soon.Article: 52990
nahum_barnea@yahoo.com (Nahum Barnea) wrote in message news:<fc23bdfc.0302270727.918478c@posting.google.com>... > Hi. > Several questions. > > 1. What Altera fpga family is an alternative to Spartan-IIE family ? This sounds just far enough away from homework that I'll answer it. The way the questions are posed though, that was the first thing that crossed my mind. It is difficult to compare across vendors because of the unique features of each. Spartan-IIE is a cost optimized Virtex-E, so everywhere you see me mention Virtex-E, it should also apply to Spartan-IIE. My personal opinion is that the Virtex-E falls between the Apex 20KE and the Apex II families, although that depends on your exact needs and the exact design. The Apex 20KE has different I/O support than the Virtex-E. Unfortunately Altera doesn't have a low cost version of those, although they offer hardwire for higher volume cost reduction. Also, last time I checked, the Apex 20KE was priced VERY competitively - so for all I know, now-a-days it might be compariable in price to the Spartan-IIE. > 2. I want to design an interface to Micron's RLDRAM device - that is > I/O bandwidth of 640 Mbps (HSTL). what fpga can I use ? I don't know about the HSTL part of it, but for high speed LVDS I/O: Xilinx: Virtex-II and above (add Virtex-E if you lower the frequency slightly) Altera: Apex 20KE and above > 3. Next generation of Micron's RLDRAM device will have a bandwidth of > 800 Mbps (HSTL). Do I have an fpga today that will be able to support > this bandwidth ? Same answer as #2, except the Virtex-E. MarcArticle: 52991
> Implement design -> Properities -> Basic -> Macrocell Power Setting > > (Low seems to be default). Thanks Uwe, I didn't realise you could right click on the processes to get those opitons. RalphArticle: 52992
Theron, If the self resonant frequency is high, then the ESR at self resonance tends to be at its lowest point. If that coincides with where the switching frequency is, then that is good. The point of xapp623 is to design a network of caps to provide a given low impedance network (say less than 0.1 ohms from KHz to GHz). Obtaining that requires that you simulate the various capacitors, with their self inductance, and the series inductance of the connections, to the power and ground planes. Suprisingly, it is hard to do much better than a bunch of 0.1uF to 0.047uF caps all in parallel, unless you are just unfortunate enough to hit a self resonant point where the noise gets large. This usually is only a problem where peopel have far too much inductnace in series with the caps, or use caps with intrinsic high self inductance. http://www.avxcorp.com/SpiApps/spicap/spicapgraph.asp If you look at a 0.1 uF cap, 0603, 10V X7R, you will note its impedance is smallest at ~17 MHz. Its self inductance is 0.9nH. I can't find the Murata details, how does this compare? Austin Theron Hicks wrote: > Austin, > My impression is that the actual capacitance value and the > self-resonant frequency are the most critical factors between X7R, > X5R, and Y5V. In my case the temperature range is primarily ambient > so the temperature coeficient is not a big issue. The AVX site shows > the Y5v as having a self-resonant frequency of about 5 MHz vs. 20 MHz > for the X7R series. However, my part is from Murata. They show both > the X7R and the Y5V as having almost the same frequency vs. impedance > characteristic. I assume the Frequency vs. Impedance plot shows the > range of frequencies at which the capacitor is appropriate for > by-pass. I was always taught that the Y5V is _not_ the capacitor of > choice for bypass. However, unless they have somehow used the wrong > plot for Frequency vs. impedance for the Y5V part, it looks like the > only issue is temperature coefficient (which is not an issue for room > temperature applications, correct?). By the way, both of Murata's > plots approximately match the X7R plot from AVX. Have I missed > something obvious (or not so obvious)? Ultimately, my design works > (at least for now.) I just hope that I have not designed any gremlins > into the unit. > Thanks, > Theron > > Austin Lesea wrote: > >> Theron, >> >> We recommend X7R or next best is X5R ceramics (last is Y5V - but >> read on). One per power/ground pin pair for Vcco's and Vccints. >> This is if you want to use the device at its maximum SSO guidelines, >> and at its max toggle rate/junction temperature/frequency. >> >> If you back off of the SSO's you may use less bypassing. >> >> If you back off of the core usage, you may get away with less core >> bypassing. >> >> All of our simulations, models, jitter predictions, app notes, >> applications and demo boards follow these rules which assume the >> peak to peak ground bounce/vcc bounce is never worse than 200 mV. >> >> As we go to even lower voltages for Vccint in the future, this may >> have to be even more stringent, requiring special laminate pcbs, >> special caps, etc. We try to avoid this as best we can, and have >> suceeded to date. >> >> Y5V is fine, but you have to carefully watch the ambient >> temperature, and also be sure the ESR and self inductance is >> comparable with the X7R, or at least taken into account. >> >> Remember that twice the self inductance doubles the noise! >> >> The avx website has lots of good graphing utilities to compare >> capacitors and types. >> >> Some bulk tantalums are good, as well as other values -- see xapp623 >> for all of the details of proper bypassing. Even though this is >> written for Virtex II and II Pro, it applies to Spartan IIE, and >> Virtex E as a best practice to follow. >> >> Austin >> >> Theron Hicks wrote: >> >> > "Peter Alfke" <peter@xilinx.com> wrote in message >> > news:3E5CFEA9.196783C3@xilinx.com... >> > > >> > > >> > > Stamatis Sotiropoulos wrote: >> > > > >> > > > Hi all, >> > > > I am designing a PCB based on a Xilinx SpartanII FPGA >> > (XC2S100 - >> > TQFP144 >> > > > package) and on an AVR Microcontroller. A clock of 8 Mhz will >> > be used. >> > In >> > > > this frequency are high frequency bypass capacitors necessary? >> > > > >> > > As has been mentioned here many times: >> > > Decoupling capacitors are needed to support the short rise and >> > fall >> > > times inside and outside the chip. The clock frequency has almost >> > >> > > nothing to do with that. So, yes, you need good decoupling even >> > at 8 MHz >> > > ( or even at 100 kHz clock rate). >> > > >> > > Peter Alfke >> > >> > Peter, >> > I am sure you are right about using proper bypass capacitors. >> > The >> > question I have is exactly what is recommended. I have a Spartan2E >> > design >> > working using two 0.1 uF capacitors on each bank. One is on the >> > internal >> > 1.8 volt supply and one is on the external supply (3.3 volt in this >> > case). >> > The capacitors are Y5V dielectric parts in a 0603 case. I have the >> > same >> > design working in both a 4 layer and a 6 layer board. The six >> > layer board >> > has a good bit of very low noise analog stuff on it. I found that >> > puting a >> > 10uf 6v tantalum in parallel with each 0.1uf substantially reduced >> > the >> > digital feedthrough into the analog stuff. I know that this is >> > gross >> > overkill in terms of the bulk capacitors but it did make a >> > substantial noise >> > improvement. The real question is "Are the Y5V parts suitable?" or >> > should I >> > get a better capacitor for the 0.1uF part? >> > >> > Thanks, >> > Theron >>Article: 52993
Jeff Cunningham wrote: > If I recall correctly, MT has said the ratio of performances of the > different versions is something like this: > > ModelSim SE = 3 x ModelSim PE > ModelSim PE = 5 x ModelSim XE > > Which, interestingly is proportional to the price. > > ModelSim XE starter has a 500 statement "soft" limit. > ModelSim XE has a 5000 statement limit. The limit of MXE was increased to 40,000 statements about a year ago. Steve > > > JCArticle: 52995
Johan,
The altsyncram megafunction assumes the following defaults
when it reads the mif files.
1. For ROM, Single Port and True Dual (Bidir Dual) Ports, the
MIF File is read based on A port parameters.
2. For Simple Dual Port, the MIF File should be read based on B
port parameters..
This default can be overridden by specifying INIT_FILE_LAYOUT ="PORT_A" or
"PORT_B". The Megawizard doesnt have any
option to set this value. So the user, if he wants to change it, has to
manually edit the instantiation of altsyncram to add this parameter.
Hope this helps.
- Subroto Datta
Altera Corp.
"Johan Ditmar" <johanditmar@hotmail.com> wrote in message
news:f43ed6f6.0302250943.7eb02446@posting.google.com...
> Hi guys,
>
> I have a question about initializing multi-ported memories for Altera
> using a MIF file. The MIF file starts with the DEPTH and the WIDTH of
> the memory, but what should these be if I have a RAM with different
> sized ports? Can I just take the depth and width of any port (with
> corresponding initialization values) or are there rules for this?
>
> Any help appreciated,
>
> Regards,
>
> Johan
Article: 52996Gaga wrote: > I ran it on Win2000 too, and here is the error message that I am getting > from win2000. I should the say one of the messages. > > Can't locate File/DummyUtils.pm/ in @INC (@INC contains: > C:\Xilinx/bin/nt/perllib > .) at C:\MicroBlaze\\bin\libgen.pl line33 > ... Yeah I seem to remember that one. Find the dummyutils script, and add that directory to the path. It went away with the new EDK. You need to think for yourself, google for the perl manuals to find out how to add things to the path, all of that. Be careful, you might learn something! :) > I guess I can hack it if I have too, but pretty ugly and big undertaking > without knowing if the thing is going to work or not on my systems. Do you > know if MDK works with win98/ME? - without doing all that hacking? many > thanks I'm not sure, I've only ever tried it on WinXP. Look at it this way - you said you're a grad student. You've got a couple of years ahead of you on this. The amount of time you'll spend "hacking" to get it working is likely to be a tiny fraction of the time you actually spend using the tool. It took about 3 days to get the old MDK working under WinXP, having never used cygwin before. When I moved up to EDK, it took about 2 days to completely expunge the Xygwin stuff and go "pure" Cygwin. I'm not Einstein, it's just not that difficult. It was 2 days' research and fiddling to find out how, then about 10 minutes in the binary editor to make the changes. Also check, but I doubt MDK is supported any longer by Xilinx. I don't think you could expect a very sympathetic response to bug reports on out-of-date tools. MDK was the "first cut", and as such is not going to be as polished as later efforts. Largely because of this, designs done under MDK require reasonable effort to ramp up to the EDK. Regards, JohnArticle: 52997
Hello Folks, I have an input clock on APEX20KE200E device which needs to be brought out as output. After synthesis with synplify and P&R on Quartus 2, I get a pin to pin delay of 4.245 ns on this o/p clock. How can I reduce this delay ? I already have another input-output clock pair and that uses the PLL to take the clock to the pin. So I cannot use the PLL for the clock in question (APEX20K200E allow only one PLL clock output to be driven out). Anyway, even if that would not have been the case, I still wouldn't be able to use the PLL since this fpga requires a reserved pin for the clock input source and I don't have that criteria satisfied. I already have the FPGA on board. oops! what now ? hirenArticle: 52998
Yes, I seem to be jumping thru hoops to get a sysem configured off the shelf with Linux and windows in a dual boot mode. I'm about ready to drop the linux part of the system till later. Thanks for the reply J "Duane Clark" <junkmail@junkmail.com> wrote in message news:b3lb4b1tmo@enews4.newsguy.com... > Jerry wrote: > > Has anyone ran place and routes for a FPGA design > > under linux and then under windows on teh same machine? I was wondering just > > what > > kind of performance gain there is under one OS vs the other. > > I have not attempted to get an exact measure, which is rather hard to do > anyway. Assuming the Xilinx tools under Wine, I have found the > performance to be roughly equal, assuming that Wine is configured to use > a Windows native version of msvcrt.dll. > > -- > My real email is akamail.com@dclark (or something like that). >Article: 52999
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z