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Martin wrote: > Also I'm looking for an operation system for the hardcore PPC 405 in > the virtex 2 pro. > Is there an open source projekt which have ported linux for the PPC > for the virtex 2 pro? Hi Martin, Does the PPC in V2pro have an MMU (I think it does?)? If so, you should be able to get standard PPC linux up and running pretty quickly. This won't be like installing linux on a PC from a red hat distro, but it's feasible to get something up and running reasonably quickly. You'll have to do all the hardware interfacing stuff (interrupts, MMU setup etc etc). At least the deep kernel source should work unchanged. If it does not have an MMU, then you'll need to look into uClinux (www.uclinux.org). There is no PPC_nommu branch in the uclinux source, so you'd have to do the port yourself. Not trivial, but a great learning exercise. I'm busy porting uClinux to the microblaze - I've just about got a complete kernel image ready to bring into the debugger! The two books you simply *must* have for this project are "Understanding the Linux Kernel" by Bovet & Cesati, and "Linux Device Drivers" by Rubini & Corbet, both published by O'Reilly. The 2nd one is available freely as PDFs from somewhere on O'Reailly's website. Regards, JohnArticle: 52851
John Larkin <jjlarkin@highsniplandthistechpleasenology.com> wrote: : Hi, : I'm considering the design of a PCI card that will use a fairly big : (400 I/Os, maybe) Xilinx FPGA and a bunch of SRAM to hold images (2D : histograms, actually). There would be a bunch of control registers in : the FPGA, and PCI block transfers to/from the dual-ported image RAM. : The thing is, I'd like to have the PC application code be able to : configure the FPGA for various applications. So the FPGA would likely : not be the actual PCI interface, and would power up un-configured. : So, any suggestions on an architecture? Some possibilities I've : thought of are... : A standard PCI chip, like the AMCC or PLX parts, do the real PCI : interface, with some sort of path (maybe a little glue logic) for : initializing and configuring the FPGA. : A second, fix-configured FPGA or CPLD to front-end the big one, ditto. : Partial reconfiguration somehow? Like initial config from a EEPOM, : with self-managed reconfig afterwards? Sounds nasty. : Ideas welcome. And if anybody has this all worked out already, we'd : consider buying the IP. The Insight Spartan II PCI board has a lot of IO ( also not 400) and the PCI can be implementd with the OpenCore core. Programming can be done through the JTAg Port. The board is not expensive, at least cheaper then a 4 layer prototype board with gold finger you need for PCI. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52852
Scott <scottiecs@yahoo.com> wrote: : I am new to FPGA's and its programming language VHDL. I am working on : an electrical engineering senior project and have a few questions. : 1.) is it possible to connect a USB device (ie a digital camera) to : the Spartan 2e FPGA? 2.) If it is possible, could someone give a : quick overview or a good resource for me to research. 3.) If not, any : good suggestions on how i would go about accomplishing my : objective(see below) : My main goal is to connect a Digital camera directly to the FPGA board : to get a picture from the camera. Once the picture is loaded into the : FPGA memory i am going to compress that image and then send it to a : computer. Have a look at the Opbecore USB core. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52853
I believe LVDS is high speed serial, but most LCD's get data in parallell. Normally, you want some bits of Red, Green and Blue plus some sync signals for hsync, vsync, rows and frames. And a pixel clock I presume. Then you probably would need a driver chip to clock out data from video memory to show on your screen. Your driver needs to initialize this chip with the correct settings for your LCD (vsync/hsync/bit per pixel etc.) and be given access to the video memory. My experience is that a passive LCD's is easier to interface than TFT displays. Your processor should not undertake the task of driving the LCD lines directly since you then probably will not have enough processor time to do your *real* stuff (depending on your processor speed of course). You may look at opencores.org for their free FPGA implementation of an LCD "chip". Several embedded processors like the SA1110 (StrongARM) have a built in LCD controller, and if you use the ARM port of Linux (i.e. Familiar Linux) for the SA1110, the kernel provide a driver for the internal LCD chip. You (or your program/XWindow/Qt-Embedded) just write your stuff to the framebuffer (/dev/fb0) and then your screen is delivered to the LCD. Of course, you must wire it up correctly, but with a little studying it is actually not that hard. If someone have used the opencores.org FPGA LCD implementation, I would be glad to know. Even so, if someone know how to wire a Wishbone to Avalon bus (if possible?), a would be grateful. Martin "mat" <mats_trash@hotmail.com> skrev i melding news:43525ce3.0302241251.7ba030b0@posting.google.com... > Sorry if this is the incorrect group > > As a project I've got a motherboard with an LVDS connector, which I > understand can be used to control an LCD screen. Can I simply > purchase an LCD screen (small <10") and connect it to this socket and > it work? Drivers? Alternatively can someone point me to introductory > material on how to connect LCDs and which also explains the necessary > components such as the different controller boards. So far I have > been bewildered by the lack of introductory material and the > impenetrable information from which I cannot glean the basic knowledge > of the roles of controller boards, when they are needed, to what > extent they are interchangable/compatible and whether I would have to > write a driver for it myself. > > Any help appreciatedArticle: 52854
John, You could spend a lot of time doing it yourself, or get it already done for you: http://www.xilinx.com/products/boards/ml300/index.htm Austin John Williams wrote: > Martin wrote: > > > Also I'm looking for an operation system for the hardcore PPC 405 in > > the virtex 2 pro. > > Is there an open source projekt which have ported linux for the PPC > > for the virtex 2 pro? > > Hi Martin, > > Does the PPC in V2pro have an MMU (I think it does?)? If so, you should > be able to get standard PPC linux up and running pretty quickly. This > won't be like installing linux on a PC from a red hat distro, but it's > feasible to get something up and running reasonably quickly. You'll > have to do all the hardware interfacing stuff (interrupts, MMU setup etc > etc). At least the deep kernel source should work unchanged. > > If it does not have an MMU, then you'll need to look into uClinux > (www.uclinux.org). There is no PPC_nommu branch in the uclinux source, > so you'd have to do the port yourself. Not trivial, but a great > learning exercise. I'm busy porting uClinux to the microblaze - I've > just about got a complete kernel image ready to bring into the debugger! > > The two books you simply *must* have for this project are "Understanding > the Linux Kernel" by Bovet & Cesati, and "Linux Device Drivers" by > Rubini & Corbet, both published by O'Reilly. The 2nd one is available > freely as PDFs from somewhere on O'Reailly's website. > > Regards, > > JohnArticle: 52855
I am trying to interface a Virtex2 to an ASIC with very poor clock/data timing. The data coming out of this ASIC is arriving as 8 distinct channels, each with its own frequency (but not phase) related clock. There are too many clocks for me to adjust their phases with DCMs to match the data. I also cannot use global clock buffers for the same reason, but I do not need to drive very many flip-flops, so skew is not an issue. I need to find a way to manually insert delay in my clock line. Inverting the clock does not provide the correct phase relationship. I have tried instantiating some AND2 primitives and placing them in the clock path, but doing this has a seemingly random effect. Does anyone have any ideas on how to do this? Thanks!!! Jeremy Whatley jeremyw@erlangtech.comArticle: 52856
Scott,
I am looking at a USB application myself and the nicest option I found
is the quickUSB option from QuickUSB. They have a daughter card with a
built-in USB 2.0 connection. The card can either go to an altera FPGA or to
a break-out board. We are also using the spartan2e. They use a cypress
chip (EZ-USB). There also a couple of USB source codes in opencores
http://www.opencores.org . If I recall correctly, the full USB core takes a
fairly big FPGA. It sounds like the real object of the project is
compression not USB. Could you live with a standard com port to do the
up-load and down load? I know the time to do the upload/download is
horrible but would that do what you want for the project? If so, there are
several good UARTs out there. (look at Xilinx for a free reliable UART.
XAPP223)
Theron Hicks
"Scott" <scottiecs@yahoo.com> wrote in message
news:ad642abe.0302241334.393e834a@posting.google.com...
> I am new to FPGA's and its programming language VHDL. I am working on
> an electrical engineering senior project and have a few questions.
> 1.) is it possible to connect a USB device (ie a digital camera) to
> the Spartan 2e FPGA? 2.) If it is possible, could someone give a
> quick overview or a good resource for me to research. 3.) If not, any
> good suggestions on how i would go about accomplishing my
> objective(see below)
>
> My main goal is to connect a Digital camera directly to the FPGA board
> to get a picture from the camera. Once the picture is loaded into the
> FPGA memory i am going to compress that image and then send it to a
> computer.
>
> Thanks in advance!!
> Scott
Article: 52857Synopsys owns fe_shell.exe, not Xilinx --- Botaojw_fan@163.com "Muhammad Khan" <kalimuddin@hotmail.com> wrote in message news:7d350237.0302240243.6dc54d65@posting.google.com... > Hi, I am doing project using four Xilinx XCv600 FPGA. I need > fe_shell.exe file. > i am using Xilinx 5.1 foundation series software and there is no > fe_shell.exe file in any of it's folder. > Does any one know or have this file? > Is there is any othee name of this file in version 5.1 as I have seen > this file in version 3.1? > Thanking you in advance > > M.K.KhanArticle: 52858
makmorbi wrote: > > Hi All, > > I am about to write a paper on effects on FPGA's at high temperatures. > One application maybe an oil well where the temperatures are very > high. Can somebody point me to some references or have any thoughts on > that. Would apprectiate it. > > Thanks How High & for how long ? In the ABS MAX ratings, you will find Storage Temp, and Tj (Operating) These are 'long life' ratings, normally ~150'C and ~130'C. You can go above this, at the expense of reduced life / reliability - eg - all parts can survive reflow/solder baths. Better packages will give better lifetimes, and slower thermal slopes will improve reliability. Further up the temp curve, and you will start to re-diffuse the device :) So, any high temp design needs a solid means of 'I'm still OK' verify, and a finite life-time replacement scheme. To get some other ideas on High Temp look at a company that specialises in this area, like http://www.ssec.honeywell.com/hightemp/datasheets.html - jgArticle: 52859
There are some misunderstandings here: For oil exploration, drilling is done to a depth where the rock temperature is well above 150 degree C, up to 200 degree C. Modern oil exploration puts sophisticated instrumentation down these boreholes, including transducers, sensors, A/D converters, microprocessors, memories and, yes, FPGAs. I have helped customers in Texas, France, and Norway with questions about device operation up to 175 degrees C, and many such projects have been very successful, operating for weeks at these elevated temperatures. We do, of course, not guarantee this kind of operation, but the users are very happy that our circuits survive. The drill operators have no choice, they cannot possibly cool down the whole planet. :-) Do a google search on: oil exploration drilling, instrumentation, high-temperature operation, or buzz words like this. I think Schlumberger is the biggest name in that business. Peter Alfke, Xilinx Applications ==================================== Martin Forsberg Lie wrote: > > What do you mean by "high"? I believe the industrial specs for most > components is maximum around +70 deg. C. Are you trying to find a limit for > FPGA technology? I believe (at least the Altera Cyclone family is) some > FPGA's are solved using SRAM technology, so there must be something to find > there. > > However, if I were running an oil plant, I would never exceed temperature > ratings anyway. > > "makmorbi" <m_kochar@yahoo.com> skrev i melding > news:1993b25f.0302191841.4a5d01ee@posting.google.com... > > Hi All, > > > > I am about to write a paper on effects on FPGA's at high temperatures. > > One application maybe an oil well where the temperatures are very > > high. Can somebody point me to some references or have any thoughts on > > that. Would apprectiate it. > > > > ThanksArticle: 52860
I am having a problem in a schematic design.I am using a 8 bit counter output to the address bus of a 256X16 RAM.My basic logic is to search for a given 16bit data in the RAM.I have a increment_counter flag from my controller. I and Increment_counter and Clock and connected it to the clock of the counter.The idea behind is that when increment_counter goes high i should increment the register address.To my dismay whenever the counter is gerting the clock it is incrementing twice.i.e when the counter gets the clock it is going from 00 to 01 at clock first clock pulse and from 01 to 02 at second clock pulse though increment_counter is 0 at the second clock pulse.i couldn't figure out why it is doing like that? --PraveenArticle: 52861
Muzaffer Kal <kal@dspia.com> wrote in message news:<b8nk5v0a6b9rs93oqqll4i8kgrnug4l4s8@4ax.com>... > On 24 Feb 2003 08:46:45 -0800, cvmnk@yahoo.com (naveen) wrote: > > >hi, > > iam using "wait until boolean expression" inside while loop of vhdl > >code to implement a design on fpga virtex 2 fpga chip. > > iam gettin an error:- > > > > ERROR:Xst:825 - D:/changemachine/CONVERT.vhd line 30: Wait > >statement in a procedure is not accepted. > > > > I know that "wiat for" is not synthesisable on fpga, but iam not > >sure abt wiat unitl. > > > > wat shall i do for this problem > > > > thanx > > naveen > > If you're waiting for a condition to change you can just stay in the > same state till it changes. You don't have to use wait. Basically stay > in the same state while your condition is false and go to a different > state when it becomes true. This way wait until is implicit in the > state machine. > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations hi, actually i have to do a synchronous design and my outputs should display for every 1 sec of delay. i can do this using a counter but that would asynchronous design. is there ne other way of gettin delay of 1 sec without using a counter. thanking you, naveenArticle: 52862
You are doing something terrible: you are gating the clock with another signal. As a result you get double clocking. Never, never do that. It is one of the cardinal mistakes in logic design. Connect the clock to the counter directly, and use the increment signal to "count enable" the counter. Peter Alfke ========================== bams wrote: > > I am having a problem in a schematic design.I am using a 8 bit counter > output to the address bus of a 256X16 RAM.My basic logic is to search > for a given 16bit data in the RAM.I have a increment_counter flag > from my controller. I and Increment_counter and Clock and connected it > to the clock of the counter.The idea behind is that when > increment_counter goes high i should increment the register address.To > my dismay whenever the counter is gerting the clock it is > incrementing twice.i.e when the counter gets the clock it is going > from 00 to 01 at clock first clock pulse and from 01 to 02 at second > clock pulse though increment_counter is 0 at the second clock pulse.i > couldn't figure out why it is doing like that? > > --PraveenArticle: 52863
We socketed the config prom and opted not to program it in circuit... so our set up was pretty safe. Another engineer did the prom. I spent more time figuring out how to make my logic correctly write to dual port ram in the Xilinx part, than actually figuring out the PLX device. This was due to my inexperience with that core. We never did get burst mode to work to the dual port rams.... I suspect it was more a problem with the Power PC, not my design, which should handle it. Clyde Andy Peters wrote: > "Clyde R. Shappee" <cshappee@ieee.org> wrote in message news:<3E59435E.FA7EDB6F@ieee.org>... > > Steve, > > > > I did an interface to the PLX9030 and it was straightforward. The hardest > > part was getting the config prom correct, a task which I did not do. > > > > They have a utility to help, but I have never tried it. > > > > If you are in a time crunch, this is the way to go. > > Clyde, > > I did a 9030 design and it was a piece of cake. Getting the config > PROM right was a bit tricky, since if you get it wrong, you may get > stuck in a state where you can't re-program it! The trick was to lift > the data-out pin on the PROM from its pad so the thing would realize > there's no config PROM and it'll start up in its "default" state. > Then you can tie the data-out pin back to the pad and re-program the > PROM. Yowza. > > BTW: I wish PLX would come out with a 66 MHz target-only device. > > The 9030 won't work in this case because it is a target only device. > The ethernet chip probably needs a master to configure it at boot > time. > > A 9052 or 9080 or something like that will work. Of course, you'll > need some logic, or a processor, on the local side of that chip to do > what needs to be done. > > --aArticle: 52865
On Sun, 16 Feb 2003 18:48:19 -0800, Amanda <awynne@controlsystems.com.au> wrote: >>> >>> Amanda posted in HTML, which typically does not work well with news >>> groups. Here it is after clean up. >>> I'm new to all this..... I've built my own parallel port to jtag interface using the Xilinx cct, and it appears to work OK. Using chain debug I can see signals going out on TCK, TDI, and TMS. But never anything coming back on TDO. WebPack 4.2 SP3 crashes on my system (kernel32.dll) so I got jtag programmer 3.3WP8.x. Now I get the following error msg on any function, Loading Boundary-Scan Description Language (BSDL) file 'xc9572.bsd'.....completed successfully. Checking boundary-scan chain integrity...done. Verifying device positions in boundary-scan chain... Verification completed. Boundary-scan chain validated successfully. ERROR:JTag - The boundary-scan based 'program' operation is not supported by the download software on the instance 'PLD2(Device1)'. These operations are currently supported only on Xilinx CPLD and FPGA devices. 'PLD2(Device1)': Programming terminated due to error. PLD2(.jed) is the file I'm trying to program into the device. Any help or pointers greatly appreciated as I'm really stuck. AmandaArticle: 52866
Okay, sorry... :-) Fair enough. I think my point is that ModelSim SE is their top of the line product and that it is expected to significantly out perform their lowest end products. A comparison to the "starter" version is comparing apples and oranges. (Check their web site for details.) For the Windows vs. Linux thing... not gonna get into religious wars. But if you are going there then it makes sense to me that you compare the same product on both OS's on the *same* hardware. IMHO Matt "Duane Clark" <junkmail@junkmail.com> wrote in message news:b3dmpm023qu@enews3.newsguy.com... > Matt wrote: > >>And as a little comparison, I recently ran a simulation of a couple > >>thousand line program on similar machines. A simulation that under > >>Modelsim SE/Linux took 20 seconds, required 30 minutes under Modelsim > >>XE-Starter/Windows 2000! Yikes! > >> > >>... oops, are we not supposed to post benchmarks ;) > > > > > > ModelSim SE (Linux) vs. ModelSim XE-Starter (Win2K)... huh? And what > > Scientific method are claiming to use? > > I don't believe I made any such claim. I merely found a 90 to 1 > difference to be rather astonishing. > > -- > My real email is akamail.com@dclark (or something like that). >Article: 52867
On Mon, 24 Feb 2003 15:59:30 -0600, "Jeremy Whatley" <jeremyw@erlangtech.com> wrote: >I am trying to interface a Virtex2 to an ASIC with very poor clock/data >timing. The data coming out of this ASIC is arriving as 8 distinct >channels, each with its own frequency (but not phase) related clock. There >are too many clocks for me to adjust their phases with DCMs to match the >data. I also cannot use global clock buffers for the same reason, but I do >not need to drive very many flip-flops, so skew is not an issue. > >I need to find a way to manually insert delay in my clock line. Inverting >the clock does not provide the correct phase relationship. I have tried >instantiating some AND2 primitives and placing them in the clock path, but >doing this has a seemingly random effect. Does anyone have any ideas on how >to do this? > >Thanks!!! > >Jeremy Whatley >jeremyw@erlangtech.com > How fast are the clocks coming from the ASIC ? If they are slow enough, you can use them as enables. IOW, sample all the clocks with a high speed internal clock and when you find a 0 to 1 transition on the clock, load the data for that channel. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 52868
Hi all I am trying to implement AMBA AHB interface i have certain dobuts regarding the same 1)How the pipelining of data and address will handle in the design 2) Is there any guidlines available for implementation other than the AHB spec 3) I heard about implementing it using FSM s can anybody give more insights into it Any advices about implemention of AHB Thanks in Advance geoArticle: 52869
Thanks for your input Theron. It looks like we're going to just use the XAPP233 UART from Xilinx and scrap the USB. I have been trying to understand the whole "black box" concept talked about in the XAPP233 application note. To be honest, I am not sure how to do that at all. I understand how to instantiate the UART Tx/Rx in VHDL, but am confused on how to link that VHDL code to the given macros in XAPP233. Since the marcos are EDIF I need to have my project be an EDIF project and not a VHDL project. Im really confused on how this is to be implemented. I dont know if you are famililar with this particular appliation or not, but I would appreciate your thoughts. Thanks again!!! Scott "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:<b3e4ph$2iln$1@msunews.cl.msu.edu>... > Scott, > I am looking at a USB application myself and the nicest option I found > is the quickUSB option from QuickUSB. They have a daughter card with a > built-in USB 2.0 connection. The card can either go to an altera FPGA or to > a break-out board. We are also using the spartan2e. They use a cypress > chip (EZ-USB). There also a couple of USB source codes in opencores > http://www.opencores.org . If I recall correctly, the full USB core takes a > fairly big FPGA. It sounds like the real object of the project is > compression not USB. Could you live with a standard com port to do the > up-load and down load? I know the time to do the upload/download is > horrible but would that do what you want for the project? If so, there are > several good UARTs out there. (look at Xilinx for a free reliable UART. > XAPP223) > > Theron Hicks > > > "Scott" <scottiecs@yahoo.com> wrote in message > news:ad642abe.0302241334.393e834a@posting.google.com... > > I am new to FPGA's and its programming language VHDL. I am working on > > an electrical engineering senior project and have a few questions. > > 1.) is it possible to connect a USB device (ie a digital camera) to > > the Spartan 2e FPGA? 2.) If it is possible, could someone give a > > quick overview or a good resource for me to research. 3.) If not, any > > good suggestions on how i would go about accomplishing my > > objective(see below) > > > > My main goal is to connect a Digital camera directly to the FPGA board > > to get a picture from the camera. Once the picture is loaded into the > > FPGA memory i am going to compress that image and then send it to a > > computer. > > > > Thanks in advance!! > > ScottArticle: 52870
On 24 Feb 2003 12:51:34 -0800, mats_trash@hotmail.com (mat) wrote:
>Sorry if this is the incorrect group
better group is probably comp.arch.embedded
>As a project I've got a motherboard with an LVDS connector, which I
>understand can be used to control an LCD screen.
Right. If this is a direct drive LVDS port, then it is designed
for a specific LCD panel. The full LCD control is local to the
motherboard, and the data on the connector is the RGB data and
timing signals needed by the specific panel. You would see this
type of output on a motherboard designed for embedded
applications, as opposed to a general purpose desktop PC type
motherboard.
If on the other hand, this is a DVI connector (which is always
LVDS too), then this is a generic LCD data port, and it is
designed to drive any LCD panel with a DVI input. In this case
there is considerably more electronics associated with the panel
itself. This is what you would typically find in a desktop type
system. I have never heard of such a desktop motherboard. All
the desktop motherboards that I know of that include any video
logic, are VGA/SVGA/XVGA type outputs, not LVDS or DVI.
>Can I simply
>purchase an LCD screen (small <10") and connect it to this socket and
>it work?
Almost certainly not. You need to find out what the motherboard
was designed to drive.
>Drivers? Alternatively can someone point me to introductory
>material on how to connect LCDs and which also explains the necessary
>components such as the different controller boards.
Driving LCDs directly is not a trivial task. Far better to get
an LCD with driver electronics built in.
Assuming you want to look at prebuilt stuff, my favorite starting
point is:
http://www.pricewatch.com/
start with a search term of "DVI"
>So far I have
>been bewildered by the lack of introductory material and the
>impenetrable information from which I cannot glean the basic knowledge
>of the roles of controller boards,
Takes graphic commands and renders image into a frame buffer.
Reads frame buffer and sends data to panel.
>when they are needed, to what
>extent they are interchangable/compatible and whether I would have to
>write a driver for it myself.
If in a PC environment (WinTel), the OS takes care of most of
this, and you write your program without regard as to whether
the target is an LCD, or a CRT (VGA etc.)
>Any help appreciated
Hope this aims you in the right direction
Philip Freidin
Philip Freidin
Fliptronics
Article: 52871John, > I'm considering the design of a PCI card that will use a fairly big > (400 I/Os, maybe) Xilinx FPGA and a bunch of SRAM to hold images (2D > histograms, actually). There would be a bunch of control registers in > the FPGA, and PCI block transfers to/from the dual-ported image RAM. we have done a similar design: http://www.trenz-electronic.de/pub/xc2s-ad-pci/21270069.jpg http://www.trenz-electronic.de/pub/xc2s-ad-pci/21270071.jpg > The thing is, I'd like to have the PC application code be able to > configure the FPGA for various applications. So the FPGA would likely > not be the actual PCI interface, and would power up un-configured. > > A standard PCI chip, like the AMCC or PLX parts, do the real PCI > interface, with some sort of path (maybe a little glue logic) for > initializing and configuring the FPGA. We do it the same way. We use the PLX PCI9030 and do the configuration with GPIO Lines of the bridge. Depending on the required bandwidth, you should consider using a busmaster capable Bridge. > A second, fix-configured FPGA or CPLD to front-end the big one, ditto. > You don't need this. > Ideas welcome. And if anybody has this all worked out already, we'd > consider buying the IP. If you want to cooperate, please mail me directly. best regards Thorsten -- Dipl.-Ing. Thorsten Trenz Trenz Electronic GmbH, Brendel 20, 32257 Buende, Germany Tel.: +49 (0) 5223 41652, Fax.: +49 (0) 5223 48945 Mailto:t.trenz@trenz-electronic.de, http://www.trenz-electronic.de Amtsgericht Bünde, HR B 1747, Geschäftsführer/CEO: Thorsten TrenzArticle: 52872
Dear John, On Mon, 24 Feb 2003, John Larkin wrote: > Hi, > > I'm considering the design of a PCI card that will use a fairly big > (400 I/Os, maybe) Xilinx FPGA and a bunch of SRAM to hold images (2D > histograms, actually). There would be a bunch of control registers in > the FPGA, and PCI block transfers to/from the dual-ported image RAM. > > The thing is, I'd like to have the PC application code be able to > configure the FPGA for various applications. So the FPGA would likely > not be the actual PCI interface, and would power up un-configured. > > So, any suggestions on an architecture? Some possibilities I've > thought of are... > > A standard PCI chip, like the AMCC or PLX parts, do the real PCI > interface, with some sort of path (maybe a little glue logic) for > initializing and configuring the FPGA. > > A second, fix-configured FPGA or CPLD to front-end the big one, ditto. > > Partial reconfiguration somehow? Like initial config from a EEPOM, > with self-managed reconfig afterwards? Sounds nasty. > > Ideas welcome. And if anybody has this all worked out already, we'd > consider buying the IP. There is an FPGA-based Rapid Prototyping platform available from SPYDER System. However I have no experience with this board and don't know what you must afford for it. You might have a look on their website http://wwwx2e.de/ Kind regards, Lars. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52873
Hi,
I would recommend taking a look at the LEON2 Sparc processor at=20
http://www.gaisler.com/leon.html#Download.
The project is available under the GNU LGPL and contains an AMBA AHB=20
interface.
Best regards,
Mit freundlichen Gr=FC=DFen,
Charles Gardiner
-------------------------------------------------------------
Charles Gardiner, B.E.
Siemens AG
Dept: I&S IT PS 8 SBY
Otto-Hahn-Ring 6
D-81730 Muenchen
Email: mailto:charles.gardiner@siemens.com
Phone: Mobile Office +49 151/1210 1903
Fax : Office +49 89/636 44595
Homepage : https://eda-services.mchp8.siemens.de/gardiner
(Siemens Intranet only)
I&S Homepage: http://www.atd.siemens.de/it-dl/eda
Article: 52874Hi all, I use the Xilinx WebPack (Release 4.2WP2.x - Par E.37) for an SpartanII in my prjekt sometimes say the "Pad Report" from "Place & Route" the SlewRate for the PCI-pads (IO-Standart : PCI33_5) is Slow and this is the "Default value". where can i switch this value permanetly to a fast SlewRate ?? Thanks for Help Erik Spaenig ----- sorry for my terrible english, my favorit language is assembler
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