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Philip Freidin <philip@fliptronics.com> wrote in message news:<1cmd5vobjuqsaiis1gmrdh4lm3pu7dfqo5@4ax.com>... > Time to OUT another TROLL :-) > > On 21 Feb 2003 16:33:13 -0800, jsmithconsultant@hotmail.com (jsmith) wrote: > >I see some new spartan family on my latest Synplicity tools. I hear > >that its on 90nm IBM. Why would anyone try and build a low cost FPGA > >family on an aggressive new process technology? They can't make 0.13um > >VII pro, what hope do they have in building 90nm any time soon. > > What a pointless posting. Too bad Altera doesn't agree - it has become a way of business for them. I heard this same FUD about yield yesterday at lunch from my Altera rep. At least he labelled it FUD rather than trying to mask it like this poster. > So "jsmithconsultant@hotmail.com" has never posted to this news group > before. Actually once, but under a different name (but same IP, and same topic): http://groups.google.com/groups?selm=ac4b1522.0204251747.713ad07d%40posting.google.com Hopefully most Altera employees learn their lessons better than this one. > To the more respectable Altera people who post here, I > believe you make a valuable contribution. Maybe you should > educate others about common courtesy and netiquette. Agreed. Marc Disclaimer: A small part of my portfolio is in Xilinx stock, but that doesn't mean I have a dislike for Altera. If they would drop the price on the Stratix GX, it would win many slots over the VII-Pro with its better high speed I/O support.Article: 52801
Sorry. I should have read Philip's post more carefully. The original post really did come from someone within Altera. My apologies. Bob "Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:9qE5a.1354$4n4.128120@newsread2.prod.itd.earthlink.net... > Philip, > > What's the problem? SpartanIII is a real thing. Also, I believe that the > geometry he's cited is what it really is. > > ??? > > Bob > > > "Philip Freidin" <philip@fliptronics.com> wrote in message > news:1cmd5vobjuqsaiis1gmrdh4lm3pu7dfqo5@4ax.com... > > > > Time to OUT another TROLL :-) > > > > On 21 Feb 2003 16:33:13 -0800, jsmithconsultant@hotmail.com (jsmith) > wrote: > > >I see some new spartan family on my latest Synplicity tools. I hear > > >that its on 90nm IBM. Why would anyone try and build a low cost FPGA > > >family on an aggressive new process technology? They can't make 0.13um > > >VII pro, what hope do they have in building 90nm any time soon. > > > > What a pointless posting. > > > > So "jsmithconsultant@hotmail.com" has never posted to this news group > > before. > > > > This was posted via google-groups to hide identity, but google > > reports the origin IP address. Here is the header of the posting > > (you can look it up for yourself) > > > > >>> Path: > newssvr05.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com! > > >>> nntp.flash.net!iad-peer.news.verio.net!news.verio.net! > > >>> news.maxwell.syr.edu!newsfeed.stanford.edu! > > >>> postnews1.google.com!not-for-mail > > >>> From: jsmithconsultant@hotmail.com (jsmith) > > >>> Newsgroups: comp.arch.fpga > > >>> Subject: spartan III what is it? > > >>> Date: 21 Feb 2003 16:33:13 -0800 > > >>> Organization: http://groups.google.com/ > > >>> Lines: 4 > > >>> Message-ID: <f8039eeb.0302211633.7fdcb50c@posting.google.com> > > >>> NNTP-Posting-Host: 66.35.226.228 > > >>> Content-Type: text/plain; charset=ISO-8859-1 > > >>> Content-Transfer-Encoding: 8bit > > >>> X-Trace: posting.google.com 1045873993 6705 127.0.0.1 (22 Feb 2003 > 00:33:13 GMT) > > >>> X-Complaints-To: groups-abuse@google.com > > >>> NNTP-Posting-Date: 22 Feb 2003 00:33:13 GMT > > >>> Xref: newsmst01.news.prodigy.com comp.arch.fpga:54372 > > > > See that "NNTP-Posting-Host: 66.35.226.228" line, well that tells > > you who sent the posting via google. > > > > Here's what NSLOOKUP has to say about that IP address :-) > > > > === >nslookup 66.35.226.228 > > === Server: dns1.snfcca.sbcglobal.net > > === Address: 206.13.28.12 > > === > > === Name: ip66-35-226-228.altera.com > > === Address: 66.35.226.228 > > > > The 206.13.28.12 is the DNS server I use, but it could have > > been any DNS. > > > > Just trying to keep things clean here. > > > > To the more respectable Altera people who post here, I > > believe you make a valuable contribution. Maybe you should > > educate others about common courtesy and netiquette. > > > > > > > > Philip Freidin > > (and just to make it clean: > > Real Consultant, > > Ex Xilinx employee (exit 1995) > > Keeper and maintainer of the www.fpga-faq.com > > ) > > > > > > =================== > > Philip Freidin > > philip@fliptronics.com > > Host for WWW.FPGA-FAQ.COM > > > > >Article: 52802
David wrote: > Hi, > Does Xilinx offer a free 'Lpm style' function generator? In the ISE web > edition, I can't seem to find anything comparable to what Altera offers for > free. Brand X doesn't talk about LPM functions, but their devices can cover them and synthesis software can pick out matching primitives if you write "LPM style" code. For examples see http://www.edif.org/lpmweb/more/220model.vhd http://www.edif.org/lpmweb/more/verilog.htm -- Mike TreselerArticle: 52803
Hi all, I work in small, development company, and we would like to start some more advanced FPGA designs (we are now using Xilinx FPGAs for simple glue logic only). My question is what tools we need to complete medium sized projects on Spartan IIe & smaller Virtex members. I learned (on Xilinx web site) that ISEbaseX would be OK? Does "one year license" that you buy from Xilinx mean your software stops working after one year, or you just don't have access to updates? If we purchase ModelSim XE does the same license apply? Can we use another VHDL simulator for post place & route simulation? We have, for example, Active VHDL, can we use it? How does XST behave, do we have to buy other synthezis tool to compile anything more advanced? Thanks in advance, Goran.Article: 52804
On 18 Feb 2003 21:01:29 -0800, mrand@my-deja.com (Marc Randolph) wrote: >sri_valli_design@hotmail.com (Valli) wrote in message news:<d9acfecb.0302180820.a6b5174@posting.google.com>... >> hi, >> >> Leonardo is giving different Flop count, if I target same >> design(arround 10K gate) to ASIC technology and FPGA technology. >> >> Please let me what could be the possible reasons! > >Could it be smart enough to duplicate logic (or not) depending on the >situation and timing requirements? Yes,that's possible. It's also possible - and more likely - that the default coding style for enumerations in ASIC is binary coding, but one-hot when targeting FPGA. -- Jonathan BromleyArticle: 52805
If I understand correctly there are not a free function generator incorporated with the ISE webpack? Thanks David "Mike Treseler" <tres@fluke.com> wrote in message news:3E57D05F.5090308@fluke.com... > David wrote: > > Hi, > > Does Xilinx offer a free 'Lpm style' function generator? In the ISE web > > edition, I can't seem to find anything comparable to what Altera offers for > > free. > > > Brand X doesn't talk about LPM functions, but their > devices can cover them and synthesis software > can pick out matching primitives if you > write "LPM style" code. For examples see > > http://www.edif.org/lpmweb/more/220model.vhd > http://www.edif.org/lpmweb/more/verilog.htm > > -- Mike Treseler >Article: 52806
Ken <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote: >> Others might disagree but I suggest ignore the timing summary. Only the >> constraint coverage information is useful. > > OK - so because my contraints gave 99.9% coverage with 0 timing errors - I > can assume that the design will work with the 150MHz master clock and the > 75MHz enabled paths? Well, you should run an unconstrained timing report (trce -u ...) to see what's missing. Probably it will be all the paths from the clk pin to the flip-flops, which you can usually ignore. Possibly I/O as well. For your design, you are fairly safe because if you missed some enabled flip-flops, they would just be constrained for 150 MHz instead of 75 MHz. Cheers Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 52807
"Ryan" <ryans@cat.co.za> wrote in message news:<3e52d5f5.0@obiwan.eastcoast.co.za>... > Hi > > Does anybody know of any books or papers that discuss synthesis and > execution efficiency as a function of HDL code layout? The reason I am > asking this is that there must be ways of improving LE allocation by setting > your code out in different manners. Normally there are several ways to write > a piece of code to perform a specific operation. Which ways are better than > others? I think all HDL programmers should be interested in this type of > topic. > > Any thoughts or pointers?? > > Ryan Most synthesis tools for FPGAs come with guides as how to efficiently code for a specific FPGA. I believe Xilinx had several white papers on their web site that would give quite a few hints. I did not see anything specific to code partitioning. I think this is most of the time left up to the synthesis tool, as it has to minimize and optimize the logic first anyway, it should be able to break it up most efficiently as well. Cheers ! rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 52808
"Gary Partis" <gary.partis@comodogroup.com> wrote in message news:<PRTS41386E012E@partis.org>... > Does anyone have any experience of Inventra/Mentor USB function controller > IP? > > More specifically, has anyone had any problems with servicing interrupts too > fast (!!!) and/or problems receiving extra data on endpoint zero (ie. > packets with data out phases). > > Thanks in advance, > > Gary Partis No, unfortunately not. But the Free OpenCores USB Function IP core works just fine in a Spartan FPGA. Had it running for quite some time now, not problems so far ! Cheers ! rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 52809
David <gretzteam@hotmail.com> wrote: : If I understand correctly there are not a free function generator : incorporated with the ISE webpack? : Thanks : David Ise has a function generator, (free) webpack has not Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52810
"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:<s8u5a.200250$HN5.852479@rwcrnsc51.ops.asp.att.net>... > "Jacky Renaux" <renaux.jacky@wanadoo.fr> wrote in message > news:2003215-192937-894018@foorum.com... > > > > oes somebody can give me where I can found details > > on end-around-carry function which is recommended > > for modulo (2^n)-1 conversion ? > > > > This is normally a property of ones-complement arithmetic, so any references > to that should do. > > As far as FPGA implementations, it would have to come through general > routing instead of fast carry logic on the architectures I know about. > Just take the carry out from the MSB and use it as the carry in for the LSB. > > -- glen I glen I do agree you are rigth , but my concern is on fpga implementation on one level as far I undestood : en-around-carry is a function with the carry out goes back to the next stage carry in. this implies : 2 stages pipeline and 2 zeroes (zero+ and zero-) such function is used in modulo 2n-1 arithmetic my questions to the group were : Am I right ? is there any other modulo 2n-1 implementations ? does somebody knows papers to read on such subject ? I am presently implementing a RNS based dsp functions and selected 2n+1,2n and 2n-1 modulus arithmetics thanks jackyArticle: 52811
Hello, Kresten, Contact the guys at www.timingtool.com - I shall continue to persuade them that this is a worthwhile avenue to explore; added weight to a request for VHDL generation from timing diagrams is more than welcome! Producing state machine-based VHDL appropriate for synthesis from timing diagram input is not an easy task, but the method has merit and is automatable. I have used this approach for both testbench generation and RTL design for a few years. My own automation approach is based upon powerpoint (for timing diagram definition) & VBA (for code generation) but requires more user intervention than I'd like. If a >>high-level<< timing definition & code-generation tool (ie, based upon TDML and VHDL) was commercially available, I'd buy it! Tim. On Sat, 22 Feb 2003 08:57:24 +0100, "Kresten Nørgaard" <kresten_noergaard@ddf.dk> wrote: >Does anyone know of a FPGA design tool, that takes timing diagrams as an >input, and produces VHDL (or something else) as an output? > >Kresten > >Article: 52812
Hello, Im programming an FPGA Virtex-E using Verilog HDL. I have used a RAM from Coregen and I instantiate it after defining data types: lut512 lutPI ( .ADDR(addr), .CLK(clk_PIPQ), .DI(PI), .WE(we_PIPQ), .DO(PId)); The question is: Can I generate a rising edge for a clk that feeds a RAM inside an always loop? Like that: always@(posege clk_index) begin we_PIPQ=0; //set LUT to read clk_PIPQ=0; clk_PIPQ=1;//Rising clk, We get PId PI=PId*V; we_PIPQ=1; //set LUT to write clk_PIPQ=0; clk_PIPQ=1;//After the rising edge, PI is written into the LUT end I have tried it and it works like the clock clk_PIPQ didnt move at all. I understand that it only cares for the ultimate value of clk_PIPQ inside the always loop. If I cant do that, How can I generate a rising clock so that I get PId and make operations with it? Thanks for your time, I appreciate your help. LauraArticle: 52813
Ryan wrote: > Hi > > Does anybody know of any books or papers that discuss synthesis and > execution efficiency as a function of HDL code layout? The reason I am > asking this is that there must be ways of improving LE allocation by setting > your code out in different manners. Normally there are several ways to write > a piece of code to perform a specific operation. Which ways are better than > others? I think all HDL programmers should be interested in this type of > topic. > > Any thoughts or pointers?? Any such book would be out of date as soon as it was published. Device primitives, synthesis strategies and the definition of design "efficiency" are moving targets. For maximum utilization or speed, consider instancing device-specific modules. For some FPGA users, the latest devices are already big/fast/cheap enough that synthesis output is more than good enough and the effect of coding style is insignificant. In these cases, code for clarity. -- Mike TreselerArticle: 52814
Tim Pagden wrote: > Producing state machine-based VHDL appropriate for synthesis from timing diagram > input is not an easy task, but the method has merit and is automatable. I have > used this approach for both testbench generation and RTL design for a few years. > > My own automation approach is based upon powerpoint (for timing diagram > definition) & VBA (for code generation) but requires more user intervention than > I'd like. If a >>high-level<< timing definition & code-generation tool (ie, > based upon TDML and VHDL) was commercially available, I'd buy it! I guess there's more than one way to synthesize a module, but I'll stick to entering text for a synchronous process and a case statement over drawing many microseconds of waveforms. A little more text for a testbench, and the simulator will draw the waveforms all by itself. -- Mike TreselerArticle: 52815
In a CSA architecture with three inputs (U , V and W), there are two stages. First stage combines u(i), v(i) and w(i) to generate s(i) and c(i+i). Next stage combines S (s(i)s) and C (c(i)s) using a carry chain to generate the final sum. Now s(i) and c(i) are a function of 6 variables (u(i), v(i), w(i), u(i-1), v(i-1) and w(i-1)). As a LUT has only 4 inputs it is impossible to fit all the logic into one LUT. However if you know oen of the inputs (U, V or W) is a constant the number of variables driving c(i) and s(i) reduces to 4 and then the CSA can be implemented using one carry chain and no extra LUTs. Regards, Ashish Kapoor _____________________________________________________________________________ Lars Unger <larsu@ida.ing.tu-bs.de> wrote in message news:<Pine.LNX.4.50.0302081057490.5385-100000@wichtel.ida.ing.tu-bs.de>... > On Fri, 7 Feb 2003, Ray Andraka wrote: > > Not without using or blocking the second half of the slice. What is the > > motivation for doing a carry save adder here? The ripple carry arithmetic uses > > half the area (because of the carry chain logic) and a tree made of FPGA ripple > > carry adds is faster than one made of carry save adds because of the hit you take > > on the routing. See my multipliers page on my website for a bit more detail (under > > wallace tree multipliers). > > I implement an algorithm for a modular multiplication. Unfortunately this > algorithm depends highly on the use of a Carry-Save-Adder. As I have to prove > the case for the algorithm, there is no way out :) > > Best wishes, > Lars.Article: 52816
On 22 Feb 2003 12:15:47 -0800, goran@net.yu (Goran) wrote: >Hi all, >I work in small, development company, and we would like to start some >more advanced FPGA designs (we are now using Xilinx FPGAs for simple >glue logic only). My question is what tools we need to complete medium >sized projects on Spartan IIe & smaller Virtex members. >I learned (on Xilinx web site) that ISEbaseX would be OK? Yup. Does all but the largest (Virtex) parts. >Does "one year license" that you buy from Xilinx mean your software >stops working after one year, or you just don't have access to >updates? The way I read it, after one year, you get to buy the software again. Which (IMnsHO) really sucks. At least one of my clients is designing Xilinx out because of tool issues. >If we purchase ModelSim XE does the same license apply? That depends. Look carefully at the license file. Call your Xilinx rep and ask. >Can we use another VHDL simulator for post place & route simulation? >We have, for example, Active VHDL, can we use it? Personally, I would use ActiveVHDL for pre-route simulation, and use vendor-supplied tools for post-route. >How does XST behave, do we have to buy other synthezis tool to compile >anything more advanced? XST works real well. At least as well as Foundation (which it replaces) and perhaps better. >Thanks in advance, >Goran. Contact me by EMail if you want to chat. You're doing exactly what the above mentioned client is doing.Article: 52817
Steve, I did an interface to the PLX9030 and it was straightforward. The hardest part was getting the config prom correct, a task which I did not do. They have a utility to help, but I have never tried it. If you are in a time crunch, this is the way to go. Also, do I remember correctly that there may be a quick hack in K. C. Changs text on VHDL? Clyde Steve T Shannon wrote: > > You will need to provide more details, but from what you wrote, it > > sounds to me what you are trying to do is to convert some kind of bus > > protocol to PCI's protocol. > Well, at the moment I've got a data bus and an event bus in my > device. I had originally planned on using one of SMSC's 100mbit > ethernet MAC/PHY combos (really nice little chips) which would have > allowed me to essentially just clock in and clock out ethernet frames. > > > If someone has already developed such a bridge chip (an ASSP), you > > should use that instead of developing one from scratch. > > Well, so PLX appears to have developed some bridges that would at > least make things slightly easier. However, 1. they are not cheap (and > I'm on a bit of a budget for total project cost) and 2. I fear that > figuring out how to interface them to the device and then interface > them to my side of things will take just as long as developing the PCI > IO myself. > > > else.), and how many people will be working on this project (It's nice > > to let someone else do the testbench because the circuit designer > > won't want to work on the testbench.). > It's just me here. It looks like it's going to be a long weekend > ahead... > > > Since your PCI bridge is going to have a point-to-point > > connection to the PCI gigabit ethernet chip, you might be able to > > relax the standard setup time of 7ns for 33MHz PCI and 3ns for 66MHz > > PCI to 10ns and 5ns, respectively, although no such timing parameters > > are officially defined by the PCI specification. > Okay, I'm looking at 32-bit 33 MHz. I care less about developing a > reusable PCI IP core and more about getting a self-contained MAC > interface. > > > Considering the complexity of PCI, and the trouble of writing > > the testbench code, anyone smart enough to develop a PCI interface has > > turned into a business (I am thinking of doing that, too.). > I've noticed that, perhaps I should take it as a hint. > > > Other than Opencores.org PCI IP core > > (http://www.opencores.org/projects/pci/), there aren't too many free > > or open source designs related to PCI. > I've had a bit of difficulty figuring out exactly how their core > works, although that might just be because I'm a VHDL guy. > > > If you have to develop a PCI bridge from scratch, obtain a copy of the > > PCI specification, and take a look at Appendix B of it. > > Appendix B has an example target and initiator state machine, and that > > should be your starting point. > Actually I found one on the web -- thank you google! > > > You should never try to copy the entire Appendix B because if you do > > so, you will see signal glitches coming out of the chip, and several > > protocol rules aren't being followed in the Appendix B example. > Could you maybe give a bit more insight into this? What if I > register the outputs? > > > Steve, does your project have to deal with 5V PCI? > > If that's the case, you will have to use the older Spartan-II instead > > because Spartan-IIE doesn't support 5V PCI, although 3.3V PCI is still > > supported. > Nope, just 3.3v on this IC. The data sheet appears to give pretty > reasonable explanation of how the PCI IO works for the device... > http://www.national.com/ds/DP/DP83820.pdf seems to suggest there might > be some places where I can cut corners. > > I'm also curious about how people implemented things like FIFOs > when they developed their interfaces. I've been spoiled before, always > doing FIFOs in spartan-II blockselect+ ram blocks, which are dual > ported. But it would seem that to get a decent-size (say, 256 KB) FIFO > in dual-ported ram would be really expensive, and so I need to go with > standard (although cheap!) SRAM. I've been thinking about clocking the > actual FPGA at 66 MHz and interleaving FIFO read-write access. Might > anyone have had any experience with this sort of thing ? > > Thanks again for all the help, > > SteveArticle: 52818
Goran,
Which Xilinx part are you planning to target?
As long as you are targeting Xilinx devices below 300K system gates or
you don't have to target a 2.5V Virtex device, you may want to try the
free ISE WebPACK first before paying for ISE BASE-X.
Unlike ISE BASE-X users, ISE WebPACK users won't have access to FPGA
Editor or CORE Generator, but if those tools aren't important to you,
you should be fine with ISE WebPACK.
Regarding ModelSim XE, you may want to try ModelSim XE-Starter
first before paying for ModelSim XE.
Yes, ModelSim XE-Starter has a 500 statements limit, but what that
really means is that the simulation speed will drop after that limit,
and the simulator will still continue to run past that limit.
In the past, I have simulated a design that exceeded the 500
statements limitation by 40,000 lines, but ModelSim XE-Starter
completed the simulation fine.
However, it took quite a time to complete because I was doing a Post
P&R simulation of a design, and a Post P&R simulation is inherently
very slow compared to an RTL simulation.
I also agree with Spam Hater that XST's synthesis quality is
good, so unless you don't mind paying $8,000 for a third party
synthesis tool, I will just use XST.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
goran@net.yu (Goran) wrote in message news:<3c0f6336.0302221215.1ab0ed0d@posting.google.com>...
> Hi all,
> I work in small, development company, and we would like to start some
> more advanced FPGA designs (we are now using Xilinx FPGAs for simple
> glue logic only). My question is what tools we need to complete medium
> sized projects on Spartan IIe & smaller Virtex members.
> I learned (on Xilinx web site) that ISEbaseX would be OK?
> Does "one year license" that you buy from Xilinx mean your software
> stops working after one year, or you just don't have access to
> updates?
> If we purchase ModelSim XE does the same license apply?
> Can we use another VHDL simulator for post place & route simulation?
> We have, for example, Active VHDL, can we use it?
> How does XST behave, do we have to buy other synthezis tool to compile
> anything more advanced?
> Thanks in advance,
> Goran.
Article: 52819Kevin Brace wrote: > ... > Regarding ModelSim XE, you may want to try ModelSim XE-Starter > first before paying for ModelSim XE. > Yes, ModelSim XE-Starter has a 500 statements limit, but what that > really means is that the simulation speed will drop after that limit, > and the simulator will still continue to run past that limit. > In the past, I have simulated a design that exceeded the 500 > statements limitation by 40,000 lines, but ModelSim XE-Starter > completed the simulation fine. > However, it took quite a time to complete because I was doing a Post > P&R simulation of a design, and a Post P&R simulation is inherently > very slow compared to an RTL simulation. And as a little comparison, I recently ran a simulation of a couple thousand line program on similar machines. A simulation that under Modelsim SE/Linux took 20 seconds, required 30 minutes under Modelsim XE-Starter/Windows 2000! Yikes! ... oops, are we not supposed to post benchmarks ;) -- My real email is akamail.com@dclark (or something like that).Article: 52822
From what I learn, you can eliminate Static 1 hazard by circle-ing minterm including the redundant one. You can eliminate static 0 hazard by circle-ing the maxterm including the redundant one. But is there any way that I can eliminate both static 1 and static 0 hazard without creating seperate circuits for each hazard?Article: 52823
hi,
iam using "wait until boolean expression" inside while loop of vhdl
code to implement a design on fpga virtex 2 fpga chip.
iam gettin an error:-
ERROR:Xst:825 - D:/changemachine/CONVERT.vhd line 30: Wait
statement in a procedure is not accepted.
wat shall i do for this problem
thanx
naveen
Article: 52824I want to know how to interface a keyboard to xilinx fpga(spartan xcs10pc84) board.? --bams
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